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1 | // Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M) |
2 | // | |
3 | // This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single | |
4 | // precision) floating point operations to hardware instructions. | |
5 | // | |
6 | // Additionally, this target uses the "hard" floating convention (ABI) where floating point values | |
7 | // are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.). | |
8 | // | |
9 | // To opt into double precision hardware support, use the `-C target-feature=+fp64` flag. | |
10 | ||
11 | use crate::spec::{Target, TargetOptions}; | |
12 | ||
13 | pub fn target() -> Target { | |
14 | Target { | |
15 | llvm_target: "thumbv7em-none-eabihf".to_string(), | |
16 | pointer_width: 32, | |
17 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(), | |
18 | arch: "arm".to_string(), | |
19 | ||
20 | options: TargetOptions { | |
21 | // `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the | |
22 | // Cortex-M7 (vfp5) | |
23 | // `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers | |
24 | // available | |
25 | // `-fp64` The Cortex-M4 only supports single precision floating point operations | |
26 | // whereas in the Cortex-M7 double precision is optional | |
27 | // | |
28 | // Reference: | |
29 | // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension | |
30 | features: "+vfp4,-d32,-fp64".to_string(), | |
31 | max_atomic_width: Some(32), | |
32 | ..super::thumb_base::opts() | |
33 | }, | |
34 | } | |
35 | } |