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53e72406 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/cpu.h> | |
53e72406 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
b452cb52 | 23 | #include <linux/irq.h> |
53e72406 | 24 | |
372b7c1b | 25 | #include <clocksource/arm_arch_timer.h> |
53e72406 | 26 | #include <asm/arch_timer.h> |
488f94d7 | 27 | #include <asm/kvm_hyp.h> |
53e72406 | 28 | |
7275acdf MZ |
29 | #include <kvm/arm_vgic.h> |
30 | #include <kvm/arm_arch_timer.h> | |
53e72406 | 31 | |
e21f0910 CD |
32 | #include "trace.h" |
33 | ||
53e72406 | 34 | static struct timecounter *timecounter; |
5ae7f87a | 35 | static unsigned int host_vtimer_irq; |
cabdc5c5 | 36 | static u32 host_vtimer_irq_flags; |
53e72406 | 37 | |
9b4a3004 MZ |
38 | void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) |
39 | { | |
fbb4aeec | 40 | vcpu_vtimer(vcpu)->active_cleared_last = false; |
9b4a3004 MZ |
41 | } |
42 | ||
7b6b4631 | 43 | u64 kvm_phys_timer_read(void) |
53e72406 MZ |
44 | { |
45 | return timecounter->cc->read(timecounter->cc); | |
46 | } | |
47 | ||
48 | static bool timer_is_armed(struct arch_timer_cpu *timer) | |
49 | { | |
50 | return timer->armed; | |
51 | } | |
52 | ||
53 | /* timer_arm: as in "arm the timer", not as in ARM the company */ | |
54 | static void timer_arm(struct arch_timer_cpu *timer, u64 ns) | |
55 | { | |
56 | timer->armed = true; | |
57 | hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns), | |
58 | HRTIMER_MODE_ABS); | |
59 | } | |
60 | ||
61 | static void timer_disarm(struct arch_timer_cpu *timer) | |
62 | { | |
63 | if (timer_is_armed(timer)) { | |
64 | hrtimer_cancel(&timer->timer); | |
65 | cancel_work_sync(&timer->expired); | |
66 | timer->armed = false; | |
67 | } | |
68 | } | |
69 | ||
53e72406 MZ |
70 | static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id) |
71 | { | |
72 | struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id; | |
73 | ||
74 | /* | |
75 | * We disable the timer in the world switch and let it be | |
76 | * handled by kvm_timer_sync_hwstate(). Getting a timer | |
77 | * interrupt at this point is a sure sign of some major | |
78 | * breakage. | |
79 | */ | |
80 | pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu); | |
81 | return IRQ_HANDLED; | |
82 | } | |
83 | ||
1a748478 CD |
84 | /* |
85 | * Work function for handling the backup timer that we schedule when a vcpu is | |
86 | * no longer running, but had a timer programmed to fire in the future. | |
87 | */ | |
53e72406 MZ |
88 | static void kvm_timer_inject_irq_work(struct work_struct *work) |
89 | { | |
90 | struct kvm_vcpu *vcpu; | |
91 | ||
92 | vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired); | |
1c5631c7 | 93 | |
1a748478 CD |
94 | /* |
95 | * If the vcpu is blocked we want to wake it up so that it will see | |
96 | * the timer has expired when entering the guest. | |
97 | */ | |
98 | kvm_vcpu_kick(vcpu); | |
53e72406 MZ |
99 | } |
100 | ||
9171fa2e | 101 | static u64 kvm_timer_compute_delta(struct arch_timer_context *timer_ctx) |
1c5631c7 | 102 | { |
a5a1d1c2 | 103 | u64 cval, now; |
1c5631c7 | 104 | |
9171fa2e JL |
105 | cval = timer_ctx->cnt_cval; |
106 | now = kvm_phys_timer_read() - timer_ctx->cntvoff; | |
1c5631c7 MZ |
107 | |
108 | if (now < cval) { | |
109 | u64 ns; | |
110 | ||
111 | ns = cyclecounter_cyc2ns(timecounter->cc, | |
112 | cval - now, | |
113 | timecounter->mask, | |
114 | &timecounter->frac); | |
115 | return ns; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
fb280e97 JL |
121 | static bool kvm_timer_irq_can_fire(struct arch_timer_context *timer_ctx) |
122 | { | |
123 | return !(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) && | |
124 | (timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_ENABLE); | |
125 | } | |
126 | ||
127 | /* | |
128 | * Returns the earliest expiration time in ns among guest timers. | |
129 | * Note that it will return 0 if none of timers can fire. | |
130 | */ | |
131 | static u64 kvm_timer_earliest_exp(struct kvm_vcpu *vcpu) | |
132 | { | |
133 | u64 min_virt = ULLONG_MAX, min_phys = ULLONG_MAX; | |
134 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); | |
135 | struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); | |
136 | ||
137 | if (kvm_timer_irq_can_fire(vtimer)) | |
138 | min_virt = kvm_timer_compute_delta(vtimer); | |
139 | ||
140 | if (kvm_timer_irq_can_fire(ptimer)) | |
141 | min_phys = kvm_timer_compute_delta(ptimer); | |
142 | ||
143 | /* If none of timers can fire, then return 0 */ | |
144 | if ((min_virt == ULLONG_MAX) && (min_phys == ULLONG_MAX)) | |
145 | return 0; | |
146 | ||
147 | return min(min_virt, min_phys); | |
148 | } | |
149 | ||
53e72406 MZ |
150 | static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt) |
151 | { | |
152 | struct arch_timer_cpu *timer; | |
1c5631c7 MZ |
153 | struct kvm_vcpu *vcpu; |
154 | u64 ns; | |
155 | ||
53e72406 | 156 | timer = container_of(hrt, struct arch_timer_cpu, timer); |
1c5631c7 MZ |
157 | vcpu = container_of(timer, struct kvm_vcpu, arch.timer_cpu); |
158 | ||
159 | /* | |
160 | * Check that the timer has really expired from the guest's | |
161 | * PoV (NTP on the host may have forced it to expire | |
162 | * early). If we should have slept longer, restart it. | |
163 | */ | |
fb280e97 | 164 | ns = kvm_timer_earliest_exp(vcpu); |
1c5631c7 MZ |
165 | if (unlikely(ns)) { |
166 | hrtimer_forward_now(hrt, ns_to_ktime(ns)); | |
167 | return HRTIMER_RESTART; | |
168 | } | |
169 | ||
3706feac | 170 | schedule_work(&timer->expired); |
53e72406 MZ |
171 | return HRTIMER_NORESTART; |
172 | } | |
173 | ||
9171fa2e | 174 | bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx) |
1a748478 | 175 | { |
a5a1d1c2 | 176 | u64 cval, now; |
1a748478 | 177 | |
9171fa2e | 178 | if (!kvm_timer_irq_can_fire(timer_ctx)) |
1a748478 CD |
179 | return false; |
180 | ||
9171fa2e JL |
181 | cval = timer_ctx->cnt_cval; |
182 | now = kvm_phys_timer_read() - timer_ctx->cntvoff; | |
1a748478 CD |
183 | |
184 | return cval <= now; | |
185 | } | |
186 | ||
9171fa2e JL |
187 | static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, |
188 | struct arch_timer_context *timer_ctx) | |
4b4b4512 CD |
189 | { |
190 | int ret; | |
4b4b4512 | 191 | |
9171fa2e JL |
192 | timer_ctx->active_cleared_last = false; |
193 | timer_ctx->irq.level = new_level; | |
194 | trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, | |
195 | timer_ctx->irq.level); | |
11710dec | 196 | |
9171fa2e JL |
197 | ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, timer_ctx->irq.irq, |
198 | timer_ctx->irq.level); | |
4b4b4512 CD |
199 | WARN_ON(ret); |
200 | } | |
201 | ||
202 | /* | |
203 | * Check if there was a change in the timer state (should we raise or lower | |
204 | * the line level to the GIC). | |
205 | */ | |
b22e7df2 | 206 | static void kvm_timer_update_state(struct kvm_vcpu *vcpu) |
4b4b4512 CD |
207 | { |
208 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
fbb4aeec | 209 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
58e0c973 | 210 | struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); |
4b4b4512 CD |
211 | |
212 | /* | |
213 | * If userspace modified the timer registers via SET_ONE_REG before | |
fbb4aeec | 214 | * the vgic was initialized, we mustn't set the vtimer->irq.level value |
4b4b4512 CD |
215 | * because the guest would never see the interrupt. Instead wait |
216 | * until we call this function from kvm_timer_flush_hwstate. | |
217 | */ | |
b22e7df2 CD |
218 | if (!timer->enabled) |
219 | return; | |
4b4b4512 | 220 | |
9171fa2e JL |
221 | if (kvm_timer_should_fire(vtimer) != vtimer->irq.level) |
222 | kvm_timer_update_irq(vcpu, !vtimer->irq.level, vtimer); | |
b3aff6cc | 223 | |
58e0c973 JL |
224 | if (kvm_timer_should_fire(ptimer) != ptimer->irq.level) |
225 | kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer); | |
4b4b4512 CD |
226 | } |
227 | ||
f242adaf JL |
228 | /* Schedule the background timer for the emulated timer. */ |
229 | static void kvm_timer_emulate(struct kvm_vcpu *vcpu, | |
230 | struct arch_timer_context *timer_ctx) | |
231 | { | |
232 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
233 | ||
234 | if (kvm_timer_should_fire(timer_ctx)) | |
235 | return; | |
236 | ||
237 | if (!kvm_timer_irq_can_fire(timer_ctx)) | |
238 | return; | |
239 | ||
240 | /* The timer has not yet expired, schedule a background timer */ | |
241 | timer_arm(timer, kvm_timer_compute_delta(timer_ctx)); | |
242 | } | |
243 | ||
d35268da CD |
244 | /* |
245 | * Schedule the background timer before calling kvm_vcpu_block, so that this | |
246 | * thread is removed from its waitqueue and made runnable when there's a timer | |
247 | * interrupt to handle. | |
248 | */ | |
249 | void kvm_timer_schedule(struct kvm_vcpu *vcpu) | |
250 | { | |
251 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
9171fa2e | 252 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
fb280e97 | 253 | struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); |
d35268da CD |
254 | |
255 | BUG_ON(timer_is_armed(timer)); | |
256 | ||
257 | /* | |
fb280e97 | 258 | * No need to schedule a background timer if any guest timer has |
d35268da CD |
259 | * already expired, because kvm_vcpu_block will return before putting |
260 | * the thread to sleep. | |
261 | */ | |
fb280e97 | 262 | if (kvm_timer_should_fire(vtimer) || kvm_timer_should_fire(ptimer)) |
d35268da CD |
263 | return; |
264 | ||
265 | /* | |
fb280e97 | 266 | * If both timers are not capable of raising interrupts (disabled or |
d35268da CD |
267 | * masked), then there's no more work for us to do. |
268 | */ | |
fb280e97 | 269 | if (!kvm_timer_irq_can_fire(vtimer) && !kvm_timer_irq_can_fire(ptimer)) |
d35268da CD |
270 | return; |
271 | ||
fb280e97 JL |
272 | /* |
273 | * The guest timers have not yet expired, schedule a background timer. | |
274 | * Set the earliest expiration time among the guest timers. | |
275 | */ | |
276 | timer_arm(timer, kvm_timer_earliest_exp(vcpu)); | |
d35268da CD |
277 | } |
278 | ||
279 | void kvm_timer_unschedule(struct kvm_vcpu *vcpu) | |
280 | { | |
281 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
282 | timer_disarm(timer); | |
283 | } | |
284 | ||
53e72406 MZ |
285 | /** |
286 | * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu | |
287 | * @vcpu: The vcpu pointer | |
288 | * | |
d35268da CD |
289 | * Check if the virtual timer has expired while we were running in the host, |
290 | * and inject an interrupt if that was the case. | |
53e72406 MZ |
291 | */ |
292 | void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) | |
293 | { | |
b22e7df2 | 294 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; |
fbb4aeec | 295 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
cff9211e CD |
296 | bool phys_active; |
297 | int ret; | |
53e72406 | 298 | |
b22e7df2 | 299 | if (unlikely(!timer->enabled)) |
b3aff6cc | 300 | return; |
cff9211e | 301 | |
b22e7df2 CD |
302 | kvm_timer_update_state(vcpu); |
303 | ||
f242adaf JL |
304 | /* Set the background timer for the physical timer emulation. */ |
305 | kvm_timer_emulate(vcpu, vcpu_ptimer(vcpu)); | |
306 | ||
cff9211e | 307 | /* |
0e3dfda9 CD |
308 | * If we enter the guest with the virtual input level to the VGIC |
309 | * asserted, then we have already told the VGIC what we need to, and | |
310 | * we don't need to exit from the guest until the guest deactivates | |
311 | * the already injected interrupt, so therefore we should set the | |
312 | * hardware active state to prevent unnecessary exits from the guest. | |
313 | * | |
314 | * Also, if we enter the guest with the virtual timer interrupt active, | |
315 | * then it must be active on the physical distributor, because we set | |
316 | * the HW bit and the guest must be able to deactivate the virtual and | |
317 | * physical interrupt at the same time. | |
318 | * | |
319 | * Conversely, if the virtual input level is deasserted and the virtual | |
320 | * interrupt is not active, then always clear the hardware active state | |
321 | * to ensure that hardware interrupts from the timer triggers a guest | |
322 | * exit. | |
323 | */ | |
fbb4aeec JL |
324 | phys_active = vtimer->irq.level || |
325 | kvm_vgic_map_is_active(vcpu, vtimer->irq.irq); | |
cff9211e | 326 | |
9b4a3004 MZ |
327 | /* |
328 | * We want to avoid hitting the (re)distributor as much as | |
329 | * possible, as this is a potentially expensive MMIO access | |
330 | * (not to mention locks in the irq layer), and a solution for | |
331 | * this is to cache the "active" state in memory. | |
332 | * | |
333 | * Things to consider: we cannot cache an "active set" state, | |
334 | * because the HW can change this behind our back (it becomes | |
335 | * "clear" in the HW). We must then restrict the caching to | |
336 | * the "clear" state. | |
337 | * | |
338 | * The cache is invalidated on: | |
339 | * - vcpu put, indicating that the HW cannot be trusted to be | |
340 | * in a sane state on the next vcpu load, | |
341 | * - any change in the interrupt state | |
342 | * | |
343 | * Usage conditions: | |
344 | * - cached value is "active clear" | |
345 | * - value to be programmed is "active clear" | |
346 | */ | |
fbb4aeec | 347 | if (vtimer->active_cleared_last && !phys_active) |
9b4a3004 MZ |
348 | return; |
349 | ||
b452cb52 | 350 | ret = irq_set_irqchip_state(host_vtimer_irq, |
cff9211e CD |
351 | IRQCHIP_STATE_ACTIVE, |
352 | phys_active); | |
353 | WARN_ON(ret); | |
9b4a3004 | 354 | |
fbb4aeec | 355 | vtimer->active_cleared_last = !phys_active; |
53e72406 MZ |
356 | } |
357 | ||
358 | /** | |
359 | * kvm_timer_sync_hwstate - sync timer state from cpu | |
360 | * @vcpu: The vcpu pointer | |
361 | * | |
d35268da CD |
362 | * Check if the virtual timer has expired while we were running in the guest, |
363 | * and inject an interrupt if that was the case. | |
53e72406 MZ |
364 | */ |
365 | void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) | |
366 | { | |
367 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
53e72406 | 368 | |
f242adaf JL |
369 | /* |
370 | * This is to cancel the background timer for the physical timer | |
371 | * emulation if it is set. | |
372 | */ | |
373 | timer_disarm(timer); | |
53e72406 | 374 | |
4b4b4512 CD |
375 | /* |
376 | * The guest could have modified the timer registers or the timer | |
377 | * could have expired, update the timer state. | |
378 | */ | |
379 | kvm_timer_update_state(vcpu); | |
53e72406 MZ |
380 | } |
381 | ||
f120cd65 | 382 | int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, |
a91d1855 JL |
383 | const struct kvm_irq_level *virt_irq, |
384 | const struct kvm_irq_level *phys_irq) | |
5ae7f87a | 385 | { |
fbb4aeec | 386 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
a91d1855 | 387 | struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); |
5ae7f87a AP |
388 | |
389 | /* | |
390 | * The vcpu timer irq number cannot be determined in | |
391 | * kvm_timer_vcpu_init() because it is called much before | |
392 | * kvm_vcpu_set_target(). To handle this, we determine | |
393 | * vcpu timer irq number when the vcpu is reset. | |
394 | */ | |
a91d1855 JL |
395 | vtimer->irq.irq = virt_irq->irq; |
396 | ptimer->irq.irq = phys_irq->irq; | |
f120cd65 | 397 | |
4ad9e16a CD |
398 | /* |
399 | * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8 | |
400 | * and to 0 for ARMv7. We provide an implementation that always | |
401 | * resets the timer to be disabled and unmasked and is compliant with | |
402 | * the ARMv7 architecture. | |
403 | */ | |
fbb4aeec | 404 | vtimer->cnt_ctl = 0; |
a91d1855 | 405 | ptimer->cnt_ctl = 0; |
4b4b4512 | 406 | kvm_timer_update_state(vcpu); |
4ad9e16a | 407 | |
41a54482 | 408 | return 0; |
5ae7f87a AP |
409 | } |
410 | ||
90de943a JL |
411 | /* Make the updates of cntvoff for all vtimer contexts atomic */ |
412 | static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) | |
413 | { | |
414 | int i; | |
415 | struct kvm *kvm = vcpu->kvm; | |
416 | struct kvm_vcpu *tmp; | |
417 | ||
418 | mutex_lock(&kvm->lock); | |
419 | kvm_for_each_vcpu(i, tmp, kvm) | |
420 | vcpu_vtimer(tmp)->cntvoff = cntvoff; | |
421 | ||
422 | /* | |
423 | * When called from the vcpu create path, the CPU being created is not | |
424 | * included in the loop above, so we just set it here as well. | |
425 | */ | |
426 | vcpu_vtimer(vcpu)->cntvoff = cntvoff; | |
427 | mutex_unlock(&kvm->lock); | |
428 | } | |
429 | ||
53e72406 MZ |
430 | void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) |
431 | { | |
432 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
433 | ||
90de943a JL |
434 | /* Synchronize cntvoff across all vtimers of a VM. */ |
435 | update_vtimer_cntvoff(vcpu, kvm_phys_timer_read()); | |
a91d1855 | 436 | vcpu_ptimer(vcpu)->cntvoff = 0; |
90de943a | 437 | |
53e72406 MZ |
438 | INIT_WORK(&timer->expired, kvm_timer_inject_irq_work); |
439 | hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
440 | timer->timer.function = kvm_timer_expire; | |
53e72406 MZ |
441 | } |
442 | ||
443 | static void kvm_timer_init_interrupt(void *info) | |
444 | { | |
cabdc5c5 | 445 | enable_percpu_irq(host_vtimer_irq, host_vtimer_irq_flags); |
53e72406 MZ |
446 | } |
447 | ||
39735a3a AP |
448 | int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) |
449 | { | |
fbb4aeec | 450 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
39735a3a AP |
451 | |
452 | switch (regid) { | |
453 | case KVM_REG_ARM_TIMER_CTL: | |
fbb4aeec | 454 | vtimer->cnt_ctl = value; |
39735a3a AP |
455 | break; |
456 | case KVM_REG_ARM_TIMER_CNT: | |
90de943a | 457 | update_vtimer_cntvoff(vcpu, kvm_phys_timer_read() - value); |
39735a3a AP |
458 | break; |
459 | case KVM_REG_ARM_TIMER_CVAL: | |
fbb4aeec | 460 | vtimer->cnt_cval = value; |
39735a3a AP |
461 | break; |
462 | default: | |
463 | return -1; | |
464 | } | |
4b4b4512 CD |
465 | |
466 | kvm_timer_update_state(vcpu); | |
39735a3a AP |
467 | return 0; |
468 | } | |
469 | ||
470 | u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) | |
471 | { | |
fbb4aeec | 472 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
39735a3a AP |
473 | |
474 | switch (regid) { | |
475 | case KVM_REG_ARM_TIMER_CTL: | |
fbb4aeec | 476 | return vtimer->cnt_ctl; |
39735a3a | 477 | case KVM_REG_ARM_TIMER_CNT: |
90de943a | 478 | return kvm_phys_timer_read() - vtimer->cntvoff; |
39735a3a | 479 | case KVM_REG_ARM_TIMER_CVAL: |
fbb4aeec | 480 | return vtimer->cnt_cval; |
39735a3a AP |
481 | } |
482 | return (u64)-1; | |
483 | } | |
53e72406 | 484 | |
b3c9950a | 485 | static int kvm_timer_starting_cpu(unsigned int cpu) |
53e72406 | 486 | { |
b3c9950a RC |
487 | kvm_timer_init_interrupt(NULL); |
488 | return 0; | |
53e72406 MZ |
489 | } |
490 | ||
b3c9950a RC |
491 | static int kvm_timer_dying_cpu(unsigned int cpu) |
492 | { | |
493 | disable_percpu_irq(host_vtimer_irq); | |
494 | return 0; | |
495 | } | |
53e72406 | 496 | |
53e72406 MZ |
497 | int kvm_timer_hyp_init(void) |
498 | { | |
29c2d6ff | 499 | struct arch_timer_kvm_info *info; |
53e72406 MZ |
500 | int err; |
501 | ||
29c2d6ff JG |
502 | info = arch_timer_get_kvm_info(); |
503 | timecounter = &info->timecounter; | |
53e72406 | 504 | |
8e1a0476 CD |
505 | if (!timecounter->cc) { |
506 | kvm_err("kvm_arch_timer: uninitialized timecounter\n"); | |
507 | return -ENODEV; | |
508 | } | |
509 | ||
29c2d6ff JG |
510 | if (info->virtual_irq <= 0) { |
511 | kvm_err("kvm_arch_timer: invalid virtual timer IRQ: %d\n", | |
512 | info->virtual_irq); | |
53e72406 MZ |
513 | return -ENODEV; |
514 | } | |
29c2d6ff | 515 | host_vtimer_irq = info->virtual_irq; |
53e72406 | 516 | |
cabdc5c5 MZ |
517 | host_vtimer_irq_flags = irq_get_trigger_type(host_vtimer_irq); |
518 | if (host_vtimer_irq_flags != IRQF_TRIGGER_HIGH && | |
519 | host_vtimer_irq_flags != IRQF_TRIGGER_LOW) { | |
520 | kvm_err("Invalid trigger for IRQ%d, assuming level low\n", | |
521 | host_vtimer_irq); | |
522 | host_vtimer_irq_flags = IRQF_TRIGGER_LOW; | |
523 | } | |
524 | ||
29c2d6ff | 525 | err = request_percpu_irq(host_vtimer_irq, kvm_arch_timer_handler, |
53e72406 MZ |
526 | "kvm guest timer", kvm_get_running_vcpus()); |
527 | if (err) { | |
528 | kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n", | |
29c2d6ff | 529 | host_vtimer_irq, err); |
5d947a14 | 530 | return err; |
53e72406 MZ |
531 | } |
532 | ||
29c2d6ff | 533 | kvm_info("virtual timer IRQ%d\n", host_vtimer_irq); |
53e72406 | 534 | |
b3c9950a | 535 | cpuhp_setup_state(CPUHP_AP_KVM_ARM_TIMER_STARTING, |
73c1b41e | 536 | "kvm/arm/timer:starting", kvm_timer_starting_cpu, |
b3c9950a | 537 | kvm_timer_dying_cpu); |
53e72406 MZ |
538 | return err; |
539 | } | |
540 | ||
541 | void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) | |
542 | { | |
543 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
fbb4aeec | 544 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
53e72406 MZ |
545 | |
546 | timer_disarm(timer); | |
fbb4aeec | 547 | kvm_vgic_unmap_phys_irq(vcpu, vtimer->irq.irq); |
53e72406 MZ |
548 | } |
549 | ||
41a54482 | 550 | int kvm_timer_enable(struct kvm_vcpu *vcpu) |
53e72406 | 551 | { |
41a54482 | 552 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; |
fbb4aeec | 553 | struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); |
41a54482 CD |
554 | struct irq_desc *desc; |
555 | struct irq_data *data; | |
556 | int phys_irq; | |
557 | int ret; | |
558 | ||
559 | if (timer->enabled) | |
560 | return 0; | |
561 | ||
562 | /* | |
563 | * Find the physical IRQ number corresponding to the host_vtimer_irq | |
564 | */ | |
565 | desc = irq_to_desc(host_vtimer_irq); | |
566 | if (!desc) { | |
567 | kvm_err("%s: no interrupt descriptor\n", __func__); | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | data = irq_desc_get_irq_data(desc); | |
572 | while (data->parent_data) | |
573 | data = data->parent_data; | |
574 | ||
575 | phys_irq = data->hwirq; | |
576 | ||
577 | /* | |
578 | * Tell the VGIC that the virtual interrupt is tied to a | |
579 | * physical interrupt. We do that once per VCPU. | |
580 | */ | |
fbb4aeec | 581 | ret = kvm_vgic_map_phys_irq(vcpu, vtimer->irq.irq, phys_irq); |
41a54482 CD |
582 | if (ret) |
583 | return ret; | |
584 | ||
fd5ebf99 | 585 | timer->enabled = 1; |
41a54482 CD |
586 | |
587 | return 0; | |
05971120 | 588 | } |
53e72406 | 589 | |
488f94d7 JL |
590 | /* |
591 | * On VHE system, we only need to configure trap on physical timer and counter | |
592 | * accesses in EL0 and EL1 once, not for every world switch. | |
593 | * The host kernel runs at EL2 with HCR_EL2.TGE == 1, | |
594 | * and this makes those bits have no effect for the host kernel execution. | |
595 | */ | |
596 | void kvm_timer_init_vhe(void) | |
597 | { | |
598 | /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */ | |
599 | u32 cnthctl_shift = 10; | |
600 | u64 val; | |
601 | ||
602 | /* | |
603 | * Disallow physical timer access for the guest. | |
604 | * Physical counter access is allowed. | |
605 | */ | |
606 | val = read_sysreg(cnthctl_el2); | |
607 | val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift); | |
608 | val |= (CNTHCTL_EL1PCTEN << cnthctl_shift); | |
609 | write_sysreg(val, cnthctl_el2); | |
610 | } |