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53e72406 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/cpu.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_host.h> | |
23 | #include <linux/interrupt.h> | |
24 | ||
372b7c1b | 25 | #include <clocksource/arm_arch_timer.h> |
53e72406 MZ |
26 | #include <asm/arch_timer.h> |
27 | ||
7275acdf MZ |
28 | #include <kvm/arm_vgic.h> |
29 | #include <kvm/arm_arch_timer.h> | |
53e72406 | 30 | |
e21f0910 CD |
31 | #include "trace.h" |
32 | ||
53e72406 MZ |
33 | static struct timecounter *timecounter; |
34 | static struct workqueue_struct *wqueue; | |
5ae7f87a | 35 | static unsigned int host_vtimer_irq; |
53e72406 MZ |
36 | |
37 | static cycle_t kvm_phys_timer_read(void) | |
38 | { | |
39 | return timecounter->cc->read(timecounter->cc); | |
40 | } | |
41 | ||
42 | static bool timer_is_armed(struct arch_timer_cpu *timer) | |
43 | { | |
44 | return timer->armed; | |
45 | } | |
46 | ||
47 | /* timer_arm: as in "arm the timer", not as in ARM the company */ | |
48 | static void timer_arm(struct arch_timer_cpu *timer, u64 ns) | |
49 | { | |
50 | timer->armed = true; | |
51 | hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns), | |
52 | HRTIMER_MODE_ABS); | |
53 | } | |
54 | ||
55 | static void timer_disarm(struct arch_timer_cpu *timer) | |
56 | { | |
57 | if (timer_is_armed(timer)) { | |
58 | hrtimer_cancel(&timer->timer); | |
59 | cancel_work_sync(&timer->expired); | |
60 | timer->armed = false; | |
61 | } | |
62 | } | |
63 | ||
53e72406 MZ |
64 | static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id) |
65 | { | |
66 | struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id; | |
67 | ||
68 | /* | |
69 | * We disable the timer in the world switch and let it be | |
70 | * handled by kvm_timer_sync_hwstate(). Getting a timer | |
71 | * interrupt at this point is a sure sign of some major | |
72 | * breakage. | |
73 | */ | |
74 | pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu); | |
75 | return IRQ_HANDLED; | |
76 | } | |
77 | ||
1a748478 CD |
78 | /* |
79 | * Work function for handling the backup timer that we schedule when a vcpu is | |
80 | * no longer running, but had a timer programmed to fire in the future. | |
81 | */ | |
53e72406 MZ |
82 | static void kvm_timer_inject_irq_work(struct work_struct *work) |
83 | { | |
84 | struct kvm_vcpu *vcpu; | |
85 | ||
86 | vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired); | |
87 | vcpu->arch.timer_cpu.armed = false; | |
1a748478 CD |
88 | |
89 | /* | |
90 | * If the vcpu is blocked we want to wake it up so that it will see | |
91 | * the timer has expired when entering the guest. | |
92 | */ | |
93 | kvm_vcpu_kick(vcpu); | |
53e72406 MZ |
94 | } |
95 | ||
96 | static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt) | |
97 | { | |
98 | struct arch_timer_cpu *timer; | |
99 | timer = container_of(hrt, struct arch_timer_cpu, timer); | |
100 | queue_work(wqueue, &timer->expired); | |
101 | return HRTIMER_NORESTART; | |
102 | } | |
103 | ||
d35268da CD |
104 | static bool kvm_timer_irq_can_fire(struct kvm_vcpu *vcpu) |
105 | { | |
106 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
107 | ||
108 | return !(timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) && | |
4b4b4512 | 109 | (timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE); |
d35268da CD |
110 | } |
111 | ||
1a748478 CD |
112 | bool kvm_timer_should_fire(struct kvm_vcpu *vcpu) |
113 | { | |
114 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
115 | cycle_t cval, now; | |
116 | ||
d35268da | 117 | if (!kvm_timer_irq_can_fire(vcpu)) |
1a748478 CD |
118 | return false; |
119 | ||
120 | cval = timer->cntv_cval; | |
121 | now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff; | |
122 | ||
123 | return cval <= now; | |
124 | } | |
125 | ||
4b4b4512 CD |
126 | static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level) |
127 | { | |
128 | int ret; | |
129 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
130 | ||
131 | BUG_ON(!vgic_initialized(vcpu->kvm)); | |
132 | ||
133 | timer->irq.level = new_level; | |
e21f0910 CD |
134 | trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->map->virt_irq, |
135 | timer->irq.level); | |
4b4b4512 CD |
136 | ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id, |
137 | timer->map, | |
138 | timer->irq.level); | |
139 | WARN_ON(ret); | |
140 | } | |
141 | ||
142 | /* | |
143 | * Check if there was a change in the timer state (should we raise or lower | |
144 | * the line level to the GIC). | |
145 | */ | |
146 | static void kvm_timer_update_state(struct kvm_vcpu *vcpu) | |
147 | { | |
148 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
149 | ||
150 | /* | |
151 | * If userspace modified the timer registers via SET_ONE_REG before | |
152 | * the vgic was initialized, we mustn't set the timer->irq.level value | |
153 | * because the guest would never see the interrupt. Instead wait | |
154 | * until we call this function from kvm_timer_flush_hwstate. | |
155 | */ | |
156 | if (!vgic_initialized(vcpu->kvm)) | |
157 | return; | |
158 | ||
159 | if (kvm_timer_should_fire(vcpu) != timer->irq.level) | |
160 | kvm_timer_update_irq(vcpu, !timer->irq.level); | |
161 | } | |
162 | ||
d35268da CD |
163 | /* |
164 | * Schedule the background timer before calling kvm_vcpu_block, so that this | |
165 | * thread is removed from its waitqueue and made runnable when there's a timer | |
166 | * interrupt to handle. | |
167 | */ | |
168 | void kvm_timer_schedule(struct kvm_vcpu *vcpu) | |
169 | { | |
170 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
171 | u64 ns; | |
172 | cycle_t cval, now; | |
173 | ||
174 | BUG_ON(timer_is_armed(timer)); | |
175 | ||
176 | /* | |
177 | * No need to schedule a background timer if the guest timer has | |
178 | * already expired, because kvm_vcpu_block will return before putting | |
179 | * the thread to sleep. | |
180 | */ | |
181 | if (kvm_timer_should_fire(vcpu)) | |
182 | return; | |
183 | ||
184 | /* | |
185 | * If the timer is not capable of raising interrupts (disabled or | |
186 | * masked), then there's no more work for us to do. | |
187 | */ | |
188 | if (!kvm_timer_irq_can_fire(vcpu)) | |
189 | return; | |
190 | ||
191 | /* The timer has not yet expired, schedule a background timer */ | |
192 | cval = timer->cntv_cval; | |
193 | now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff; | |
194 | ||
195 | ns = cyclecounter_cyc2ns(timecounter->cc, | |
196 | cval - now, | |
197 | timecounter->mask, | |
198 | &timecounter->frac); | |
199 | timer_arm(timer, ns); | |
200 | } | |
201 | ||
202 | void kvm_timer_unschedule(struct kvm_vcpu *vcpu) | |
203 | { | |
204 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
205 | timer_disarm(timer); | |
206 | } | |
207 | ||
53e72406 MZ |
208 | /** |
209 | * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu | |
210 | * @vcpu: The vcpu pointer | |
211 | * | |
d35268da CD |
212 | * Check if the virtual timer has expired while we were running in the host, |
213 | * and inject an interrupt if that was the case. | |
53e72406 MZ |
214 | */ |
215 | void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) | |
216 | { | |
217 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
cff9211e CD |
218 | bool phys_active; |
219 | int ret; | |
53e72406 | 220 | |
4b4b4512 | 221 | kvm_timer_update_state(vcpu); |
cff9211e CD |
222 | |
223 | /* | |
0e3dfda9 CD |
224 | * If we enter the guest with the virtual input level to the VGIC |
225 | * asserted, then we have already told the VGIC what we need to, and | |
226 | * we don't need to exit from the guest until the guest deactivates | |
227 | * the already injected interrupt, so therefore we should set the | |
228 | * hardware active state to prevent unnecessary exits from the guest. | |
229 | * | |
230 | * Also, if we enter the guest with the virtual timer interrupt active, | |
231 | * then it must be active on the physical distributor, because we set | |
232 | * the HW bit and the guest must be able to deactivate the virtual and | |
233 | * physical interrupt at the same time. | |
234 | * | |
235 | * Conversely, if the virtual input level is deasserted and the virtual | |
236 | * interrupt is not active, then always clear the hardware active state | |
237 | * to ensure that hardware interrupts from the timer triggers a guest | |
238 | * exit. | |
239 | */ | |
240 | if (timer->irq.level || kvm_vgic_map_is_active(vcpu, timer->map)) | |
cff9211e CD |
241 | phys_active = true; |
242 | else | |
243 | phys_active = false; | |
244 | ||
245 | ret = irq_set_irqchip_state(timer->map->irq, | |
246 | IRQCHIP_STATE_ACTIVE, | |
247 | phys_active); | |
248 | WARN_ON(ret); | |
53e72406 MZ |
249 | } |
250 | ||
251 | /** | |
252 | * kvm_timer_sync_hwstate - sync timer state from cpu | |
253 | * @vcpu: The vcpu pointer | |
254 | * | |
d35268da CD |
255 | * Check if the virtual timer has expired while we were running in the guest, |
256 | * and inject an interrupt if that was the case. | |
53e72406 MZ |
257 | */ |
258 | void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) | |
259 | { | |
260 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
53e72406 | 261 | |
53e72406 MZ |
262 | BUG_ON(timer_is_armed(timer)); |
263 | ||
4b4b4512 CD |
264 | /* |
265 | * The guest could have modified the timer registers or the timer | |
266 | * could have expired, update the timer state. | |
267 | */ | |
268 | kvm_timer_update_state(vcpu); | |
53e72406 MZ |
269 | } |
270 | ||
f120cd65 MZ |
271 | int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, |
272 | const struct kvm_irq_level *irq) | |
5ae7f87a AP |
273 | { |
274 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
f120cd65 | 275 | struct irq_phys_map *map; |
5ae7f87a AP |
276 | |
277 | /* | |
278 | * The vcpu timer irq number cannot be determined in | |
279 | * kvm_timer_vcpu_init() because it is called much before | |
280 | * kvm_vcpu_set_target(). To handle this, we determine | |
281 | * vcpu timer irq number when the vcpu is reset. | |
282 | */ | |
4b4b4512 | 283 | timer->irq.irq = irq->irq; |
f120cd65 | 284 | |
4ad9e16a CD |
285 | /* |
286 | * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8 | |
287 | * and to 0 for ARMv7. We provide an implementation that always | |
288 | * resets the timer to be disabled and unmasked and is compliant with | |
289 | * the ARMv7 architecture. | |
290 | */ | |
291 | timer->cntv_ctl = 0; | |
4b4b4512 | 292 | kvm_timer_update_state(vcpu); |
4ad9e16a | 293 | |
f120cd65 MZ |
294 | /* |
295 | * Tell the VGIC that the virtual interrupt is tied to a | |
296 | * physical interrupt. We do that once per VCPU. | |
297 | */ | |
298 | map = kvm_vgic_map_phys_irq(vcpu, irq->irq, host_vtimer_irq); | |
299 | if (WARN_ON(IS_ERR(map))) | |
300 | return PTR_ERR(map); | |
301 | ||
302 | timer->map = map; | |
303 | return 0; | |
5ae7f87a AP |
304 | } |
305 | ||
53e72406 MZ |
306 | void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) |
307 | { | |
308 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
309 | ||
310 | INIT_WORK(&timer->expired, kvm_timer_inject_irq_work); | |
311 | hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
312 | timer->timer.function = kvm_timer_expire; | |
53e72406 MZ |
313 | } |
314 | ||
315 | static void kvm_timer_init_interrupt(void *info) | |
316 | { | |
5ae7f87a | 317 | enable_percpu_irq(host_vtimer_irq, 0); |
53e72406 MZ |
318 | } |
319 | ||
39735a3a AP |
320 | int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) |
321 | { | |
322 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
323 | ||
324 | switch (regid) { | |
325 | case KVM_REG_ARM_TIMER_CTL: | |
326 | timer->cntv_ctl = value; | |
327 | break; | |
328 | case KVM_REG_ARM_TIMER_CNT: | |
329 | vcpu->kvm->arch.timer.cntvoff = kvm_phys_timer_read() - value; | |
330 | break; | |
331 | case KVM_REG_ARM_TIMER_CVAL: | |
332 | timer->cntv_cval = value; | |
333 | break; | |
334 | default: | |
335 | return -1; | |
336 | } | |
4b4b4512 CD |
337 | |
338 | kvm_timer_update_state(vcpu); | |
39735a3a AP |
339 | return 0; |
340 | } | |
341 | ||
342 | u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) | |
343 | { | |
344 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
345 | ||
346 | switch (regid) { | |
347 | case KVM_REG_ARM_TIMER_CTL: | |
348 | return timer->cntv_ctl; | |
349 | case KVM_REG_ARM_TIMER_CNT: | |
350 | return kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff; | |
351 | case KVM_REG_ARM_TIMER_CVAL: | |
352 | return timer->cntv_cval; | |
353 | } | |
354 | return (u64)-1; | |
355 | } | |
53e72406 MZ |
356 | |
357 | static int kvm_timer_cpu_notify(struct notifier_block *self, | |
358 | unsigned long action, void *cpu) | |
359 | { | |
360 | switch (action) { | |
361 | case CPU_STARTING: | |
362 | case CPU_STARTING_FROZEN: | |
363 | kvm_timer_init_interrupt(NULL); | |
364 | break; | |
365 | case CPU_DYING: | |
366 | case CPU_DYING_FROZEN: | |
5ae7f87a | 367 | disable_percpu_irq(host_vtimer_irq); |
53e72406 MZ |
368 | break; |
369 | } | |
370 | ||
371 | return NOTIFY_OK; | |
372 | } | |
373 | ||
374 | static struct notifier_block kvm_timer_cpu_nb = { | |
375 | .notifier_call = kvm_timer_cpu_notify, | |
376 | }; | |
377 | ||
378 | static const struct of_device_id arch_timer_of_match[] = { | |
379 | { .compatible = "arm,armv7-timer", }, | |
f61701e0 | 380 | { .compatible = "arm,armv8-timer", }, |
53e72406 MZ |
381 | {}, |
382 | }; | |
383 | ||
384 | int kvm_timer_hyp_init(void) | |
385 | { | |
386 | struct device_node *np; | |
387 | unsigned int ppi; | |
388 | int err; | |
389 | ||
390 | timecounter = arch_timer_get_timecounter(); | |
391 | if (!timecounter) | |
392 | return -ENODEV; | |
393 | ||
394 | np = of_find_matching_node(NULL, arch_timer_of_match); | |
395 | if (!np) { | |
396 | kvm_err("kvm_arch_timer: can't find DT node\n"); | |
397 | return -ENODEV; | |
398 | } | |
399 | ||
400 | ppi = irq_of_parse_and_map(np, 2); | |
401 | if (!ppi) { | |
402 | kvm_err("kvm_arch_timer: no virtual timer interrupt\n"); | |
403 | err = -EINVAL; | |
404 | goto out; | |
405 | } | |
406 | ||
407 | err = request_percpu_irq(ppi, kvm_arch_timer_handler, | |
408 | "kvm guest timer", kvm_get_running_vcpus()); | |
409 | if (err) { | |
410 | kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n", | |
411 | ppi, err); | |
412 | goto out; | |
413 | } | |
414 | ||
5ae7f87a | 415 | host_vtimer_irq = ppi; |
53e72406 | 416 | |
553f809e | 417 | err = __register_cpu_notifier(&kvm_timer_cpu_nb); |
53e72406 MZ |
418 | if (err) { |
419 | kvm_err("Cannot register timer CPU notifier\n"); | |
420 | goto out_free; | |
421 | } | |
422 | ||
423 | wqueue = create_singlethread_workqueue("kvm_arch_timer"); | |
424 | if (!wqueue) { | |
425 | err = -ENOMEM; | |
426 | goto out_free; | |
427 | } | |
428 | ||
429 | kvm_info("%s IRQ%d\n", np->name, ppi); | |
430 | on_each_cpu(kvm_timer_init_interrupt, NULL, 1); | |
431 | ||
432 | goto out; | |
433 | out_free: | |
434 | free_percpu_irq(ppi, kvm_get_running_vcpus()); | |
435 | out: | |
436 | of_node_put(np); | |
437 | return err; | |
438 | } | |
439 | ||
440 | void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) | |
441 | { | |
442 | struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; | |
443 | ||
444 | timer_disarm(timer); | |
f120cd65 MZ |
445 | if (timer->map) |
446 | kvm_vgic_unmap_phys_irq(vcpu, timer->map); | |
53e72406 MZ |
447 | } |
448 | ||
05971120 | 449 | void kvm_timer_enable(struct kvm *kvm) |
53e72406 | 450 | { |
05971120 CD |
451 | if (kvm->arch.timer.enabled) |
452 | return; | |
453 | ||
454 | /* | |
455 | * There is a potential race here between VCPUs starting for the first | |
456 | * time, which may be enabling the timer multiple times. That doesn't | |
457 | * hurt though, because we're just setting a variable to the same | |
458 | * variable that it already was. The important thing is that all | |
459 | * VCPUs have the enabled variable set, before entering the guest, if | |
460 | * the arch timers are enabled. | |
461 | */ | |
462 | if (timecounter && wqueue) | |
53e72406 | 463 | kvm->arch.timer.enabled = 1; |
05971120 | 464 | } |
53e72406 | 465 | |
05971120 CD |
466 | void kvm_timer_init(struct kvm *kvm) |
467 | { | |
468 | kvm->arch.timer.cntvoff = kvm_phys_timer_read(); | |
53e72406 | 469 | } |