[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic-mmio-v2.c

/*
 * VGICv2 MMIO handling functions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irqchip/arm-gic.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/iodev.h>
#include <kvm/arm_vgic.h>

#include "vgic.h"
#include "vgic-mmio.h"

static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	u32 value;

	switch (addr & 0x0c) {
	case GIC_DIST_CTRL:
		value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
		break;
	case GIC_DIST_CTR:
		value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		value = (value >> 5) - 1;
		value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
		break;
	case GIC_DIST_IIDR:
		value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
		break;
	default:
		return 0;
	}

	return value;
}

static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
				    gpa_t addr, unsigned int len,
				    unsigned long val)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	bool was_enabled = dist->enabled;

	switch (addr & 0x0c) {
	case GIC_DIST_CTRL:
		dist->enabled = val & GICD_ENABLE;
		if (!was_enabled && dist->enabled)
			vgic_kick_vcpus(vcpu->kvm);
		break;
	case GIC_DIST_CTR:
	case GIC_DIST_IIDR:
		/* Nothing to do */
		return;
	}
}

static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
				 gpa_t addr, unsigned int len,
				 unsigned long val)
{
	int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
	int intid = val & 0xf;
	int targets = (val >> 16) & 0xff;
	int mode = (val >> 24) & 0x03;
	int c;
	struct kvm_vcpu *vcpu;

	switch (mode) {
	case 0x0:		/* as specified by targets */
		break;
	case 0x1:
		targets = (1U << nr_vcpus) - 1;			/* all, ... */
		targets &= ~(1U << source_vcpu->vcpu_id);	/* but self */
		break;
	case 0x2:		/* this very vCPU only */
		targets = (1U << source_vcpu->vcpu_id);
		break;
	case 0x3:		/* reserved */
		return;
	}

	kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
		struct vgic_irq *irq;

		if (!(targets & (1U << c)))
			continue;

		irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);

		spin_lock(&irq->irq_lock);
		irq->pending_latch = true;
		irq->source |= 1U << source_vcpu->vcpu_id;

		vgic_queue_irq_unlock(source_vcpu->kvm, irq);
		vgic_put_irq(source_vcpu->kvm, irq);
	}
}

static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
					   gpa_t addr, unsigned int len)
{
	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
	int i;
	u64 val = 0;

	for (i = 0; i < len; i++) {
		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);

		val |= (u64)irq->targets << (i * 8);

		vgic_put_irq(vcpu->kvm, irq);
	}

	return val;
}

static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
				   gpa_t addr, unsigned int len,
				   unsigned long val)
{
	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
	u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
	int i;

	/* GICD_ITARGETSR[0-7] are read-only */
	if (intid < VGIC_NR_PRIVATE_IRQS)
		return;

	for (i = 0; i < len; i++) {
		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
		int target;

		spin_lock(&irq->irq_lock);

		irq->targets = (val >> (i * 8)) & cpu_mask;
		target = irq->targets ? __ffs(irq->targets) : 0;
		irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);

		spin_unlock(&irq->irq_lock);
		vgic_put_irq(vcpu->kvm, irq);
	}
}

static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	u32 intid = addr & 0x0f;
	int i;
	u64 val = 0;

	for (i = 0; i < len; i++) {
		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);

		val |= (u64)irq->source << (i * 8);

		vgic_put_irq(vcpu->kvm, irq);
	}
	return val;
}

static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
				     gpa_t addr, unsigned int len,
				     unsigned long val)
{
	u32 intid = addr & 0x0f;
	int i;

	for (i = 0; i < len; i++) {
		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);

		spin_lock(&irq->irq_lock);

		irq->source &= ~((val >> (i * 8)) & 0xff);
		if (!irq->source)
			irq->pending_latch = false;

		spin_unlock(&irq->irq_lock);
		vgic_put_irq(vcpu->kvm, irq);
	}
}

static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
				     gpa_t addr, unsigned int len,
				     unsigned long val)
{
	u32 intid = addr & 0x0f;
	int i;

	for (i = 0; i < len; i++) {
		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);

		spin_lock(&irq->irq_lock);

		irq->source |= (val >> (i * 8)) & 0xff;

		if (irq->source) {
			irq->pending_latch = true;
			vgic_queue_irq_unlock(vcpu->kvm, irq);
		} else {
			spin_unlock(&irq->irq_lock);
		}
		vgic_put_irq(vcpu->kvm, irq);
	}
}

#define GICC_ARCH_VERSION_V2	0x2

/* These are for userland accesses only, there is no guest-facing emulation. */
static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
					   gpa_t addr, unsigned int len)
{
	struct vgic_vmcr vmcr;
	u32 val;

	vgic_get_vmcr(vcpu, &vmcr);

	switch (addr & 0xff) {
	case GIC_CPU_CTRL:
		val = vmcr.ctlr;
		break;
	case GIC_CPU_PRIMASK:
		val = vmcr.pmr;
		break;
	case GIC_CPU_BINPOINT:
		val = vmcr.bpr;
		break;
	case GIC_CPU_ALIAS_BINPOINT:
		val = vmcr.abpr;
		break;
	case GIC_CPU_IDENT:
		val = ((PRODUCT_ID_KVM << 20) |
		       (GICC_ARCH_VERSION_V2 << 16) |
		       IMPLEMENTER_ARM);
		break;
	default:
		return 0;
	}

	return val;
}

static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
				   gpa_t addr, unsigned int len,
				   unsigned long val)
{
	struct vgic_vmcr vmcr;

	vgic_get_vmcr(vcpu, &vmcr);

	switch (addr & 0xff) {
	case GIC_CPU_CTRL:
		vmcr.ctlr = val;
		break;
	case GIC_CPU_PRIMASK:
		vmcr.pmr = val;
		break;
	case GIC_CPU_BINPOINT:
		vmcr.bpr = val;
		break;
	case GIC_CPU_ALIAS_BINPOINT:
		vmcr.abpr = val;
		break;
	}

	vgic_set_vmcr(vcpu, &vmcr);
}

static const struct vgic_register_region vgic_v2_dist_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
		vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
		vgic_mmio_read_target, vgic_mmio_write_target, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
		vgic_mmio_read_config, vgic_mmio_write_config, 2,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
		vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
		vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
		vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
};

static const struct vgic_register_region vgic_v2_cpu_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
		VGIC_ACCESS_32bit),
};

unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
{
	dev->regions = vgic_v2_dist_registers;
	dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);

	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);

	return SZ_4K;
}

int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
{
	const struct vgic_register_region *region;
	struct vgic_io_device iodev;
	struct vgic_reg_attr reg_attr;
	struct kvm_vcpu *vcpu;
	gpa_t addr;
	int ret;

	ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
	if (ret)
		return ret;

	vcpu = reg_attr.vcpu;
	addr = reg_attr.addr;

	switch (attr->group) {
	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		iodev.regions = vgic_v2_dist_registers;
		iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
		iodev.base_addr = 0;
		break;
	case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
		iodev.regions = vgic_v2_cpu_registers;
		iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
		iodev.base_addr = 0;
		break;
	default:
		return -ENXIO;
	}

	/* We only support aligned 32-bit accesses. */
	if (addr & 3)
		return -ENXIO;

	region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
	if (!region)
		return -ENXIO;

	return 0;
}

int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			  int offset, u32 *val)
{
	struct vgic_io_device dev = {
		.regions = vgic_v2_cpu_registers,
		.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
		.iodev_type = IODEV_CPUIF,
	};

	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
}

int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val)
{
	struct vgic_io_device dev = {
		.regions = vgic_v2_dist_registers,
		.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
		.iodev_type = IODEV_DIST,
	};

	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
}
Commit	Line	Data
fb848db3 AP	1	/*
	2	* VGICv2 MMIO handling functions
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/irqchip/arm-gic.h>
	15	#include <linux/kvm.h>
	16	#include <linux/kvm_host.h>
	17	#include <kvm/iodev.h>
	18	#include <kvm/arm_vgic.h>
	19
	20	#include "vgic.h"
	21	#include "vgic-mmio.h"
	22
2b0cda87 MZ	23	static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
	24	gpa_t addr, unsigned int len)
	25	{
	26	u32 value;
	27
	28	switch (addr & 0x0c) {
	29	case GIC_DIST_CTRL:
	30	value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
	31	break;
	32	case GIC_DIST_CTR:
	33	value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
	34	value = (value >> 5) - 1;
	35	value \|= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
	36	break;
	37	case GIC_DIST_IIDR:
	38	value = (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	39	break;
	40	default:
	41	return 0;
	42	}
	43
	44	return value;
	45	}
	46
	47	static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
	48	gpa_t addr, unsigned int len,
	49	unsigned long val)
	50	{
	51	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	52	bool was_enabled = dist->enabled;
	53
	54	switch (addr & 0x0c) {
	55	case GIC_DIST_CTRL:
	56	dist->enabled = val & GICD_ENABLE;
	57	if (!was_enabled && dist->enabled)
	58	vgic_kick_vcpus(vcpu->kvm);
	59	break;
	60	case GIC_DIST_CTR:
	61	case GIC_DIST_IIDR:
	62	/* Nothing to do */
	63	return;
	64	}
	65	}
	66
55cc01fb AP	67	static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
	68	gpa_t addr, unsigned int len,
	69	unsigned long val)
	70	{
	71	int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
	72	int intid = val & 0xf;
	73	int targets = (val >> 16) & 0xff;
	74	int mode = (val >> 24) & 0x03;
	75	int c;
	76	struct kvm_vcpu *vcpu;
	77
	78	switch (mode) {
	79	case 0x0: /* as specified by targets */
	80	break;
	81	case 0x1:
	82	targets = (1U << nr_vcpus) - 1; /* all, ... */
	83	targets &= ~(1U << source_vcpu->vcpu_id); /* but self */
	84	break;
	85	case 0x2: /* this very vCPU only */
	86	targets = (1U << source_vcpu->vcpu_id);
	87	break;
	88	case 0x3: /* reserved */
	89	return;
	90	}
	91
	92	kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
	93	struct vgic_irq *irq;
	94
	95	if (!(targets & (1U << c)))
	96	continue;
	97
	98	irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
	99
	100	spin_lock(&irq->irq_lock);
8694e4da	101	irq->pending_latch = true;
55cc01fb AP	102	irq->source \|= 1U << source_vcpu->vcpu_id;
	103
	104	vgic_queue_irq_unlock(source_vcpu->kvm, irq);
5dd4b924	105	vgic_put_irq(source_vcpu->kvm, irq);
55cc01fb AP	106	}
	107	}
	108
2c234d6f AP	109	static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
	110	gpa_t addr, unsigned int len)
	111	{
	112	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
	113	int i;
	114	u64 val = 0;
	115
	116	for (i = 0; i < len; i++) {
	117	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
	118
	119	val \|= (u64)irq->targets << (i * 8);
5dd4b924 AP	120
5dd4b924 AP	121	vgic_put_irq(vcpu->kvm, irq);
2c234d6f AP	122	}
	123
	124	return val;
	125	}
	126
	127	static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
	128	gpa_t addr, unsigned int len,
	129	unsigned long val)
	130	{
	131	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
266068ea	132	u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
2c234d6f AP	133	int i;
	134
	135	/* GICD_ITARGETSR[0-7] are read-only */
	136	if (intid < VGIC_NR_PRIVATE_IRQS)
	137	return;
	138
	139	for (i = 0; i < len; i++) {
	140	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
	141	int target;
	142
	143	spin_lock(&irq->irq_lock);
	144
266068ea	145	irq->targets = (val >> (i * 8)) & cpu_mask;
2c234d6f AP	146	target = irq->targets ? __ffs(irq->targets) : 0;
	147	irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
	148
	149	spin_unlock(&irq->irq_lock);
5dd4b924	150	vgic_put_irq(vcpu->kvm, irq);
2c234d6f AP	151	}
	152	}
	153
ed40213e AP	154	static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
	155	gpa_t addr, unsigned int len)
	156	{
	157	u32 intid = addr & 0x0f;
	158	int i;
	159	u64 val = 0;
	160
	161	for (i = 0; i < len; i++) {
	162	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
	163
	164	val \|= (u64)irq->source << (i * 8);
5dd4b924 AP	165
5dd4b924 AP	166	vgic_put_irq(vcpu->kvm, irq);
ed40213e AP	167	}
	168	return val;
	169	}
	170
	171	static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
	172	gpa_t addr, unsigned int len,
	173	unsigned long val)
	174	{
	175	u32 intid = addr & 0x0f;
	176	int i;
	177
	178	for (i = 0; i < len; i++) {
	179	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
	180
	181	spin_lock(&irq->irq_lock);
	182
	183	irq->source &= ~((val >> (i * 8)) & 0xff);
	184	if (!irq->source)
8694e4da	185	irq->pending_latch = false;
ed40213e AP	186
ed40213e AP	187	spin_unlock(&irq->irq_lock);
5dd4b924	188	vgic_put_irq(vcpu->kvm, irq);
ed40213e AP	189	}
	190	}
	191
	192	static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
	193	gpa_t addr, unsigned int len,
	194	unsigned long val)
	195	{
	196	u32 intid = addr & 0x0f;
	197	int i;
	198
	199	for (i = 0; i < len; i++) {
	200	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
	201
	202	spin_lock(&irq->irq_lock);
	203
	204	irq->source \|= (val >> (i * 8)) & 0xff;
	205
	206	if (irq->source) {
8694e4da	207	irq->pending_latch = true;
ed40213e AP	208	vgic_queue_irq_unlock(vcpu->kvm, irq);
	209	} else {
	210	spin_unlock(&irq->irq_lock);
	211	}
5dd4b924	212	vgic_put_irq(vcpu->kvm, irq);
ed40213e AP	213	}
	214	}
	215
878c569e AP	216	#define GICC_ARCH_VERSION_V2 0x2
	217
	218	/* These are for userland accesses only, there is no guest-facing emulation. */
	219	static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
	220	gpa_t addr, unsigned int len)
	221	{
	222	struct vgic_vmcr vmcr;
	223	u32 val;
	224
	225	vgic_get_vmcr(vcpu, &vmcr);
	226
	227	switch (addr & 0xff) {
	228	case GIC_CPU_CTRL:
	229	val = vmcr.ctlr;
	230	break;
	231	case GIC_CPU_PRIMASK:
	232	val = vmcr.pmr;
	233	break;
	234	case GIC_CPU_BINPOINT:
	235	val = vmcr.bpr;
	236	break;
	237	case GIC_CPU_ALIAS_BINPOINT:
	238	val = vmcr.abpr;
	239	break;
	240	case GIC_CPU_IDENT:
	241	val = ((PRODUCT_ID_KVM << 20) \|
	242	(GICC_ARCH_VERSION_V2 << 16) \|
	243	IMPLEMENTER_ARM);
	244	break;
	245	default:
	246	return 0;
	247	}
	248
	249	return val;
	250	}
	251
	252	static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
	253	gpa_t addr, unsigned int len,
	254	unsigned long val)
	255	{
	256	struct vgic_vmcr vmcr;
	257
	258	vgic_get_vmcr(vcpu, &vmcr);
	259
	260	switch (addr & 0xff) {
	261	case GIC_CPU_CTRL:
	262	vmcr.ctlr = val;
	263	break;
	264	case GIC_CPU_PRIMASK:
	265	vmcr.pmr = val;
	266	break;
	267	case GIC_CPU_BINPOINT:
	268	vmcr.bpr = val;
	269	break;
	270	case GIC_CPU_ALIAS_BINPOINT:
	271	vmcr.abpr = val;
	272	break;
	273	}
	274
	275	vgic_set_vmcr(vcpu, &vmcr);
	276	}
	277
fb848db3 AP	278	static const struct vgic_register_region vgic_v2_dist_registers[] = {
fb848db3 AP	279	REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
2b0cda87	280	vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
fb848db3 AP	281	VGIC_ACCESS_32bit),
	282	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
	283	vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
	284	VGIC_ACCESS_32bit),
	285	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
fd122e62	286	vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
fb848db3 AP	287	VGIC_ACCESS_32bit),
fb848db3 AP	288	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
fd122e62	289	vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
fb848db3 AP	290	VGIC_ACCESS_32bit),
fb848db3 AP	291	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
96b29800	292	vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
fb848db3 AP	293	VGIC_ACCESS_32bit),
fb848db3 AP	294	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
96b29800	295	vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
fb848db3 AP	296	VGIC_ACCESS_32bit),
fb848db3 AP	297	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
69b6fe0c	298	vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
fb848db3 AP	299	VGIC_ACCESS_32bit),
fb848db3 AP	300	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
69b6fe0c	301	vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
fb848db3 AP	302	VGIC_ACCESS_32bit),
fb848db3 AP	303	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
055658bf	304	vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
fb848db3 AP	305	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
fb848db3 AP	306	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
2c234d6f	307	vgic_mmio_read_target, vgic_mmio_write_target, 8,
fb848db3 AP	308	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
fb848db3 AP	309	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
79717e4a	310	vgic_mmio_read_config, vgic_mmio_write_config, 2,
fb848db3 AP	311	VGIC_ACCESS_32bit),
fb848db3 AP	312	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
55cc01fb	313	vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
fb848db3 AP	314	VGIC_ACCESS_32bit),
fb848db3 AP	315	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
ed40213e	316	vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
fb848db3 AP	317	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
fb848db3 AP	318	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
ed40213e	319	vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
fb848db3 AP	320	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	321	};
	322
878c569e AP	323	static const struct vgic_register_region vgic_v2_cpu_registers[] = {
	324	REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
	325	vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
	326	VGIC_ACCESS_32bit),
	327	REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
	328	vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
	329	VGIC_ACCESS_32bit),
	330	REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
	331	vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
	332	VGIC_ACCESS_32bit),
	333	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
	334	vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
	335	VGIC_ACCESS_32bit),
	336	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
	337	vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
	338	VGIC_ACCESS_32bit),
	339	REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
	340	vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
	341	VGIC_ACCESS_32bit),
	342	};
	343
fb848db3 AP	344	unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
	345	{
	346	dev->regions = vgic_v2_dist_registers;
	347	dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
	348
	349	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
	350
	351	return SZ_4K;
	352	}
f94591e2 EA	353
	354	int vgic_v2_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr)
	355	{
94574c94 VK	356	const struct vgic_register_region *region;
	357	struct vgic_io_device iodev;
	358	struct vgic_reg_attr reg_attr;
	359	struct kvm_vcpu *vcpu;
f94591e2	360	gpa_t addr;
94574c94 VK	361	int ret;
	362
	363	ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
	364	if (ret)
	365	return ret;
f94591e2	366
94574c94 VK	367	vcpu = reg_attr.vcpu;
94574c94 VK	368	addr = reg_attr.addr;
f94591e2 EA	369
	370	switch (attr->group) {
	371	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
94574c94 VK	372	iodev.regions = vgic_v2_dist_registers;
	373	iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
	374	iodev.base_addr = 0;
f94591e2 EA	375	break;
f94591e2 EA	376	case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
94574c94 VK	377	iodev.regions = vgic_v2_cpu_registers;
	378	iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
	379	iodev.base_addr = 0;
878c569e	380	break;
f94591e2 EA	381	default:
	382	return -ENXIO;
	383	}
	384
	385	/* We only support aligned 32-bit accesses. */
	386	if (addr & 3)
	387	return -ENXIO;
	388
94574c94 VK	389	region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
	390	if (!region)
	391	return -ENXIO;
f94591e2	392
94574c94	393	return 0;
f94591e2	394	}
c3199f28	395
878c569e AP	396	int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	397	int offset, u32 *val)
	398	{
	399	struct vgic_io_device dev = {
	400	.regions = vgic_v2_cpu_registers,
	401	.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
9d5fcb9d	402	.iodev_type = IODEV_CPUIF,
878c569e AP	403	};
	404
	405	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
	406	}
	407
c3199f28 CD	408	int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	409	int offset, u32 *val)
	410	{
	411	struct vgic_io_device dev = {
	412	.regions = vgic_v2_dist_registers,
	413	.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
9d5fcb9d	414	.iodev_type = IODEV_DIST,
c3199f28 CD	415	};
	416
	417	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
	418	}