[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic-mmio-v3.c

/*
 * VGICv3 MMIO handling functions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/iodev.h>
#include <kvm/arm_vgic.h>

#include <asm/kvm_emulate.h>

#include "vgic.h"
#include "vgic-mmio.h"

/* extract @num bytes at @offset bytes offset in data */
static unsigned long extract_bytes(unsigned long data, unsigned int offset,
				   unsigned int num)
{
	return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
}

/* allows updates of any half of a 64-bit register (or the whole thing) */
static u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
			    unsigned long val)
{
	int lower = (offset & 4) * 8;
	int upper = lower + 8 * len - 1;

	reg &= ~GENMASK_ULL(upper, lower);
	val &= GENMASK_ULL(len * 8 - 1, 0);

	return reg | ((u64)val << lower);
}

bool vgic_has_its(struct kvm *kvm)
{
	struct vgic_dist *dist = &kvm->arch.vgic;

	if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
		return false;

	return dist->has_its;
}

static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	u32 value = 0;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		if (vcpu->kvm->arch.vgic.enabled)
			value |= GICD_CTLR_ENABLE_SS_G1;
		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
		break;
	case GICD_TYPER:
		value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		value = (value >> 5) - 1;
		value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
		break;
	case GICD_IIDR:
		value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
		break;
	default:
		return 0;
	}

	return value;
}

static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
				    gpa_t addr, unsigned int len,
				    unsigned long val)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	bool was_enabled = dist->enabled;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;

		if (!was_enabled && dist->enabled)
			vgic_kick_vcpus(vcpu->kvm);
		break;
	case GICD_TYPER:
	case GICD_IIDR:
		return;
	}
}

static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	int intid = VGIC_ADDR_TO_INTID(addr, 64);
	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
	unsigned long ret = 0;

	if (!irq)
		return 0;

	/* The upper word is RAZ for us. */
	if (!(addr & 4))
		ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);

	vgic_put_irq(vcpu->kvm, irq);
	return ret;
}

static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
				    gpa_t addr, unsigned int len,
				    unsigned long val)
{
	int intid = VGIC_ADDR_TO_INTID(addr, 64);
	struct vgic_irq *irq;

	/* The upper word is WI for us since we don't implement Aff3. */
	if (addr & 4)
		return;

	irq = vgic_get_irq(vcpu->kvm, NULL, intid);

	if (!irq)
		return;

	spin_lock(&irq->irq_lock);

	/* We only care about and preserve Aff0, Aff1 and Aff2. */
	irq->mpidr = val & GENMASK(23, 0);
	irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);

	spin_unlock(&irq->irq_lock);
	vgic_put_irq(vcpu->kvm, irq);
}

static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
					     gpa_t addr, unsigned int len)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;

	return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
}


static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
				     gpa_t addr, unsigned int len,
				     unsigned long val)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	bool was_enabled = vgic_cpu->lpis_enabled;

	if (!vgic_has_its(vcpu->kvm))
		return;

	vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;

	if (!was_enabled && vgic_cpu->lpis_enabled) {
		/* Eventually do something */
	}
}

static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
					      gpa_t addr, unsigned int len)
{
	unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
	int target_vcpu_id = vcpu->vcpu_id;
	u64 value;

	value = (mpidr & GENMASK(23, 0)) << 32;
	value |= ((target_vcpu_id & 0xffff) << 8);
	if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
		value |= GICR_TYPER_LAST;

	return extract_bytes(value, addr & 7, len);
}

static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
					     gpa_t addr, unsigned int len)
{
	return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
}

static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
					      gpa_t addr, unsigned int len)
{
	switch (addr & 0xffff) {
	case GICD_PIDR2:
		/* report a GICv3 compliant implementation */
		return 0x3b;
	}

	return 0;
}

/* We want to avoid outer shareable. */
u64 vgic_sanitise_shareability(u64 field)
{
	switch (field) {
	case GIC_BASER_OuterShareable:
		return GIC_BASER_InnerShareable;
	default:
		return field;
	}
}

/* Avoid any inner non-cacheable mapping. */
u64 vgic_sanitise_inner_cacheability(u64 field)
{
	switch (field) {
	case GIC_BASER_CACHE_nCnB:
	case GIC_BASER_CACHE_nC:
		return GIC_BASER_CACHE_RaWb;
	default:
		return field;
	}
}

/* Non-cacheable or same-as-inner are OK. */
u64 vgic_sanitise_outer_cacheability(u64 field)
{
	switch (field) {
	case GIC_BASER_CACHE_SameAsInner:
	case GIC_BASER_CACHE_nC:
		return field;
	default:
		return GIC_BASER_CACHE_nC;
	}
}

u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
			u64 (*sanitise_fn)(u64))
{
	u64 field = (reg & field_mask) >> field_shift;

	field = sanitise_fn(field) << field_shift;
	return (reg & ~field_mask) | field;
}

#define PROPBASER_RES0_MASK						\
	(GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
#define PENDBASER_RES0_MASK						\
	(BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |	\
	 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))

static u64 vgic_sanitise_pendbaser(u64 reg)
{
	reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
				  GICR_PENDBASER_SHAREABILITY_SHIFT,
				  vgic_sanitise_shareability);
	reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
				  GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
				  vgic_sanitise_inner_cacheability);
	reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
				  GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
				  vgic_sanitise_outer_cacheability);

	reg &= ~PENDBASER_RES0_MASK;
	reg &= ~GENMASK_ULL(51, 48);

	return reg;
}

static u64 vgic_sanitise_propbaser(u64 reg)
{
	reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
				  GICR_PROPBASER_SHAREABILITY_SHIFT,
				  vgic_sanitise_shareability);
	reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
				  GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
				  vgic_sanitise_inner_cacheability);
	reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
				  GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
				  vgic_sanitise_outer_cacheability);

	reg &= ~PROPBASER_RES0_MASK;
	reg &= ~GENMASK_ULL(51, 48);
	return reg;
}

static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
					     gpa_t addr, unsigned int len)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;

	return extract_bytes(dist->propbaser, addr & 7, len);
}

static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
				     gpa_t addr, unsigned int len,
				     unsigned long val)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	u64 propbaser = dist->propbaser;

	/* Storing a value with LPIs already enabled is undefined */
	if (vgic_cpu->lpis_enabled)
		return;

	propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
	propbaser = vgic_sanitise_propbaser(propbaser);

	dist->propbaser = propbaser;
}

static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
					     gpa_t addr, unsigned int len)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;

	return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
}

static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
				     gpa_t addr, unsigned int len,
				     unsigned long val)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	u64 pendbaser = vgic_cpu->pendbaser;

	/* Storing a value with LPIs already enabled is undefined */
	if (vgic_cpu->lpis_enabled)
		return;

	pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
	pendbaser = vgic_sanitise_pendbaser(pendbaser);

	vgic_cpu->pendbaser = pendbaser;
}

/*
 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 * redistributors, while SPIs are covered by registers in the distributor
 * block. Trying to set private IRQs in this block gets ignored.
 * We take some special care here to fix the calculation of the register
 * offset.
 */
#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)	\
	{								\
		.reg_offset = off,					\
		.bits_per_irq = bpi,					\
		.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,		\
		.access_flags = acc,					\
		.read = vgic_mmio_read_raz,				\
		.write = vgic_mmio_write_wi,				\
	}, {								\
		.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,	\
		.bits_per_irq = bpi,					\
		.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,	\
		.access_flags = acc,					\
		.read = rd,						\
		.write = wr,						\
	}

static const struct vgic_register_region vgic_v3_dist_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
		vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
		vgic_mmio_read_config, vgic_mmio_write_config, 2,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
		vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
		vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
		vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
		vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
		vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
		vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
		vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
		vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
		vgic_mmio_read_config, vgic_mmio_write_config, 8,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
};

unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
{
	dev->regions = vgic_v3_dist_registers;
	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);

	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);

	return SZ_64K;
}

int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
{
	struct kvm_vcpu *vcpu;
	int c, ret = 0;

	kvm_for_each_vcpu(c, vcpu, kvm) {
		gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
		gpa_t sgi_base = rd_base + SZ_64K;
		struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
		struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;

		kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
		rd_dev->base_addr = rd_base;
		rd_dev->iodev_type = IODEV_REDIST;
		rd_dev->regions = vgic_v3_rdbase_registers;
		rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
		rd_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
					      SZ_64K, &rd_dev->dev);
		mutex_unlock(&kvm->slots_lock);

		if (ret)
			break;

		kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
		sgi_dev->base_addr = sgi_base;
		sgi_dev->iodev_type = IODEV_REDIST;
		sgi_dev->regions = vgic_v3_sgibase_registers;
		sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
		sgi_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
					      SZ_64K, &sgi_dev->dev);
		mutex_unlock(&kvm->slots_lock);
		if (ret) {
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &rd_dev->dev);
			break;
		}
	}

	if (ret) {
		/* The current c failed, so we start with the previous one. */
		for (c--; c >= 0; c--) {
			struct vgic_cpu *vgic_cpu;

			vcpu = kvm_get_vcpu(kvm, c);
			vgic_cpu = &vcpu->arch.vgic_cpu;
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &vgic_cpu->rd_iodev.dev);
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &vgic_cpu->sgi_iodev.dev);
		}
	}

	return ret;
}

/*
 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 * generation register ICC_SGI1R_EL1) with a given VCPU.
 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 * return -1.
 */
static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
{
	unsigned long affinity;
	int level0;

	/*
	 * Split the current VCPU's MPIDR into affinity level 0 and the
	 * rest as this is what we have to compare against.
	 */
	affinity = kvm_vcpu_get_mpidr_aff(vcpu);
	level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
	affinity &= ~MPIDR_LEVEL_MASK;

	/* bail out if the upper three levels don't match */
	if (sgi_aff != affinity)
		return -1;

	/* Is this VCPU's bit set in the mask ? */
	if (!(sgi_cpu_mask & BIT(level0)))
		return -1;

	return level0;
}

/*
 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 * so provide a wrapper to use the existing defines to isolate a certain
 * affinity level.
 */
#define SGI_AFFINITY_LEVEL(reg, level) \
	((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
	>> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))

/**
 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 * @vcpu: The VCPU requesting a SGI
 * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
 *
 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 * This will trap in sys_regs.c and call this function.
 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 * target processors as well as a bitmask of 16 Aff0 CPUs.
 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 * check for matching ones. If this bit is set, we signal all, but not the
 * calling VCPU.
 */
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
{
	struct kvm *kvm = vcpu->kvm;
	struct kvm_vcpu *c_vcpu;
	u16 target_cpus;
	u64 mpidr;
	int sgi, c;
	int vcpu_id = vcpu->vcpu_id;
	bool broadcast;

	sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
	broadcast = reg & BIT(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
	target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
	mpidr = SGI_AFFINITY_LEVEL(reg, 3);
	mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
	mpidr |= SGI_AFFINITY_LEVEL(reg, 1);

	/*
	 * We iterate over all VCPUs to find the MPIDRs matching the request.
	 * If we have handled one CPU, we clear its bit to detect early
	 * if we are already finished. This avoids iterating through all
	 * VCPUs when most of the times we just signal a single VCPU.
	 */
	kvm_for_each_vcpu(c, c_vcpu, kvm) {
		struct vgic_irq *irq;

		/* Exit early if we have dealt with all requested CPUs */
		if (!broadcast && target_cpus == 0)
			break;

		/* Don't signal the calling VCPU */
		if (broadcast && c == vcpu_id)
			continue;

		if (!broadcast) {
			int level0;

			level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
			if (level0 == -1)
				continue;

			/* remove this matching VCPU from the mask */
			target_cpus &= ~BIT(level0);
		}

		irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);

		spin_lock(&irq->irq_lock);
		irq->pending = true;

		vgic_queue_irq_unlock(vcpu->kvm, irq);
		vgic_put_irq(vcpu->kvm, irq);
	}
}
Commit	Line	Data
ed9b8cef AP	1	/*
	2	* VGICv3 MMIO handling functions
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/irqchip/arm-gic-v3.h>
	15	#include <linux/kvm.h>
	16	#include <linux/kvm_host.h>
	17	#include <kvm/iodev.h>
	18	#include <kvm/arm_vgic.h>
	19
	20	#include <asm/kvm_emulate.h>
	21
	22	#include "vgic.h"
	23	#include "vgic-mmio.h"
	24
741972d8 AP	25	/* extract @num bytes at @offset bytes offset in data */
	26	static unsigned long extract_bytes(unsigned long data, unsigned int offset,
	27	unsigned int num)
	28	{
	29	return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
	30	}
	31
0aa1de57 AP	32	/* allows updates of any half of a 64-bit register (or the whole thing) */
	33	static u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
	34	unsigned long val)
	35	{
	36	int lower = (offset & 4) * 8;
	37	int upper = lower + 8 * len - 1;
	38
	39	reg &= ~GENMASK_ULL(upper, lower);
	40	val &= GENMASK_ULL(len * 8 - 1, 0);
	41
	42	return reg \| ((u64)val << lower);
	43	}
	44
59c5ab40 AP	45	bool vgic_has_its(struct kvm *kvm)
	46	{
	47	struct vgic_dist *dist = &kvm->arch.vgic;
	48
	49	if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
	50	return false;
	51
1085fdc6	52	return dist->has_its;
59c5ab40 AP	53	}
59c5ab40 AP	54
fd59ed3b AP	55	static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
	56	gpa_t addr, unsigned int len)
	57	{
	58	u32 value = 0;
	59
	60	switch (addr & 0x0c) {
	61	case GICD_CTLR:
	62	if (vcpu->kvm->arch.vgic.enabled)
	63	value \|= GICD_CTLR_ENABLE_SS_G1;
	64	value \|= GICD_CTLR_ARE_NS \| GICD_CTLR_DS;
	65	break;
	66	case GICD_TYPER:
	67	value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
	68	value = (value >> 5) - 1;
	69	value \|= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
	70	break;
	71	case GICD_IIDR:
	72	value = (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	73	break;
	74	default:
	75	return 0;
	76	}
	77
	78	return value;
	79	}
	80
	81	static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
	82	gpa_t addr, unsigned int len,
	83	unsigned long val)
	84	{
	85	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	86	bool was_enabled = dist->enabled;
	87
	88	switch (addr & 0x0c) {
	89	case GICD_CTLR:
	90	dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
	91
	92	if (!was_enabled && dist->enabled)
	93	vgic_kick_vcpus(vcpu->kvm);
	94	break;
	95	case GICD_TYPER:
	96	case GICD_IIDR:
	97	return;
	98	}
	99	}
	100
78a714ab AP	101	static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
	102	gpa_t addr, unsigned int len)
	103	{
	104	int intid = VGIC_ADDR_TO_INTID(addr, 64);
	105	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
5dd4b924	106	unsigned long ret = 0;
78a714ab AP	107
	108	if (!irq)
	109	return 0;
	110
	111	/* The upper word is RAZ for us. */
5dd4b924 AP	112	if (!(addr & 4))
5dd4b924 AP	113	ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
78a714ab	114
5dd4b924 AP	115	vgic_put_irq(vcpu->kvm, irq);
5dd4b924 AP	116	return ret;
78a714ab AP	117	}
	118
	119	static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
	120	gpa_t addr, unsigned int len,
	121	unsigned long val)
	122	{
	123	int intid = VGIC_ADDR_TO_INTID(addr, 64);
5dd4b924	124	struct vgic_irq *irq;
78a714ab AP	125
	126	/* The upper word is WI for us since we don't implement Aff3. */
	127	if (addr & 4)
	128	return;
	129
5dd4b924 AP	130	irq = vgic_get_irq(vcpu->kvm, NULL, intid);
	131
	132	if (!irq)
	133	return;
	134
78a714ab AP	135	spin_lock(&irq->irq_lock);
	136
	137	/* We only care about and preserve Aff0, Aff1 and Aff2. */
	138	irq->mpidr = val & GENMASK(23, 0);
	139	irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
	140
	141	spin_unlock(&irq->irq_lock);
5dd4b924	142	vgic_put_irq(vcpu->kvm, irq);
78a714ab AP	143	}
78a714ab AP	144
59c5ab40 AP	145	static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
	146	gpa_t addr, unsigned int len)
	147	{
	148	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	149
	150	return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
	151	}
	152
	153
	154	static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
	155	gpa_t addr, unsigned int len,
	156	unsigned long val)
	157	{
	158	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	159	bool was_enabled = vgic_cpu->lpis_enabled;
	160
	161	if (!vgic_has_its(vcpu->kvm))
	162	return;
	163
	164	vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
	165
	166	if (!was_enabled && vgic_cpu->lpis_enabled) {
	167	/* Eventually do something */
	168	}
	169	}
	170
741972d8 AP	171	static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
	172	gpa_t addr, unsigned int len)
	173	{
	174	unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
	175	int target_vcpu_id = vcpu->vcpu_id;
	176	u64 value;
	177
	178	value = (mpidr & GENMASK(23, 0)) << 32;
	179	value \|= ((target_vcpu_id & 0xffff) << 8);
	180	if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
	181	value \|= GICR_TYPER_LAST;
	182
	183	return extract_bytes(value, addr & 7, len);
	184	}
	185
	186	static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
	187	gpa_t addr, unsigned int len)
	188	{
	189	return (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	190	}
	191
54f59d2b AP	192	static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
	193	gpa_t addr, unsigned int len)
	194	{
	195	switch (addr & 0xffff) {
	196	case GICD_PIDR2:
	197	/* report a GICv3 compliant implementation */
	198	return 0x3b;
	199	}
	200
	201	return 0;
	202	}
	203
0aa1de57 AP	204	/* We want to avoid outer shareable. */
	205	u64 vgic_sanitise_shareability(u64 field)
	206	{
	207	switch (field) {
	208	case GIC_BASER_OuterShareable:
	209	return GIC_BASER_InnerShareable;
	210	default:
	211	return field;
	212	}
	213	}
	214
	215	/* Avoid any inner non-cacheable mapping. */
	216	u64 vgic_sanitise_inner_cacheability(u64 field)
	217	{
	218	switch (field) {
	219	case GIC_BASER_CACHE_nCnB:
	220	case GIC_BASER_CACHE_nC:
	221	return GIC_BASER_CACHE_RaWb;
	222	default:
	223	return field;
	224	}
	225	}
	226
	227	/* Non-cacheable or same-as-inner are OK. */
	228	u64 vgic_sanitise_outer_cacheability(u64 field)
	229	{
	230	switch (field) {
	231	case GIC_BASER_CACHE_SameAsInner:
	232	case GIC_BASER_CACHE_nC:
	233	return field;
	234	default:
	235	return GIC_BASER_CACHE_nC;
	236	}
	237	}
	238
	239	u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
	240	u64 (*sanitise_fn)(u64))
	241	{
	242	u64 field = (reg & field_mask) >> field_shift;
	243
	244	field = sanitise_fn(field) << field_shift;
	245	return (reg & ~field_mask) \| field;
	246	}
	247
	248	#define PROPBASER_RES0_MASK \
	249	(GENMASK_ULL(63, 59) \| GENMASK_ULL(55, 52) \| GENMASK_ULL(6, 5))
	250	#define PENDBASER_RES0_MASK \
	251	(BIT_ULL(63) \| GENMASK_ULL(61, 59) \| GENMASK_ULL(55, 52) \| \
	252	GENMASK_ULL(15, 12) \| GENMASK_ULL(6, 0))
	253
	254	static u64 vgic_sanitise_pendbaser(u64 reg)
	255	{
	256	reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
	257	GICR_PENDBASER_SHAREABILITY_SHIFT,
	258	vgic_sanitise_shareability);
	259	reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
	260	GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
	261	vgic_sanitise_inner_cacheability);
	262	reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
	263	GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
	264	vgic_sanitise_outer_cacheability);
	265
	266	reg &= ~PENDBASER_RES0_MASK;
	267	reg &= ~GENMASK_ULL(51, 48);
268
269	return reg;
270	}
271
272	static u64 vgic_sanitise_propbaser(u64 reg)
273	{
274	reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
275	GICR_PROPBASER_SHAREABILITY_SHIFT,
276	vgic_sanitise_shareability);
277	reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
278	GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
279	vgic_sanitise_inner_cacheability);
280	reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
281	GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
282	vgic_sanitise_outer_cacheability);
283
284	reg &= ~PROPBASER_RES0_MASK;
285	reg &= ~GENMASK_ULL(51, 48);
286	return reg;
287	}
288
289	static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
290	gpa_t addr, unsigned int len)
291	{
292	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
293
294	return extract_bytes(dist->propbaser, addr & 7, len);
295	}
296
297	static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
298	gpa_t addr, unsigned int len,
299	unsigned long val)
300	{
301	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
302	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
303	u64 propbaser = dist->propbaser;
304
305	/* Storing a value with LPIs already enabled is undefined */
306	if (vgic_cpu->lpis_enabled)
307	return;
308
309	propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
310	propbaser = vgic_sanitise_propbaser(propbaser);
311
312	dist->propbaser = propbaser;
313	}
314
315	static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
316	gpa_t addr, unsigned int len)
317	{
318	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
319
320	return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
321	}
322
323	static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
324	gpa_t addr, unsigned int len,
325	unsigned long val)
326	{
327	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
328	u64 pendbaser = vgic_cpu->pendbaser;
329
330	/* Storing a value with LPIs already enabled is undefined */
331	if (vgic_cpu->lpis_enabled)
332	return;
333
334	pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
335	pendbaser = vgic_sanitise_pendbaser(pendbaser);
336
337	vgic_cpu->pendbaser = pendbaser;
338	}
339
ed9b8cef AP	340	/*
	341	* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
	342	* redistributors, while SPIs are covered by registers in the distributor
	343	* block. Trying to set private IRQs in this block gets ignored.
	344	* We take some special care here to fix the calculation of the register
	345	* offset.
	346	*/
	347	#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
	348	{ \
	349	.reg_offset = off, \
	350	.bits_per_irq = bpi, \
	351	.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	352	.access_flags = acc, \
	353	.read = vgic_mmio_read_raz, \
	354	.write = vgic_mmio_write_wi, \
	355	}, { \
	356	.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	357	.bits_per_irq = bpi, \
	358	.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
	359	.access_flags = acc, \
	360	.read = rd, \
	361	.write = wr, \
	362	}
	363
	364	static const struct vgic_register_region vgic_v3_dist_registers[] = {
	365	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
fd59ed3b	366	vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
ed9b8cef AP	367	VGIC_ACCESS_32bit),
	368	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
	369	vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
	370	VGIC_ACCESS_32bit),
	371	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
	372	vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
	373	VGIC_ACCESS_32bit),
	374	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
	375	vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
	376	VGIC_ACCESS_32bit),
	377	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
	378	vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
	379	VGIC_ACCESS_32bit),
	380	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
	381	vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
	382	VGIC_ACCESS_32bit),
	383	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
	384	vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
	385	VGIC_ACCESS_32bit),
	386	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
	387	vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
	388	VGIC_ACCESS_32bit),
	389	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
	390	vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
	391	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	392	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
	393	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	394	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	395	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
	396	vgic_mmio_read_config, vgic_mmio_write_config, 2,
	397	VGIC_ACCESS_32bit),
	398	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
	399	vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
	400	VGIC_ACCESS_32bit),
	401	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
78a714ab	402	vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
ed9b8cef AP	403	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
ed9b8cef AP	404	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
54f59d2b	405	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef AP	406	VGIC_ACCESS_32bit),
	407	};
	408
	409	static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	410	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
59c5ab40	411	vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
ed9b8cef AP	412	VGIC_ACCESS_32bit),
ed9b8cef AP	413	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
741972d8	414	vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
ed9b8cef AP	415	VGIC_ACCESS_32bit),
ed9b8cef AP	416	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
741972d8	417	vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
ed9b8cef AP	418	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
ed9b8cef AP	419	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
0aa1de57	420	vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
ed9b8cef AP	421	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
ed9b8cef AP	422	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
0aa1de57	423	vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
ed9b8cef AP	424	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
ed9b8cef AP	425	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
54f59d2b	426	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef AP	427	VGIC_ACCESS_32bit),
	428	};
	429
	430	static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
	431	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
	432	vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
	433	VGIC_ACCESS_32bit),
	434	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
	435	vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
	436	VGIC_ACCESS_32bit),
	437	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
	438	vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
	439	VGIC_ACCESS_32bit),
	440	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
	441	vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
	442	VGIC_ACCESS_32bit),
	443	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
	444	vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
	445	VGIC_ACCESS_32bit),
	446	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
	447	vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
	448	VGIC_ACCESS_32bit),
	449	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
	450	vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
	451	VGIC_ACCESS_32bit),
	452	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
	453	vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
	454	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	455	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
	456	vgic_mmio_read_config, vgic_mmio_write_config, 8,
	457	VGIC_ACCESS_32bit),
	458	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
	459	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	460	VGIC_ACCESS_32bit),
	461	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
	462	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	463	VGIC_ACCESS_32bit),
	464	};
	465
	466	unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
	467	{
	468	dev->regions = vgic_v3_dist_registers;
	469	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
	470
	471	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
	472
	473	return SZ_64K;
	474	}
	475
	476	int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
	477	{
ed9b8cef	478	struct kvm_vcpu *vcpu;
ed9b8cef AP	479	int c, ret = 0;
ed9b8cef AP	480
ed9b8cef AP	481	kvm_for_each_vcpu(c, vcpu, kvm) {
	482	gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
	483	gpa_t sgi_base = rd_base + SZ_64K;
8f6cdc1c AP	484	struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
8f6cdc1c AP	485	struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
ed9b8cef AP	486
	487	kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
	488	rd_dev->base_addr = rd_base;
59c5ab40	489	rd_dev->iodev_type = IODEV_REDIST;
ed9b8cef AP	490	rd_dev->regions = vgic_v3_rdbase_registers;
	491	rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
	492	rd_dev->redist_vcpu = vcpu;
	493
	494	mutex_lock(&kvm->slots_lock);
	495	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
	496	SZ_64K, &rd_dev->dev);
	497	mutex_unlock(&kvm->slots_lock);
	498
	499	if (ret)
	500	break;
	501
	502	kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
	503	sgi_dev->base_addr = sgi_base;
59c5ab40	504	sgi_dev->iodev_type = IODEV_REDIST;
ed9b8cef AP	505	sgi_dev->regions = vgic_v3_sgibase_registers;
	506	sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
	507	sgi_dev->redist_vcpu = vcpu;
	508
	509	mutex_lock(&kvm->slots_lock);
	510	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
	511	SZ_64K, &sgi_dev->dev);
	512	mutex_unlock(&kvm->slots_lock);
	513	if (ret) {
	514	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
	515	&rd_dev->dev);
	516	break;
	517	}
	518	}
	519
	520	if (ret) {
	521	/* The current c failed, so we start with the previous one. */
	522	for (c--; c >= 0; c--) {
8f6cdc1c AP	523	struct vgic_cpu *vgic_cpu;
	524
	525	vcpu = kvm_get_vcpu(kvm, c);
	526	vgic_cpu = &vcpu->arch.vgic_cpu;
ed9b8cef	527	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
8f6cdc1c	528	&vgic_cpu->rd_iodev.dev);
ed9b8cef	529	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
8f6cdc1c	530	&vgic_cpu->sgi_iodev.dev);
ed9b8cef	531	}
ed9b8cef AP	532	}
	533
	534	return ret;
	535	}
621ecd8d AP	536
	537	/*
	538	* Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
	539	* generation register ICC_SGI1R_EL1) with a given VCPU.
	540	* If the VCPU's MPIDR matches, return the level0 affinity, otherwise
	541	* return -1.
	542	*/
	543	static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
	544	{
	545	unsigned long affinity;
	546	int level0;
	547
	548	/*
	549	* Split the current VCPU's MPIDR into affinity level 0 and the
	550	* rest as this is what we have to compare against.
	551	*/
	552	affinity = kvm_vcpu_get_mpidr_aff(vcpu);
	553	level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
	554	affinity &= ~MPIDR_LEVEL_MASK;
	555
	556	/* bail out if the upper three levels don't match */
	557	if (sgi_aff != affinity)
	558	return -1;
	559
	560	/* Is this VCPU's bit set in the mask ? */
	561	if (!(sgi_cpu_mask & BIT(level0)))
	562	return -1;
	563
	564	return level0;
	565	}
	566
	567	/*
	568	* The ICC_SGI* registers encode the affinity differently from the MPIDR,
	569	* so provide a wrapper to use the existing defines to isolate a certain
	570	* affinity level.
	571	*/
	572	#define SGI_AFFINITY_LEVEL(reg, level) \
	573	((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
	574	>> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
	575
	576	/**
	577	* vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
	578	* @vcpu: The VCPU requesting a SGI
	579	* @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
	580	*
	581	* With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
	582	* This will trap in sys_regs.c and call this function.
	583	* This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
	584	* target processors as well as a bitmask of 16 Aff0 CPUs.
	585	* If the interrupt routing mode bit is not set, we iterate over all VCPUs to
	586	* check for matching ones. If this bit is set, we signal all, but not the
	587	* calling VCPU.
	588	*/
	589	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
	590	{
	591	struct kvm *kvm = vcpu->kvm;
	592	struct kvm_vcpu *c_vcpu;
	593	u16 target_cpus;
	594	u64 mpidr;
	595	int sgi, c;
	596	int vcpu_id = vcpu->vcpu_id;
	597	bool broadcast;
	598
	599	sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
600	broadcast = reg & BIT(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
601	target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
602	mpidr = SGI_AFFINITY_LEVEL(reg, 3);
603	mpidr \|= SGI_AFFINITY_LEVEL(reg, 2);
604	mpidr \|= SGI_AFFINITY_LEVEL(reg, 1);
605
606	/*
607	* We iterate over all VCPUs to find the MPIDRs matching the request.
608	* If we have handled one CPU, we clear its bit to detect early
609	* if we are already finished. This avoids iterating through all
610	* VCPUs when most of the times we just signal a single VCPU.
611	*/
612	kvm_for_each_vcpu(c, c_vcpu, kvm) {
613	struct vgic_irq *irq;
614
615	/* Exit early if we have dealt with all requested CPUs */
616	if (!broadcast && target_cpus == 0)
617	break;
618
619	/* Don't signal the calling VCPU */
620	if (broadcast && c == vcpu_id)
621	continue;
622
623	if (!broadcast) {
624	int level0;
625
626	level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
627	if (level0 == -1)
628	continue;
629
630	/* remove this matching VCPU from the mask */
631	target_cpus &= ~BIT(level0);
632	}
633
634	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
635
636	spin_lock(&irq->irq_lock);
637	irq->pending = true;
638
639	vgic_queue_irq_unlock(vcpu->kvm, irq);
5dd4b924	640	vgic_put_irq(vcpu->kvm, irq);
621ecd8d AP	641	}
621ecd8d AP	642	}