[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic-mmio-v3.c

/*
 * VGICv3 MMIO handling functions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/iodev.h>
#include <kvm/arm_vgic.h>

#include <asm/kvm_emulate.h>

#include "vgic.h"
#include "vgic-mmio.h"

static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
					    gpa_t addr, unsigned int len)
{
	u32 value = 0;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		if (vcpu->kvm->arch.vgic.enabled)
			value |= GICD_CTLR_ENABLE_SS_G1;
		value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
		break;
	case GICD_TYPER:
		value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		value = (value >> 5) - 1;
		value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
		break;
	case GICD_IIDR:
		value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
		break;
	default:
		return 0;
	}

	return value;
}

static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
				    gpa_t addr, unsigned int len,
				    unsigned long val)
{
	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	bool was_enabled = dist->enabled;

	switch (addr & 0x0c) {
	case GICD_CTLR:
		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;

		if (!was_enabled && dist->enabled)
			vgic_kick_vcpus(vcpu->kvm);
		break;
	case GICD_TYPER:
	case GICD_IIDR:
		return;
	}
}

/*
 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 * redistributors, while SPIs are covered by registers in the distributor
 * block. Trying to set private IRQs in this block gets ignored.
 * We take some special care here to fix the calculation of the register
 * offset.
 */
#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)	\
	{								\
		.reg_offset = off,					\
		.bits_per_irq = bpi,					\
		.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,		\
		.access_flags = acc,					\
		.read = vgic_mmio_read_raz,				\
		.write = vgic_mmio_write_wi,				\
	}, {								\
		.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,	\
		.bits_per_irq = bpi,					\
		.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,	\
		.access_flags = acc,					\
		.read = rd,						\
		.write = wr,						\
	}

static const struct vgic_register_region vgic_v3_dist_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
		vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
		vgic_mmio_read_config, vgic_mmio_write_config, 2,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
		VGIC_ACCESS_32bit),
};

static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
		vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
		vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
		vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
		vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
		vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
		vgic_mmio_read_config, vgic_mmio_write_config, 8,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		VGIC_ACCESS_32bit),
};

unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
{
	dev->regions = vgic_v3_dist_registers;
	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);

	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);

	return SZ_64K;
}

int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
{
	int nr_vcpus = atomic_read(&kvm->online_vcpus);
	struct kvm_vcpu *vcpu;
	struct vgic_io_device *devices;
	int c, ret = 0;

	devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
			  GFP_KERNEL);
	if (!devices)
		return -ENOMEM;

	kvm_for_each_vcpu(c, vcpu, kvm) {
		gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
		gpa_t sgi_base = rd_base + SZ_64K;
		struct vgic_io_device *rd_dev = &devices[c * 2];
		struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];

		kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
		rd_dev->base_addr = rd_base;
		rd_dev->regions = vgic_v3_rdbase_registers;
		rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
		rd_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
					      SZ_64K, &rd_dev->dev);
		mutex_unlock(&kvm->slots_lock);

		if (ret)
			break;

		kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
		sgi_dev->base_addr = sgi_base;
		sgi_dev->regions = vgic_v3_sgibase_registers;
		sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
		sgi_dev->redist_vcpu = vcpu;

		mutex_lock(&kvm->slots_lock);
		ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
					      SZ_64K, &sgi_dev->dev);
		mutex_unlock(&kvm->slots_lock);
		if (ret) {
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &rd_dev->dev);
			break;
		}
	}

	if (ret) {
		/* The current c failed, so we start with the previous one. */
		for (c--; c >= 0; c--) {
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &devices[c * 2].dev);
			kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
						  &devices[c * 2 + 1].dev);
		}
		kfree(devices);
	} else {
		kvm->arch.vgic.redist_iodevs = devices;
	}

	return ret;
}
Commit	Line	Data
ed9b8cef AP	1	/*
	2	* VGICv3 MMIO handling functions
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/irqchip/arm-gic-v3.h>
	15	#include <linux/kvm.h>
	16	#include <linux/kvm_host.h>
	17	#include <kvm/iodev.h>
	18	#include <kvm/arm_vgic.h>
	19
	20	#include <asm/kvm_emulate.h>
	21
	22	#include "vgic.h"
	23	#include "vgic-mmio.h"
	24
fd59ed3b AP	25	static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
	26	gpa_t addr, unsigned int len)
	27	{
	28	u32 value = 0;
	29
	30	switch (addr & 0x0c) {
	31	case GICD_CTLR:
	32	if (vcpu->kvm->arch.vgic.enabled)
	33	value \|= GICD_CTLR_ENABLE_SS_G1;
	34	value \|= GICD_CTLR_ARE_NS \| GICD_CTLR_DS;
	35	break;
	36	case GICD_TYPER:
	37	value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
	38	value = (value >> 5) - 1;
	39	value \|= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
	40	break;
	41	case GICD_IIDR:
	42	value = (PRODUCT_ID_KVM << 24) \| (IMPLEMENTER_ARM << 0);
	43	break;
	44	default:
	45	return 0;
	46	}
	47
	48	return value;
	49	}
	50
	51	static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
	52	gpa_t addr, unsigned int len,
	53	unsigned long val)
	54	{
	55	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
	56	bool was_enabled = dist->enabled;
	57
	58	switch (addr & 0x0c) {
	59	case GICD_CTLR:
	60	dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
	61
	62	if (!was_enabled && dist->enabled)
	63	vgic_kick_vcpus(vcpu->kvm);
	64	break;
	65	case GICD_TYPER:
	66	case GICD_IIDR:
	67	return;
	68	}
	69	}
	70
ed9b8cef AP	71	/*
	72	* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
	73	* redistributors, while SPIs are covered by registers in the distributor
	74	* block. Trying to set private IRQs in this block gets ignored.
	75	* We take some special care here to fix the calculation of the register
	76	* offset.
	77	*/
	78	#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
	79	{ \
	80	.reg_offset = off, \
	81	.bits_per_irq = bpi, \
	82	.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	83	.access_flags = acc, \
	84	.read = vgic_mmio_read_raz, \
	85	.write = vgic_mmio_write_wi, \
	86	}, { \
	87	.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
	88	.bits_per_irq = bpi, \
	89	.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
	90	.access_flags = acc, \
	91	.read = rd, \
	92	.write = wr, \
	93	}
	94
	95	static const struct vgic_register_region vgic_v3_dist_registers[] = {
	96	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
fd59ed3b	97	vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
ed9b8cef AP	98	VGIC_ACCESS_32bit),
	99	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
	100	vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
	101	VGIC_ACCESS_32bit),
	102	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
	103	vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
	104	VGIC_ACCESS_32bit),
	105	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
	106	vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
	107	VGIC_ACCESS_32bit),
	108	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
	109	vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
	110	VGIC_ACCESS_32bit),
	111	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
	112	vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
	113	VGIC_ACCESS_32bit),
	114	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
	115	vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
	116	VGIC_ACCESS_32bit),
	117	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
	118	vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
	119	VGIC_ACCESS_32bit),
	120	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
	121	vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
	122	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	123	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
	124	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	125	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
	126	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
	127	vgic_mmio_read_config, vgic_mmio_write_config, 2,
	128	VGIC_ACCESS_32bit),
	129	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
	130	vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
	131	VGIC_ACCESS_32bit),
	132	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
	133	vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
	134	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	135	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
	136	vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
	137	VGIC_ACCESS_32bit),
	138	};
	139
	140	static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
	141	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
	142	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	143	VGIC_ACCESS_32bit),
	144	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
	145	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
	146	VGIC_ACCESS_32bit),
	147	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
	148	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	149	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	150	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
	151	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	152	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	153	REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
	154	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
	155	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
	156	REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
	157	vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
	158	VGIC_ACCESS_32bit),
	159	};
	160
	161	static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
162	REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
163	vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
164	VGIC_ACCESS_32bit),
165	REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
166	vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
167	VGIC_ACCESS_32bit),
168	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
169	vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
170	VGIC_ACCESS_32bit),
171	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
172	vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
173	VGIC_ACCESS_32bit),
174	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
175	vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
176	VGIC_ACCESS_32bit),
177	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
178	vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
179	VGIC_ACCESS_32bit),
180	REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
181	vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
182	VGIC_ACCESS_32bit),
183	REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
184	vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
185	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
186	REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
187	vgic_mmio_read_config, vgic_mmio_write_config, 8,
188	VGIC_ACCESS_32bit),
189	REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
190	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
191	VGIC_ACCESS_32bit),
192	REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
193	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
194	VGIC_ACCESS_32bit),
195	};
196
197	unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
198	{
199	dev->regions = vgic_v3_dist_registers;
200	dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
201
202	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
203
204	return SZ_64K;
205	}
206
207	int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
208	{
209	int nr_vcpus = atomic_read(&kvm->online_vcpus);
210	struct kvm_vcpu *vcpu;
211	struct vgic_io_device *devices;
212	int c, ret = 0;
213
214	devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
215	GFP_KERNEL);
216	if (!devices)
217	return -ENOMEM;
218
219	kvm_for_each_vcpu(c, vcpu, kvm) {
220	gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
221	gpa_t sgi_base = rd_base + SZ_64K;
222	struct vgic_io_device rd_dev = &devices[c 2];
223	struct vgic_io_device sgi_dev = &devices[c 2 + 1];
224
225	kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
226	rd_dev->base_addr = rd_base;
227	rd_dev->regions = vgic_v3_rdbase_registers;
228	rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
229	rd_dev->redist_vcpu = vcpu;
230
231	mutex_lock(&kvm->slots_lock);
232	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
233	SZ_64K, &rd_dev->dev);
234	mutex_unlock(&kvm->slots_lock);
235
236	if (ret)
237	break;
238
239	kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
240	sgi_dev->base_addr = sgi_base;
241	sgi_dev->regions = vgic_v3_sgibase_registers;
242	sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
243	sgi_dev->redist_vcpu = vcpu;
244
245	mutex_lock(&kvm->slots_lock);
246	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
247	SZ_64K, &sgi_dev->dev);
248	mutex_unlock(&kvm->slots_lock);
249	if (ret) {
250	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
251	&rd_dev->dev);
252	break;
253	}
254	}
255
256	if (ret) {
257	/* The current c failed, so we start with the previous one. */
258	for (c--; c >= 0; c--) {
259	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
260	&devices[c * 2].dev);
261	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
262	&devices[c * 2 + 1].dev);
263	}
264	kfree(devices);
265	} else {
266	kvm->arch.vgic.redist_iodevs = devices;
267	}
268
269	return ret;
270	}