[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic-v2.c

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>

#include "vgic.h"

/*
 * Call this function to convert a u64 value to an unsigned long * bitmask
 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
 *
 * Warning: Calling this function may modify *val.
 */
static unsigned long *u64_to_bitmask(u64 *val)
{
#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
	*val = (*val >> 32) | (*val << 32);
#endif
	return (unsigned long *)val;
}

void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;

	if (cpuif->vgic_misr & GICH_MISR_EOI) {
		u64 eisr = cpuif->vgic_eisr;
		unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
		int lr;

		for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
			u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;

			WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);

			kvm_notify_acked_irq(vcpu->kvm, 0,
					     intid - VGIC_NR_PRIVATE_IRQS);
		}
	}

	/* check and disable underflow maintenance IRQ */
	cpuif->vgic_hcr &= ~GICH_HCR_UIE;

	/*
	 * In the next iterations of the vcpu loop, if we sync the
	 * vgic state after flushing it, but before entering the guest
	 * (this happens for pending signals and vmid rollovers), then
	 * make sure we don't pick up any old maintenance interrupts
	 * here.
	 */
	cpuif->vgic_eisr = 0;
}

void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;

	cpuif->vgic_hcr |= GICH_HCR_UIE;
}

/*
 * transfer the content of the LRs back into the corresponding ap_list:
 * - active bit is transferred as is
 * - pending bit is
 *   - transferred as is in case of edge sensitive IRQs
 *   - set to the line-level (resample time) for level sensitive IRQs
 */
void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
	int lr;

	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
		u32 val = cpuif->vgic_lr[lr];
		u32 intid = val & GICH_LR_VIRTUALID;
		struct vgic_irq *irq;

		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);

		spin_lock(&irq->irq_lock);

		/* Always preserve the active bit */
		irq->active = !!(val & GICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & GICH_LR_PENDING_BIT)) {
			irq->pending = true;

			if (vgic_irq_is_sgi(intid)) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & GICH_LR_PENDING_BIT))
				irq->soft_pending = false;

			irq->pending = irq->line_level || irq->soft_pending;
		}

		spin_unlock(&irq->irq_lock);
	}
}

/*
 * Populates the particular LR with the state of a given IRQ:
 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 * - for a level sensitive IRQ the pending state value is unchanged;
 *   it is dictated directly by the input level
 *
 * If @irq describes an SGI with multiple sources, we choose the
 * lowest-numbered source VCPU and clear that bit in the source bitmap.
 *
 * The irq_lock must be held by the caller.
 */
void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 val = irq->intid;

	if (irq->pending) {
		val |= GICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending = false;

		if (vgic_irq_is_sgi(irq->intid)) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending = true;
		}
	}

	if (irq->active)
		val |= GICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= GICH_LR_HW;
		val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= GICH_LR_EOI;
	}

	/* The GICv2 LR only holds five bits of priority. */
	val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
}

void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
}

void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
	vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
		GICH_VMCR_ALIAS_BINPOINT_MASK;
	vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
		GICH_VMCR_BINPOINT_MASK;
	vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
		GICH_VMCR_PRIMASK_MASK;

	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
}

void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;

	vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
			GICH_VMCR_CTRL_SHIFT;
	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
			GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
			GICH_VMCR_BINPOINT_SHIFT;
	vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
			GICH_VMCR_PRIMASK_SHIFT;
}

void vgic_v2_enable(struct kvm_vcpu *vcpu)
{
	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;

	/* Get the show on the road... */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
}

/* check for overlapping regions and for regions crossing the end of memory */
static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
{
	if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
		return false;
	if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
		return false;

	if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
		return true;
	if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
		return true;

	return false;
}

int vgic_v2_map_resources(struct kvm *kvm)
{
	struct vgic_dist *dist = &kvm->arch.vgic;
	int ret = 0;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
		kvm_err("Need to set vgic cpu and dist addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
		kvm_err("VGIC CPU and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * Initialize the vgic if this hasn't already been done on demand by
	 * accessing the vgic state from userspace.
	 */
	ret = vgic_init(kvm);
	if (ret) {
		kvm_err("Unable to initialize VGIC dynamic data structures\n");
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
	if (ret) {
		kvm_err("Unable to register VGIC MMIO regions\n");
		goto out;
	}

	ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
				    kvm_vgic_global_state.vcpu_base,
				    KVM_VGIC_V2_CPU_SIZE, true);
	if (ret) {
		kvm_err("Unable to remap VGIC CPU to VCPU\n");
		goto out;
	}

	dist->ready = true;

out:
	if (ret)
		kvm_vgic_destroy(kvm);
	return ret;
}

/**
 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv2 has been found, returns an error code otherwise
 */
int vgic_v2_probe(const struct gic_kvm_info *info)
{
	int ret;
	u32 vtr;

	if (!info->vctrl.start) {
		kvm_err("GICH not present in the firmware table\n");
		return -ENXIO;
	}

	if (!PAGE_ALIGNED(info->vcpu.start)) {
		kvm_err("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)info->vcpu.start);
		return -ENXIO;
	}

	if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
		kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&info->vcpu),
			PAGE_SIZE);
		return -ENXIO;
	}

	kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
						   resource_size(&info->vctrl));
	if (!kvm_vgic_global_state.vctrl_base) {
		kvm_err("Cannot ioremap GICH\n");
		return -ENOMEM;
	}

	vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
	kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;

	ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
				     kvm_vgic_global_state.vctrl_base +
					 resource_size(&info->vctrl),
				     info->vctrl.start);

	if (ret) {
		kvm_err("Cannot map VCTRL into hyp\n");
		iounmap(kvm_vgic_global_state.vctrl_base);
		return ret;
	}

	kvm_vgic_global_state.can_emulate_gicv2 = true;
	kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);

	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	kvm_vgic_global_state.type = VGIC_V2;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;

	kvm_info("vgic-v2@%llx\n", info->vctrl.start);

	return 0;
}
Commit	Line	Data
140b086d MZ	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/irqchip/arm-gic.h>
	18	#include <linux/kvm.h>
	19	#include <linux/kvm_host.h>
90977732 EA	20	#include <kvm/arm_vgic.h>
90977732 EA	21	#include <asm/kvm_mmu.h>
140b086d MZ	22
	23	#include "vgic.h"
	24
	25	/*
	26	* Call this function to convert a u64 value to an unsigned long * bitmask
	27	* in a way that works on both 32-bit and 64-bit LE and BE platforms.
	28	*
	29	* Warning: Calling this function may modify *val.
	30	*/
	31	static unsigned long u64_to_bitmask(u64 val)
	32	{
	33	#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
	34	val = (val >> 32) \| (*val << 32);
	35	#endif
	36	return (unsigned long *)val;
	37	}
	38
	39	void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
	40	{
	41	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
	42
	43	if (cpuif->vgic_misr & GICH_MISR_EOI) {
	44	u64 eisr = cpuif->vgic_eisr;
	45	unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
	46	int lr;
	47
	48	for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
	49	u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
	50
	51	WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
	52
	53	kvm_notify_acked_irq(vcpu->kvm, 0,
	54	intid - VGIC_NR_PRIVATE_IRQS);
	55	}
	56	}
	57
	58	/* check and disable underflow maintenance IRQ */
	59	cpuif->vgic_hcr &= ~GICH_HCR_UIE;
	60
	61	/*
	62	* In the next iterations of the vcpu loop, if we sync the
	63	* vgic state after flushing it, but before entering the guest
	64	* (this happens for pending signals and vmid rollovers), then
	65	* make sure we don't pick up any old maintenance interrupts
	66	* here.
	67	*/
	68	cpuif->vgic_eisr = 0;
	69	}
	70
	71	void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
	72	{
	73	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
	74
	75	cpuif->vgic_hcr \|= GICH_HCR_UIE;
	76	}
	77
	78	/*
	79	* transfer the content of the LRs back into the corresponding ap_list:
	80	* - active bit is transferred as is
	81	* - pending bit is
	82	* - transferred as is in case of edge sensitive IRQs
	83	* - set to the line-level (resample time) for level sensitive IRQs
	84	*/
	85	void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
86	{
87	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
88	int lr;
89
90	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
91	u32 val = cpuif->vgic_lr[lr];
92	u32 intid = val & GICH_LR_VIRTUALID;
93	struct vgic_irq *irq;
94
95	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
96
97	spin_lock(&irq->irq_lock);
98
99	/* Always preserve the active bit */
100	irq->active = !!(val & GICH_LR_ACTIVE_BIT);
101
102	/* Edge is the only case where we preserve the pending bit */
103	if (irq->config == VGIC_CONFIG_EDGE &&
104	(val & GICH_LR_PENDING_BIT)) {
105	irq->pending = true;
106
107	if (vgic_irq_is_sgi(intid)) {
108	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
109
110	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
111	irq->source \|= (1 << cpuid);
112	}
113	}
114
df7942d1 MZ	115	/*
	116	* Clear soft pending state when level irqs have been acked.
	117	* Always regenerate the pending state.
	118	*/
	119	if (irq->config == VGIC_CONFIG_LEVEL) {
	120	if (!(val & GICH_LR_PENDING_BIT))
	121	irq->soft_pending = false;
	122
	123	irq->pending = irq->line_level \|\| irq->soft_pending;
140b086d MZ	124	}
	125
	126	spin_unlock(&irq->irq_lock);
	127	}
	128	}
	129
	130	/*
	131	* Populates the particular LR with the state of a given IRQ:
	132	* - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
	133	* - for a level sensitive IRQ the pending state value is unchanged;
	134	* it is dictated directly by the input level
	135	*
	136	* If @irq describes an SGI with multiple sources, we choose the
	137	* lowest-numbered source VCPU and clear that bit in the source bitmap.
	138	*
	139	* The irq_lock must be held by the caller.
	140	*/
	141	void vgic_v2_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	142	{
	143	u32 val = irq->intid;
	144
	145	if (irq->pending) {
	146	val \|= GICH_LR_PENDING_BIT;
	147
	148	if (irq->config == VGIC_CONFIG_EDGE)
	149	irq->pending = false;
	150
	151	if (vgic_irq_is_sgi(irq->intid)) {
	152	u32 src = ffs(irq->source);
	153
	154	BUG_ON(!src);
	155	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	156	irq->source &= ~(1 << (src - 1));
	157	if (irq->source)
	158	irq->pending = true;
	159	}
	160	}
	161
	162	if (irq->active)
	163	val \|= GICH_LR_ACTIVE_BIT;
	164
	165	if (irq->hw) {
	166	val \|= GICH_LR_HW;
	167	val \|= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
	168	} else {
	169	if (irq->config == VGIC_CONFIG_LEVEL)
	170	val \|= GICH_LR_EOI;
	171	}
	172
	173	/* The GICv2 LR only holds five bits of priority. */
	174	val \|= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
	175
	176	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
	177	}
	178
	179	void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
	180	{
	181	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
	182	}
e4823a7a AP	183
	184	void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	185	{
	186	u32 vmcr;
	187
	188	vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
	189	vmcr \|= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
	190	GICH_VMCR_ALIAS_BINPOINT_MASK;
	191	vmcr \|= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
	192	GICH_VMCR_BINPOINT_MASK;
	193	vmcr \|= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
	194	GICH_VMCR_PRIMASK_MASK;
	195
	196	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
	197	}
	198
	199	void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	200	{
	201	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
	202
	203	vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
	204	GICH_VMCR_CTRL_SHIFT;
	205	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
	206	GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	207	vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
	208	GICH_VMCR_BINPOINT_SHIFT;
	209	vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
	210	GICH_VMCR_PRIMASK_SHIFT;
	211	}
90977732	212
ad275b8b EA	213	void vgic_v2_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	214	{
f7b6985c EA	215	/*
	216	* By forcing VMCR to zero, the GIC will restore the binary
	217	* points to their reset values. Anything else resets to zero
	218	* anyway.
	219	*/
	220	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
	221	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
	222
	223	/* Get the show on the road... */
	224	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
ad275b8b EA	225	}
ad275b8b EA	226
b0442ee2 EA	227	/* check for overlapping regions and for regions crossing the end of memory */
	228	static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
	229	{
	230	if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
	231	return false;
	232	if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
	233	return false;
	234
	235	if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
	236	return true;
	237	if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
	238	return true;
	239
	240	return false;
	241	}
	242
	243	int vgic_v2_map_resources(struct kvm *kvm)
	244	{
	245	struct vgic_dist *dist = &kvm->arch.vgic;
	246	int ret = 0;
	247
	248	if (vgic_ready(kvm))
	249	goto out;
	250
	251	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	252	IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
	253	kvm_err("Need to set vgic cpu and dist addresses first\n");
	254	ret = -ENXIO;
	255	goto out;
	256	}
	257
	258	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
	259	kvm_err("VGIC CPU and dist frames overlap\n");
	260	ret = -EINVAL;
	261	goto out;
	262	}
	263
	264	/*
	265	* Initialize the vgic if this hasn't already been done on demand by
	266	* accessing the vgic state from userspace.
	267	*/
	268	ret = vgic_init(kvm);
	269	if (ret) {
	270	kvm_err("Unable to initialize VGIC dynamic data structures\n");
	271	goto out;
	272	}
	273
	274	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
	275	if (ret) {
	276	kvm_err("Unable to register VGIC MMIO regions\n");
	277	goto out;
	278	}
	279
	280	ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
	281	kvm_vgic_global_state.vcpu_base,
	282	KVM_VGIC_V2_CPU_SIZE, true);
	283	if (ret) {
	284	kvm_err("Unable to remap VGIC CPU to VCPU\n");
	285	goto out;
	286	}
	287
	288	dist->ready = true;
	289
	290	out:
291	if (ret)
292	kvm_vgic_destroy(kvm);
293	return ret;
294	}
295
90977732 EA	296	/**
	297	* vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
	298	* @node: pointer to the DT node
	299	*
	300	* Returns 0 if a GICv2 has been found, returns an error code otherwise
	301	*/
	302	int vgic_v2_probe(const struct gic_kvm_info *info)
	303	{
	304	int ret;
	305	u32 vtr;
	306
	307	if (!info->vctrl.start) {
	308	kvm_err("GICH not present in the firmware table\n");
	309	return -ENXIO;
	310	}
	311
	312	if (!PAGE_ALIGNED(info->vcpu.start)) {
	313	kvm_err("GICV physical address 0x%llx not page aligned\n",
	314	(unsigned long long)info->vcpu.start);
	315	return -ENXIO;
	316	}
	317
	318	if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	319	kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
	320	(unsigned long long)resource_size(&info->vcpu),
	321	PAGE_SIZE);
	322	return -ENXIO;
	323	}
	324
	325	kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
	326	resource_size(&info->vctrl));
	327	if (!kvm_vgic_global_state.vctrl_base) {
	328	kvm_err("Cannot ioremap GICH\n");
	329	return -ENOMEM;
	330	}
	331
	332	vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
	333	kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
	334
	335	ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
	336	kvm_vgic_global_state.vctrl_base +
	337	resource_size(&info->vctrl),
	338	info->vctrl.start);
	339
	340	if (ret) {
	341	kvm_err("Cannot map VCTRL into hyp\n");
	342	iounmap(kvm_vgic_global_state.vctrl_base);
	343	return ret;
	344	}
	345
	346	kvm_vgic_global_state.can_emulate_gicv2 = true;
	347	kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	348
	349	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	350	kvm_vgic_global_state.type = VGIC_V2;
	351	kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
	352
	353	kvm_info("vgic-v2@%llx\n", info->vctrl.start);
	354
	355	return 0;
	356	}