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Commit | Line | Data |
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59529f69 MZ |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
13 | */ | |
14 | ||
15 | #include <linux/irqchip/arm-gic-v3.h> | |
16 | #include <linux/kvm.h> | |
17 | #include <linux/kvm_host.h> | |
90977732 EA |
18 | #include <kvm/arm_vgic.h> |
19 | #include <asm/kvm_mmu.h> | |
20 | #include <asm/kvm_asm.h> | |
59529f69 MZ |
21 | |
22 | #include "vgic.h" | |
23 | ||
abf55766 | 24 | static bool group0_trap; |
9c7bfc28 | 25 | static bool group1_trap; |
ff89511e | 26 | static bool common_trap; |
9c7bfc28 | 27 | |
af061499 | 28 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) |
59529f69 MZ |
29 | { |
30 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
59529f69 | 31 | |
af061499 | 32 | cpuif->vgic_hcr |= ICH_HCR_UIE; |
59529f69 MZ |
33 | } |
34 | ||
af061499 | 35 | static bool lr_signals_eoi_mi(u64 lr_val) |
59529f69 | 36 | { |
af061499 CD |
37 | return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) && |
38 | !(lr_val & ICH_LR_HW); | |
59529f69 MZ |
39 | } |
40 | ||
41 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) | |
42 | { | |
8ac76ef4 CD |
43 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
44 | struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; | |
59529f69 MZ |
45 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
46 | int lr; | |
47 | ||
af061499 CD |
48 | cpuif->vgic_hcr &= ~ICH_HCR_UIE; |
49 | ||
8ac76ef4 | 50 | for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { |
59529f69 MZ |
51 | u64 val = cpuif->vgic_lr[lr]; |
52 | u32 intid; | |
53 | struct vgic_irq *irq; | |
54 | ||
55 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
56 | intid = val & ICH_LR_VIRTUAL_ID_MASK; | |
57 | else | |
58 | intid = val & GICH_LR_VIRTUALID; | |
af061499 CD |
59 | |
60 | /* Notify fds when the guest EOI'ed a level-triggered IRQ */ | |
61 | if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) | |
62 | kvm_notify_acked_irq(vcpu->kvm, 0, | |
63 | intid - VGIC_NR_PRIVATE_IRQS); | |
64 | ||
59529f69 | 65 | irq = vgic_get_irq(vcpu->kvm, vcpu, intid); |
3802411d AP |
66 | if (!irq) /* An LPI could have been unmapped. */ |
67 | continue; | |
59529f69 MZ |
68 | |
69 | spin_lock(&irq->irq_lock); | |
70 | ||
71 | /* Always preserve the active bit */ | |
72 | irq->active = !!(val & ICH_LR_ACTIVE_BIT); | |
73 | ||
74 | /* Edge is the only case where we preserve the pending bit */ | |
75 | if (irq->config == VGIC_CONFIG_EDGE && | |
76 | (val & ICH_LR_PENDING_BIT)) { | |
8694e4da | 77 | irq->pending_latch = true; |
59529f69 MZ |
78 | |
79 | if (vgic_irq_is_sgi(intid) && | |
80 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
81 | u32 cpuid = val & GICH_LR_PHYSID_CPUID; | |
82 | ||
83 | cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | |
84 | irq->source |= (1 << cpuid); | |
85 | } | |
86 | } | |
87 | ||
637d122b MZ |
88 | /* |
89 | * Clear soft pending state when level irqs have been acked. | |
90 | * Always regenerate the pending state. | |
91 | */ | |
92 | if (irq->config == VGIC_CONFIG_LEVEL) { | |
93 | if (!(val & ICH_LR_PENDING_BIT)) | |
8694e4da | 94 | irq->pending_latch = false; |
59529f69 MZ |
95 | } |
96 | ||
97 | spin_unlock(&irq->irq_lock); | |
5dd4b924 | 98 | vgic_put_irq(vcpu->kvm, irq); |
59529f69 | 99 | } |
8ac76ef4 CD |
100 | |
101 | vgic_cpu->used_lrs = 0; | |
59529f69 MZ |
102 | } |
103 | ||
104 | /* Requires the irq to be locked already */ | |
105 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | |
106 | { | |
107 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
108 | u64 val = irq->intid; | |
109 | ||
8694e4da | 110 | if (irq_is_pending(irq)) { |
59529f69 MZ |
111 | val |= ICH_LR_PENDING_BIT; |
112 | ||
113 | if (irq->config == VGIC_CONFIG_EDGE) | |
8694e4da | 114 | irq->pending_latch = false; |
59529f69 MZ |
115 | |
116 | if (vgic_irq_is_sgi(irq->intid) && | |
117 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
118 | u32 src = ffs(irq->source); | |
119 | ||
120 | BUG_ON(!src); | |
121 | val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | |
122 | irq->source &= ~(1 << (src - 1)); | |
123 | if (irq->source) | |
8694e4da | 124 | irq->pending_latch = true; |
59529f69 MZ |
125 | } |
126 | } | |
127 | ||
128 | if (irq->active) | |
129 | val |= ICH_LR_ACTIVE_BIT; | |
130 | ||
131 | if (irq->hw) { | |
132 | val |= ICH_LR_HW; | |
133 | val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; | |
3d6e77ad MZ |
134 | /* |
135 | * Never set pending+active on a HW interrupt, as the | |
136 | * pending state is kept at the physical distributor | |
137 | * level. | |
138 | */ | |
139 | if (irq->active && irq_is_pending(irq)) | |
140 | val &= ~ICH_LR_PENDING_BIT; | |
59529f69 MZ |
141 | } else { |
142 | if (irq->config == VGIC_CONFIG_LEVEL) | |
143 | val |= ICH_LR_EOI; | |
144 | } | |
145 | ||
146 | /* | |
147 | * We currently only support Group1 interrupts, which is a | |
148 | * known defect. This needs to be addressed at some point. | |
149 | */ | |
150 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
151 | val |= ICH_LR_GROUP; | |
152 | ||
153 | val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; | |
154 | ||
155 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; | |
156 | } | |
157 | ||
158 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) | |
159 | { | |
160 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; | |
161 | } | |
e4823a7a AP |
162 | |
163 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
164 | { | |
328e5664 | 165 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 166 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
e4823a7a AP |
167 | u32 vmcr; |
168 | ||
28232a43 CD |
169 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
170 | vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & | |
171 | ICH_VMCR_ACK_CTL_MASK; | |
172 | vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & | |
173 | ICH_VMCR_FIQ_EN_MASK; | |
174 | } else { | |
175 | /* | |
176 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
177 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
178 | */ | |
179 | vmcr = ICH_VMCR_FIQ_EN_MASK; | |
180 | } | |
181 | ||
182 | vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; | |
183 | vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; | |
e4823a7a AP |
184 | vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; |
185 | vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; | |
186 | vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; | |
5fb247d7 VK |
187 | vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; |
188 | vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; | |
e4823a7a | 189 | |
328e5664 | 190 | cpu_if->vgic_vmcr = vmcr; |
e4823a7a AP |
191 | } |
192 | ||
193 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
194 | { | |
328e5664 | 195 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 196 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
328e5664 CD |
197 | u32 vmcr; |
198 | ||
199 | vmcr = cpu_if->vgic_vmcr; | |
e4823a7a | 200 | |
28232a43 CD |
201 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
202 | vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> | |
203 | ICH_VMCR_ACK_CTL_SHIFT; | |
204 | vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> | |
205 | ICH_VMCR_FIQ_EN_SHIFT; | |
206 | } else { | |
207 | /* | |
208 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
209 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
210 | */ | |
211 | vmcrp->fiqen = 1; | |
212 | vmcrp->ackctl = 0; | |
213 | } | |
214 | ||
215 | vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; | |
216 | vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; | |
e4823a7a AP |
217 | vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; |
218 | vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; | |
219 | vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; | |
5fb247d7 VK |
220 | vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; |
221 | vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; | |
e4823a7a | 222 | } |
90977732 | 223 | |
0aa1de57 AP |
224 | #define INITIAL_PENDBASER_VALUE \ |
225 | (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ | |
226 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ | |
227 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) | |
228 | ||
ad275b8b EA |
229 | void vgic_v3_enable(struct kvm_vcpu *vcpu) |
230 | { | |
f7b6985c EA |
231 | struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; |
232 | ||
233 | /* | |
234 | * By forcing VMCR to zero, the GIC will restore the binary | |
235 | * points to their reset values. Anything else resets to zero | |
236 | * anyway. | |
237 | */ | |
238 | vgic_v3->vgic_vmcr = 0; | |
239 | vgic_v3->vgic_elrsr = ~0; | |
240 | ||
241 | /* | |
242 | * If we are emulating a GICv3, we do it in an non-GICv2-compatible | |
243 | * way, so we force SRE to 1 to demonstrate this to the guest. | |
4dfc0505 | 244 | * Also, we don't support any form of IRQ/FIQ bypass. |
f7b6985c EA |
245 | * This goes with the spec allowing the value to be RAO/WI. |
246 | */ | |
0aa1de57 | 247 | if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { |
4dfc0505 MZ |
248 | vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | |
249 | ICC_SRE_EL1_DFB | | |
250 | ICC_SRE_EL1_SRE); | |
0aa1de57 AP |
251 | vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; |
252 | } else { | |
f7b6985c | 253 | vgic_v3->vgic_sre = 0; |
0aa1de57 | 254 | } |
f7b6985c | 255 | |
d017d7b0 VK |
256 | vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 & |
257 | ICH_VTR_ID_BITS_MASK) >> | |
258 | ICH_VTR_ID_BITS_SHIFT; | |
259 | vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 & | |
260 | ICH_VTR_PRI_BITS_MASK) >> | |
261 | ICH_VTR_PRI_BITS_SHIFT) + 1; | |
262 | ||
f7b6985c EA |
263 | /* Get the show on the road... */ |
264 | vgic_v3->vgic_hcr = ICH_HCR_EN; | |
abf55766 MZ |
265 | if (group0_trap) |
266 | vgic_v3->vgic_hcr |= ICH_HCR_TALL0; | |
9c7bfc28 MZ |
267 | if (group1_trap) |
268 | vgic_v3->vgic_hcr |= ICH_HCR_TALL1; | |
ff89511e MZ |
269 | if (common_trap) |
270 | vgic_v3->vgic_hcr |= ICH_HCR_TC; | |
ad275b8b EA |
271 | } |
272 | ||
44de9d68 EA |
273 | int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq) |
274 | { | |
275 | struct kvm_vcpu *vcpu; | |
276 | int byte_offset, bit_nr; | |
277 | gpa_t pendbase, ptr; | |
278 | bool status; | |
279 | u8 val; | |
280 | int ret; | |
281 | ||
282 | retry: | |
283 | vcpu = irq->target_vcpu; | |
284 | if (!vcpu) | |
285 | return 0; | |
286 | ||
287 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
288 | ||
289 | byte_offset = irq->intid / BITS_PER_BYTE; | |
290 | bit_nr = irq->intid % BITS_PER_BYTE; | |
291 | ptr = pendbase + byte_offset; | |
292 | ||
293 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
294 | if (ret) | |
295 | return ret; | |
296 | ||
297 | status = val & (1 << bit_nr); | |
298 | ||
299 | spin_lock(&irq->irq_lock); | |
300 | if (irq->target_vcpu != vcpu) { | |
301 | spin_unlock(&irq->irq_lock); | |
302 | goto retry; | |
303 | } | |
304 | irq->pending_latch = status; | |
305 | vgic_queue_irq_unlock(vcpu->kvm, irq); | |
306 | ||
307 | if (status) { | |
308 | /* clear consumed data */ | |
309 | val &= ~(1 << bit_nr); | |
310 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
311 | if (ret) | |
312 | return ret; | |
313 | } | |
314 | return 0; | |
315 | } | |
316 | ||
28077125 EA |
317 | /** |
318 | * vgic_its_save_pending_tables - Save the pending tables into guest RAM | |
319 | * kvm lock and all vcpu lock must be held | |
320 | */ | |
321 | int vgic_v3_save_pending_tables(struct kvm *kvm) | |
322 | { | |
323 | struct vgic_dist *dist = &kvm->arch.vgic; | |
324 | int last_byte_offset = -1; | |
325 | struct vgic_irq *irq; | |
326 | int ret; | |
327 | ||
328 | list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { | |
329 | int byte_offset, bit_nr; | |
330 | struct kvm_vcpu *vcpu; | |
331 | gpa_t pendbase, ptr; | |
332 | bool stored; | |
333 | u8 val; | |
334 | ||
335 | vcpu = irq->target_vcpu; | |
336 | if (!vcpu) | |
337 | continue; | |
338 | ||
339 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
340 | ||
341 | byte_offset = irq->intid / BITS_PER_BYTE; | |
342 | bit_nr = irq->intid % BITS_PER_BYTE; | |
343 | ptr = pendbase + byte_offset; | |
344 | ||
345 | if (byte_offset != last_byte_offset) { | |
346 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
347 | if (ret) | |
348 | return ret; | |
349 | last_byte_offset = byte_offset; | |
350 | } | |
351 | ||
352 | stored = val & (1U << bit_nr); | |
353 | if (stored == irq->pending_latch) | |
354 | continue; | |
355 | ||
356 | if (irq->pending_latch) | |
357 | val |= 1 << bit_nr; | |
358 | else | |
359 | val &= ~(1 << bit_nr); | |
360 | ||
361 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
362 | if (ret) | |
363 | return ret; | |
364 | } | |
365 | return 0; | |
366 | } | |
367 | ||
9a746d75 CD |
368 | /* |
369 | * Check for overlapping regions and for regions crossing the end of memory | |
370 | * for base addresses which have already been set. | |
371 | */ | |
372 | bool vgic_v3_check_base(struct kvm *kvm) | |
b0442ee2 EA |
373 | { |
374 | struct vgic_dist *d = &kvm->arch.vgic; | |
375 | gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE; | |
376 | ||
377 | redist_size *= atomic_read(&kvm->online_vcpus); | |
378 | ||
9a746d75 CD |
379 | if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && |
380 | d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base) | |
b0442ee2 | 381 | return false; |
9a746d75 CD |
382 | |
383 | if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) && | |
384 | d->vgic_redist_base + redist_size < d->vgic_redist_base) | |
b0442ee2 EA |
385 | return false; |
386 | ||
9a746d75 CD |
387 | /* Both base addresses must be set to check if they overlap */ |
388 | if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) || | |
389 | IS_VGIC_ADDR_UNDEF(d->vgic_redist_base)) | |
390 | return true; | |
391 | ||
b0442ee2 EA |
392 | if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base) |
393 | return true; | |
394 | if (d->vgic_redist_base + redist_size <= d->vgic_dist_base) | |
395 | return true; | |
396 | ||
397 | return false; | |
398 | } | |
399 | ||
400 | int vgic_v3_map_resources(struct kvm *kvm) | |
401 | { | |
402 | int ret = 0; | |
403 | struct vgic_dist *dist = &kvm->arch.vgic; | |
404 | ||
405 | if (vgic_ready(kvm)) | |
406 | goto out; | |
407 | ||
408 | if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) || | |
409 | IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) { | |
410 | kvm_err("Need to set vgic distributor addresses first\n"); | |
411 | ret = -ENXIO; | |
412 | goto out; | |
413 | } | |
414 | ||
415 | if (!vgic_v3_check_base(kvm)) { | |
416 | kvm_err("VGIC redist and dist frames overlap\n"); | |
417 | ret = -EINVAL; | |
418 | goto out; | |
419 | } | |
420 | ||
421 | /* | |
422 | * For a VGICv3 we require the userland to explicitly initialize | |
423 | * the VGIC before we need to use it. | |
424 | */ | |
425 | if (!vgic_initialized(kvm)) { | |
426 | ret = -EBUSY; | |
427 | goto out; | |
428 | } | |
429 | ||
430 | ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3); | |
431 | if (ret) { | |
432 | kvm_err("Unable to register VGICv3 dist MMIO regions\n"); | |
433 | goto out; | |
434 | } | |
435 | ||
b0442ee2 EA |
436 | dist->ready = true; |
437 | ||
438 | out: | |
b0442ee2 EA |
439 | return ret; |
440 | } | |
441 | ||
59da1cbf MZ |
442 | DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap); |
443 | ||
e23f62f7 MZ |
444 | static int __init early_group0_trap_cfg(char *buf) |
445 | { | |
446 | return strtobool(buf, &group0_trap); | |
447 | } | |
448 | early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg); | |
449 | ||
182936ee MZ |
450 | static int __init early_group1_trap_cfg(char *buf) |
451 | { | |
452 | return strtobool(buf, &group1_trap); | |
453 | } | |
454 | early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg); | |
455 | ||
ff89511e MZ |
456 | static int __init early_common_trap_cfg(char *buf) |
457 | { | |
458 | return strtobool(buf, &common_trap); | |
459 | } | |
460 | early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg); | |
461 | ||
90977732 EA |
462 | /** |
463 | * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT | |
464 | * @node: pointer to the DT node | |
465 | * | |
466 | * Returns 0 if a GICv3 has been found, returns an error code otherwise | |
467 | */ | |
468 | int vgic_v3_probe(const struct gic_kvm_info *info) | |
469 | { | |
470 | u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2); | |
42c8870f | 471 | int ret; |
90977732 EA |
472 | |
473 | /* | |
474 | * The ListRegs field is 5 bits, but there is a architectural | |
475 | * maximum of 16 list registers. Just ignore bit 4... | |
476 | */ | |
477 | kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; | |
478 | kvm_vgic_global_state.can_emulate_gicv2 = false; | |
d017d7b0 | 479 | kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2; |
90977732 EA |
480 | |
481 | if (!info->vcpu.start) { | |
482 | kvm_info("GICv3: no GICV resource entry\n"); | |
483 | kvm_vgic_global_state.vcpu_base = 0; | |
484 | } else if (!PAGE_ALIGNED(info->vcpu.start)) { | |
485 | pr_warn("GICV physical address 0x%llx not page aligned\n", | |
486 | (unsigned long long)info->vcpu.start); | |
487 | kvm_vgic_global_state.vcpu_base = 0; | |
488 | } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) { | |
489 | pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n", | |
490 | (unsigned long long)resource_size(&info->vcpu), | |
491 | PAGE_SIZE); | |
492 | kvm_vgic_global_state.vcpu_base = 0; | |
493 | } else { | |
494 | kvm_vgic_global_state.vcpu_base = info->vcpu.start; | |
495 | kvm_vgic_global_state.can_emulate_gicv2 = true; | |
42c8870f AP |
496 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); |
497 | if (ret) { | |
498 | kvm_err("Cannot register GICv2 KVM device.\n"); | |
499 | return ret; | |
500 | } | |
90977732 EA |
501 | kvm_info("vgic-v2@%llx\n", info->vcpu.start); |
502 | } | |
42c8870f AP |
503 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); |
504 | if (ret) { | |
505 | kvm_err("Cannot register GICv3 KVM device.\n"); | |
506 | kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2); | |
507 | return ret; | |
508 | } | |
509 | ||
90977732 EA |
510 | if (kvm_vgic_global_state.vcpu_base == 0) |
511 | kvm_info("disabling GICv2 emulation\n"); | |
90977732 | 512 | |
690a3415 DD |
513 | #ifdef CONFIG_ARM64 |
514 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) { | |
515 | group0_trap = true; | |
516 | group1_trap = true; | |
517 | } | |
518 | #endif | |
519 | ||
ff89511e | 520 | if (group0_trap || group1_trap || common_trap) { |
2873b508 MZ |
521 | kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n", |
522 | group0_trap ? "G0" : "", | |
523 | group1_trap ? "G1" : "", | |
524 | common_trap ? "C" : ""); | |
182936ee MZ |
525 | static_branch_enable(&vgic_v3_cpuif_trap); |
526 | } | |
527 | ||
90977732 EA |
528 | kvm_vgic_global_state.vctrl_base = NULL; |
529 | kvm_vgic_global_state.type = VGIC_V3; | |
530 | kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; | |
531 | ||
532 | return 0; | |
533 | } | |
328e5664 CD |
534 | |
535 | void vgic_v3_load(struct kvm_vcpu *vcpu) | |
536 | { | |
537 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
538 | ||
ff567614 MZ |
539 | /* |
540 | * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen | |
541 | * is dependent on ICC_SRE_EL1.SRE, and we have to perform the | |
542 | * VMCR_EL2 save/restore in the world switch. | |
543 | */ | |
544 | if (likely(cpu_if->vgic_sre)) | |
545 | kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr); | |
328e5664 CD |
546 | } |
547 | ||
548 | void vgic_v3_put(struct kvm_vcpu *vcpu) | |
549 | { | |
550 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
551 | ||
ff567614 MZ |
552 | if (likely(cpu_if->vgic_sre)) |
553 | cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr); | |
328e5664 | 554 | } |