[mirror_ubuntu-bionic-kernel.git] / virt / kvm / arm / vgic / vgic-v3.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_asm.h>

#include "vgic.h"

void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;

	if (cpuif->vgic_misr & ICH_MISR_EOI) {
		unsigned long eisr_bmap = cpuif->vgic_eisr;
		int lr;

		for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
			u32 intid;
			u64 val = cpuif->vgic_lr[lr];

			if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
				intid = val & ICH_LR_VIRTUAL_ID_MASK;
			else
				intid = val & GICH_LR_VIRTUALID;

			WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);

			kvm_notify_acked_irq(vcpu->kvm, 0,
					     intid - VGIC_NR_PRIVATE_IRQS);
		}

		/*
		 * In the next iterations of the vcpu loop, if we sync
		 * the vgic state after flushing it, but before
		 * entering the guest (this happens for pending
		 * signals and vmid rollovers), then make sure we
		 * don't pick up any old maintenance interrupts here.
		 */
		cpuif->vgic_eisr = 0;
	}

	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
}

void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;

	cpuif->vgic_hcr |= ICH_HCR_UIE;
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	int lr;

	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
		u64 val = cpuif->vgic_lr[lr];
		u32 intid;
		struct vgic_irq *irq;

		if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
			intid = val & ICH_LR_VIRTUAL_ID_MASK;
		else
			intid = val & GICH_LR_VIRTUALID;
		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);

		spin_lock(&irq->irq_lock);

		/* Always preserve the active bit */
		irq->active = !!(val & ICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & ICH_LR_PENDING_BIT)) {
			irq->pending = true;

			if (vgic_irq_is_sgi(intid) &&
			    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & ICH_LR_PENDING_BIT))
				irq->soft_pending = false;

			irq->pending = irq->line_level || irq->soft_pending;
		}

		spin_unlock(&irq->irq_lock);
	}
}

/* Requires the irq to be locked already */
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u64 val = irq->intid;

	if (irq->pending) {
		val |= ICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending = false;

		if (vgic_irq_is_sgi(irq->intid) &&
		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending = true;
		}
	}

	if (irq->active)
		val |= ICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= ICH_LR_HW;
		val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= ICH_LR_EOI;
	}

	/*
	 * We currently only support Group1 interrupts, which is a
	 * known defect. This needs to be addressed at some point.
	 */
	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
		val |= ICH_LR_GROUP;

	val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
}

void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}

void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
}

void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;

	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
}

void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
		vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	else
		vgic_v3->vgic_sre = 0;

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
}

/* check for overlapping regions and for regions crossing the end of memory */
static bool vgic_v3_check_base(struct kvm *kvm)
{
	struct vgic_dist *d = &kvm->arch.vgic;
	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;

	redist_size *= atomic_read(&kvm->online_vcpus);

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
		return false;
	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
		return false;

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
		return true;
	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
		return true;

	return false;
}

int vgic_v3_map_resources(struct kvm *kvm)
{
	int ret = 0;
	struct vgic_dist *dist = &kvm->arch.vgic;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
		kvm_err("Need to set vgic distributor addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v3_check_base(kvm)) {
		kvm_err("VGIC redist and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * For a VGICv3 we require the userland to explicitly initialize
	 * the VGIC before we need to use it.
	 */
	if (!vgic_initialized(kvm)) {
		ret = -EBUSY;
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	if (ret) {
		kvm_err("Unable to register VGICv3 dist MMIO regions\n");
		goto out;
	}

	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	if (ret) {
		kvm_err("Unable to register VGICv3 redist MMIO regions\n");
		goto out;
	}

	dist->ready = true;

out:
	if (ret)
		kvm_vgic_destroy(kvm);
	return ret;
}

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv3 has been found, returns an error code otherwise
 */
int vgic_v3_probe(const struct gic_kvm_info *info)
{
	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	kvm_vgic_global_state.can_emulate_gicv2 = false;

	if (!info->vcpu.start) {
		kvm_info("GICv3: no GICV resource entry\n");
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)info->vcpu.start);
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&info->vcpu),
			PAGE_SIZE);
		kvm_vgic_global_state.vcpu_base = 0;
	} else {
		kvm_vgic_global_state.vcpu_base = info->vcpu.start;
		kvm_vgic_global_state.can_emulate_gicv2 = true;
		kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
		kvm_info("vgic-v2@%llx\n", info->vcpu.start);
	}
	if (kvm_vgic_global_state.vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");
	kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);

	kvm_vgic_global_state.vctrl_base = NULL;
	kvm_vgic_global_state.type = VGIC_V3;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;

	return 0;
}
Commit	Line	Data
59529f69 MZ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License version 2 as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	13	*/
	14
	15	#include <linux/irqchip/arm-gic-v3.h>
	16	#include <linux/kvm.h>
	17	#include <linux/kvm_host.h>
90977732 EA	18	#include <kvm/arm_vgic.h>
	19	#include <asm/kvm_mmu.h>
	20	#include <asm/kvm_asm.h>
59529f69 MZ	21
	22	#include "vgic.h"
	23
	24	void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
	25	{
	26	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	27	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	28
	29	if (cpuif->vgic_misr & ICH_MISR_EOI) {
	30	unsigned long eisr_bmap = cpuif->vgic_eisr;
	31	int lr;
	32
	33	for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
	34	u32 intid;
	35	u64 val = cpuif->vgic_lr[lr];
	36
	37	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	38	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	39	else
	40	intid = val & GICH_LR_VIRTUALID;
	41
	42	WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
	43
	44	kvm_notify_acked_irq(vcpu->kvm, 0,
	45	intid - VGIC_NR_PRIVATE_IRQS);
	46	}
	47
	48	/*
	49	* In the next iterations of the vcpu loop, if we sync
	50	* the vgic state after flushing it, but before
	51	* entering the guest (this happens for pending
	52	* signals and vmid rollovers), then make sure we
	53	* don't pick up any old maintenance interrupts here.
	54	*/
	55	cpuif->vgic_eisr = 0;
	56	}
	57
	58	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
	59	}
	60
	61	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
	62	{
	63	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	64
	65	cpuif->vgic_hcr \|= ICH_HCR_UIE;
	66	}
	67
	68	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
	69	{
	70	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	71	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	72	int lr;
	73
	74	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
	75	u64 val = cpuif->vgic_lr[lr];
	76	u32 intid;
	77	struct vgic_irq *irq;
	78
	79	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	80	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	81	else
	82	intid = val & GICH_LR_VIRTUALID;
	83	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
	84
85	spin_lock(&irq->irq_lock);
86
87	/* Always preserve the active bit */
88	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
89
90	/* Edge is the only case where we preserve the pending bit */
91	if (irq->config == VGIC_CONFIG_EDGE &&
92	(val & ICH_LR_PENDING_BIT)) {
93	irq->pending = true;
94
95	if (vgic_irq_is_sgi(intid) &&
96	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
97	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
98
99	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
100	irq->source \|= (1 << cpuid);
101	}
102	}
103
637d122b MZ	104	/*
	105	* Clear soft pending state when level irqs have been acked.
	106	* Always regenerate the pending state.
	107	*/
	108	if (irq->config == VGIC_CONFIG_LEVEL) {
	109	if (!(val & ICH_LR_PENDING_BIT))
	110	irq->soft_pending = false;
	111
	112	irq->pending = irq->line_level \|\| irq->soft_pending;
59529f69 MZ	113	}
	114
	115	spin_unlock(&irq->irq_lock);
	116	}
	117	}
	118
	119	/* Requires the irq to be locked already */
	120	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	121	{
	122	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	123	u64 val = irq->intid;
	124
	125	if (irq->pending) {
	126	val \|= ICH_LR_PENDING_BIT;
	127
	128	if (irq->config == VGIC_CONFIG_EDGE)
	129	irq->pending = false;
	130
	131	if (vgic_irq_is_sgi(irq->intid) &&
	132	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	133	u32 src = ffs(irq->source);
	134
	135	BUG_ON(!src);
	136	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	137	irq->source &= ~(1 << (src - 1));
	138	if (irq->source)
	139	irq->pending = true;
	140	}
	141	}
	142
	143	if (irq->active)
	144	val \|= ICH_LR_ACTIVE_BIT;
	145
	146	if (irq->hw) {
	147	val \|= ICH_LR_HW;
	148	val \|= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	149	} else {
	150	if (irq->config == VGIC_CONFIG_LEVEL)
	151	val \|= ICH_LR_EOI;
	152	}
	153
	154	/*
	155	* We currently only support Group1 interrupts, which is a
	156	* known defect. This needs to be addressed at some point.
	157	*/
	158	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	159	val \|= ICH_LR_GROUP;
	160
	161	val \|= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
	162
	163	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
	164	}
	165
	166	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
	167	{
	168	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
	169	}
e4823a7a AP	170
	171	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	172	{
	173	u32 vmcr;
	174
	175	vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	176	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	177	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	178	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	179
	180	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
	181	}
	182
	183	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	184	{
	185	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
	186
	187	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	188	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	189	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	190	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	191	}
90977732	192
ad275b8b EA	193	void vgic_v3_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	194	{
f7b6985c EA	195	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
	196
	197	/*
	198	* By forcing VMCR to zero, the GIC will restore the binary
	199	* points to their reset values. Anything else resets to zero
	200	* anyway.
	201	*/
	202	vgic_v3->vgic_vmcr = 0;
	203	vgic_v3->vgic_elrsr = ~0;
	204
	205	/*
	206	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	207	* way, so we force SRE to 1 to demonstrate this to the guest.
	208	* This goes with the spec allowing the value to be RAO/WI.
	209	*/
	210	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
	211	vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	212	else
	213	vgic_v3->vgic_sre = 0;
	214
	215	/* Get the show on the road... */
	216	vgic_v3->vgic_hcr = ICH_HCR_EN;
ad275b8b EA	217	}
ad275b8b EA	218
b0442ee2 EA	219	/* check for overlapping regions and for regions crossing the end of memory */
	220	static bool vgic_v3_check_base(struct kvm *kvm)
	221	{
	222	struct vgic_dist *d = &kvm->arch.vgic;
	223	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
	224
	225	redist_size *= atomic_read(&kvm->online_vcpus);
	226
	227	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
	228	return false;
	229	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
	230	return false;
	231
	232	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
	233	return true;
	234	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
	235	return true;
	236
	237	return false;
	238	}
	239
	240	int vgic_v3_map_resources(struct kvm *kvm)
	241	{
	242	int ret = 0;
	243	struct vgic_dist *dist = &kvm->arch.vgic;
	244
	245	if (vgic_ready(kvm))
	246	goto out;
	247
	248	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	249	IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
	250	kvm_err("Need to set vgic distributor addresses first\n");
	251	ret = -ENXIO;
	252	goto out;
	253	}
	254
	255	if (!vgic_v3_check_base(kvm)) {
	256	kvm_err("VGIC redist and dist frames overlap\n");
	257	ret = -EINVAL;
	258	goto out;
	259	}
	260
	261	/*
	262	* For a VGICv3 we require the userland to explicitly initialize
	263	* the VGIC before we need to use it.
	264	*/
	265	if (!vgic_initialized(kvm)) {
	266	ret = -EBUSY;
	267	goto out;
	268	}
	269
	270	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	271	if (ret) {
	272	kvm_err("Unable to register VGICv3 dist MMIO regions\n");
	273	goto out;
	274	}
	275
	276	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	277	if (ret) {
	278	kvm_err("Unable to register VGICv3 redist MMIO regions\n");
	279	goto out;
	280	}
	281
	282	dist->ready = true;
283
284	out:
285	if (ret)
286	kvm_vgic_destroy(kvm);
287	return ret;
288	}
289
90977732 EA	290	/**
	291	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
	292	* @node: pointer to the DT node
	293	*
	294	* Returns 0 if a GICv3 has been found, returns an error code otherwise
	295	*/
	296	int vgic_v3_probe(const struct gic_kvm_info *info)
	297	{
	298	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	299
	300	/*
	301	* The ListRegs field is 5 bits, but there is a architectural
	302	* maximum of 16 list registers. Just ignore bit 4...
	303	*/
	304	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	305	kvm_vgic_global_state.can_emulate_gicv2 = false;
	306
	307	if (!info->vcpu.start) {
	308	kvm_info("GICv3: no GICV resource entry\n");
	309	kvm_vgic_global_state.vcpu_base = 0;
	310	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
	311	pr_warn("GICV physical address 0x%llx not page aligned\n",
	312	(unsigned long long)info->vcpu.start);
	313	kvm_vgic_global_state.vcpu_base = 0;
	314	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	315	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
	316	(unsigned long long)resource_size(&info->vcpu),
	317	PAGE_SIZE);
	318	kvm_vgic_global_state.vcpu_base = 0;
	319	} else {
	320	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	321	kvm_vgic_global_state.can_emulate_gicv2 = true;
	322	kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	323	kvm_info("vgic-v2@%llx\n", info->vcpu.start);
	324	}
	325	if (kvm_vgic_global_state.vcpu_base == 0)
	326	kvm_info("disabling GICv2 emulation\n");
	327	kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	328
	329	kvm_vgic_global_state.vctrl_base = NULL;
	330	kvm_vgic_global_state.type = VGIC_V3;
	331	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
	332
	333	return 0;
	334	}