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59529f69 MZ |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
13 | */ | |
14 | ||
15 | #include <linux/irqchip/arm-gic-v3.h> | |
16 | #include <linux/kvm.h> | |
17 | #include <linux/kvm_host.h> | |
90977732 EA |
18 | #include <kvm/arm_vgic.h> |
19 | #include <asm/kvm_mmu.h> | |
20 | #include <asm/kvm_asm.h> | |
59529f69 MZ |
21 | |
22 | #include "vgic.h" | |
23 | ||
24 | void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu) | |
25 | { | |
26 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
27 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
28 | ||
29 | if (cpuif->vgic_misr & ICH_MISR_EOI) { | |
30 | unsigned long eisr_bmap = cpuif->vgic_eisr; | |
31 | int lr; | |
32 | ||
33 | for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) { | |
34 | u32 intid; | |
35 | u64 val = cpuif->vgic_lr[lr]; | |
36 | ||
37 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
38 | intid = val & ICH_LR_VIRTUAL_ID_MASK; | |
39 | else | |
40 | intid = val & GICH_LR_VIRTUALID; | |
41 | ||
42 | WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE); | |
43 | ||
44 | kvm_notify_acked_irq(vcpu->kvm, 0, | |
45 | intid - VGIC_NR_PRIVATE_IRQS); | |
46 | } | |
47 | ||
48 | /* | |
49 | * In the next iterations of the vcpu loop, if we sync | |
50 | * the vgic state after flushing it, but before | |
51 | * entering the guest (this happens for pending | |
52 | * signals and vmid rollovers), then make sure we | |
53 | * don't pick up any old maintenance interrupts here. | |
54 | */ | |
55 | cpuif->vgic_eisr = 0; | |
56 | } | |
57 | ||
58 | cpuif->vgic_hcr &= ~ICH_HCR_UIE; | |
59 | } | |
60 | ||
61 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) | |
62 | { | |
63 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
64 | ||
65 | cpuif->vgic_hcr |= ICH_HCR_UIE; | |
66 | } | |
67 | ||
68 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) | |
69 | { | |
70 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
71 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
72 | int lr; | |
73 | ||
74 | for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) { | |
75 | u64 val = cpuif->vgic_lr[lr]; | |
76 | u32 intid; | |
77 | struct vgic_irq *irq; | |
78 | ||
79 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
80 | intid = val & ICH_LR_VIRTUAL_ID_MASK; | |
81 | else | |
82 | intid = val & GICH_LR_VIRTUALID; | |
83 | irq = vgic_get_irq(vcpu->kvm, vcpu, intid); | |
84 | ||
85 | spin_lock(&irq->irq_lock); | |
86 | ||
87 | /* Always preserve the active bit */ | |
88 | irq->active = !!(val & ICH_LR_ACTIVE_BIT); | |
89 | ||
90 | /* Edge is the only case where we preserve the pending bit */ | |
91 | if (irq->config == VGIC_CONFIG_EDGE && | |
92 | (val & ICH_LR_PENDING_BIT)) { | |
93 | irq->pending = true; | |
94 | ||
95 | if (vgic_irq_is_sgi(intid) && | |
96 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
97 | u32 cpuid = val & GICH_LR_PHYSID_CPUID; | |
98 | ||
99 | cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | |
100 | irq->source |= (1 << cpuid); | |
101 | } | |
102 | } | |
103 | ||
104 | /* Clear soft pending state when level irqs have been acked */ | |
105 | if (irq->config == VGIC_CONFIG_LEVEL && | |
106 | !(val & ICH_LR_PENDING_BIT)) { | |
107 | irq->soft_pending = false; | |
108 | irq->pending = irq->line_level; | |
109 | } | |
110 | ||
111 | spin_unlock(&irq->irq_lock); | |
112 | } | |
113 | } | |
114 | ||
115 | /* Requires the irq to be locked already */ | |
116 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | |
117 | { | |
118 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
119 | u64 val = irq->intid; | |
120 | ||
121 | if (irq->pending) { | |
122 | val |= ICH_LR_PENDING_BIT; | |
123 | ||
124 | if (irq->config == VGIC_CONFIG_EDGE) | |
125 | irq->pending = false; | |
126 | ||
127 | if (vgic_irq_is_sgi(irq->intid) && | |
128 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
129 | u32 src = ffs(irq->source); | |
130 | ||
131 | BUG_ON(!src); | |
132 | val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | |
133 | irq->source &= ~(1 << (src - 1)); | |
134 | if (irq->source) | |
135 | irq->pending = true; | |
136 | } | |
137 | } | |
138 | ||
139 | if (irq->active) | |
140 | val |= ICH_LR_ACTIVE_BIT; | |
141 | ||
142 | if (irq->hw) { | |
143 | val |= ICH_LR_HW; | |
144 | val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; | |
145 | } else { | |
146 | if (irq->config == VGIC_CONFIG_LEVEL) | |
147 | val |= ICH_LR_EOI; | |
148 | } | |
149 | ||
150 | /* | |
151 | * We currently only support Group1 interrupts, which is a | |
152 | * known defect. This needs to be addressed at some point. | |
153 | */ | |
154 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
155 | val |= ICH_LR_GROUP; | |
156 | ||
157 | val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; | |
158 | ||
159 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; | |
160 | } | |
161 | ||
162 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) | |
163 | { | |
164 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; | |
165 | } | |
e4823a7a AP |
166 | |
167 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
168 | { | |
169 | u32 vmcr; | |
170 | ||
171 | vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK; | |
172 | vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; | |
173 | vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; | |
174 | vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; | |
175 | ||
176 | vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr; | |
177 | } | |
178 | ||
179 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
180 | { | |
181 | u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr; | |
182 | ||
183 | vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT; | |
184 | vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; | |
185 | vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; | |
186 | vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; | |
187 | } | |
90977732 | 188 | |
ad275b8b EA |
189 | /* not yet implemented */ |
190 | void vgic_v3_enable(struct kvm_vcpu *vcpu) | |
191 | { | |
192 | } | |
193 | ||
90977732 EA |
194 | /** |
195 | * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT | |
196 | * @node: pointer to the DT node | |
197 | * | |
198 | * Returns 0 if a GICv3 has been found, returns an error code otherwise | |
199 | */ | |
200 | int vgic_v3_probe(const struct gic_kvm_info *info) | |
201 | { | |
202 | u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2); | |
203 | ||
204 | /* | |
205 | * The ListRegs field is 5 bits, but there is a architectural | |
206 | * maximum of 16 list registers. Just ignore bit 4... | |
207 | */ | |
208 | kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; | |
209 | kvm_vgic_global_state.can_emulate_gicv2 = false; | |
210 | ||
211 | if (!info->vcpu.start) { | |
212 | kvm_info("GICv3: no GICV resource entry\n"); | |
213 | kvm_vgic_global_state.vcpu_base = 0; | |
214 | } else if (!PAGE_ALIGNED(info->vcpu.start)) { | |
215 | pr_warn("GICV physical address 0x%llx not page aligned\n", | |
216 | (unsigned long long)info->vcpu.start); | |
217 | kvm_vgic_global_state.vcpu_base = 0; | |
218 | } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) { | |
219 | pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n", | |
220 | (unsigned long long)resource_size(&info->vcpu), | |
221 | PAGE_SIZE); | |
222 | kvm_vgic_global_state.vcpu_base = 0; | |
223 | } else { | |
224 | kvm_vgic_global_state.vcpu_base = info->vcpu.start; | |
225 | kvm_vgic_global_state.can_emulate_gicv2 = true; | |
226 | kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); | |
227 | kvm_info("vgic-v2@%llx\n", info->vcpu.start); | |
228 | } | |
229 | if (kvm_vgic_global_state.vcpu_base == 0) | |
230 | kvm_info("disabling GICv2 emulation\n"); | |
231 | kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); | |
232 | ||
233 | kvm_vgic_global_state.vctrl_base = NULL; | |
234 | kvm_vgic_global_state.type = VGIC_V3; | |
235 | kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; | |
236 | ||
237 | return 0; | |
238 | } |