[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic-v3.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_asm.h>

#include "vgic.h"

void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;

	cpuif->vgic_hcr |= ICH_HCR_UIE;
}

static bool lr_signals_eoi_mi(u64 lr_val)
{
	return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
	       !(lr_val & ICH_LR_HW);
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	int lr;

	cpuif->vgic_hcr &= ~ICH_HCR_UIE;

	for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
		u64 val = cpuif->vgic_lr[lr];
		u32 intid;
		struct vgic_irq *irq;

		if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
			intid = val & ICH_LR_VIRTUAL_ID_MASK;
		else
			intid = val & GICH_LR_VIRTUALID;

		/* Notify fds when the guest EOI'ed a level-triggered IRQ */
		if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
			kvm_notify_acked_irq(vcpu->kvm, 0,
					     intid - VGIC_NR_PRIVATE_IRQS);

		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
		if (!irq)	/* An LPI could have been unmapped. */
			continue;

		spin_lock(&irq->irq_lock);

		/* Always preserve the active bit */
		irq->active = !!(val & ICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & ICH_LR_PENDING_BIT)) {
			irq->pending_latch = true;

			if (vgic_irq_is_sgi(intid) &&
			    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & ICH_LR_PENDING_BIT))
				irq->pending_latch = false;
		}

		spin_unlock(&irq->irq_lock);
		vgic_put_irq(vcpu->kvm, irq);
	}

	vgic_cpu->used_lrs = 0;
}

/* Requires the irq to be locked already */
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u64 val = irq->intid;

	if (irq_is_pending(irq)) {
		val |= ICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending_latch = false;

		if (vgic_irq_is_sgi(irq->intid) &&
		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending_latch = true;
		}
	}

	if (irq->active)
		val |= ICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= ICH_LR_HW;
		val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
		/*
		 * Never set pending+active on a HW interrupt, as the
		 * pending state is kept at the physical distributor
		 * level.
		 */
		if (irq->active && irq_is_pending(irq))
			val &= ~ICH_LR_PENDING_BIT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= ICH_LR_EOI;
	}

	/*
	 * We currently only support Group1 interrupts, which is a
	 * known defect. This needs to be addressed at some point.
	 */
	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
		val |= ICH_LR_GROUP;

	val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
}

void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}

void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u32 vmcr;

	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
		vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
			ICH_VMCR_ACK_CTL_MASK;
		vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
			ICH_VMCR_FIQ_EN_MASK;
	} else {
		/*
		 * When emulating GICv3 on GICv3 with SRE=1 on the
		 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
		 */
		vmcr = ICH_VMCR_FIQ_EN_MASK;
	}

	vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
	vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
	vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;

	cpu_if->vgic_vmcr = vmcr;
}

void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u32 vmcr;

	vmcr = cpu_if->vgic_vmcr;

	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
		vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
			ICH_VMCR_ACK_CTL_SHIFT;
		vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
			ICH_VMCR_FIQ_EN_SHIFT;
	} else {
		/*
		 * When emulating GICv3 on GICv3 with SRE=1 on the
		 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
		 */
		vmcrp->fiqen = 1;
		vmcrp->ackctl = 0;
	}

	vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
	vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
}

#define INITIAL_PENDBASER_VALUE						  \
	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)		| \
	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)	| \
	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))

void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * Also, we don't support any form of IRQ/FIQ bypass.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
		vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
				     ICC_SRE_EL1_DFB |
				     ICC_SRE_EL1_SRE);
		vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
	} else {
		vgic_v3->vgic_sre = 0;
	}

	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
					   ICH_VTR_ID_BITS_MASK) >>
					   ICH_VTR_ID_BITS_SHIFT;
	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
					    ICH_VTR_PRI_BITS_MASK) >>
					    ICH_VTR_PRI_BITS_SHIFT) + 1;

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
}

int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
{
	struct kvm_vcpu *vcpu;
	int byte_offset, bit_nr;
	gpa_t pendbase, ptr;
	bool status;
	u8 val;
	int ret;

retry:
	vcpu = irq->target_vcpu;
	if (!vcpu)
		return 0;

	pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);

	byte_offset = irq->intid / BITS_PER_BYTE;
	bit_nr = irq->intid % BITS_PER_BYTE;
	ptr = pendbase + byte_offset;

	ret = kvm_read_guest(kvm, ptr, &val, 1);
	if (ret)
		return ret;

	status = val & (1 << bit_nr);

	spin_lock(&irq->irq_lock);
	if (irq->target_vcpu != vcpu) {
		spin_unlock(&irq->irq_lock);
		goto retry;
	}
	irq->pending_latch = status;
	vgic_queue_irq_unlock(vcpu->kvm, irq);

	if (status) {
		/* clear consumed data */
		val &= ~(1 << bit_nr);
		ret = kvm_write_guest(kvm, ptr, &val, 1);
		if (ret)
			return ret;
	}
	return 0;
}

/**
 * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 * kvm lock and all vcpu lock must be held
 */
int vgic_v3_save_pending_tables(struct kvm *kvm)
{
	struct vgic_dist *dist = &kvm->arch.vgic;
	int last_byte_offset = -1;
	struct vgic_irq *irq;
	int ret;

	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
		int byte_offset, bit_nr;
		struct kvm_vcpu *vcpu;
		gpa_t pendbase, ptr;
		bool stored;
		u8 val;

		vcpu = irq->target_vcpu;
		if (!vcpu)
			continue;

		pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);

		byte_offset = irq->intid / BITS_PER_BYTE;
		bit_nr = irq->intid % BITS_PER_BYTE;
		ptr = pendbase + byte_offset;

		if (byte_offset != last_byte_offset) {
			ret = kvm_read_guest(kvm, ptr, &val, 1);
			if (ret)
				return ret;
			last_byte_offset = byte_offset;
		}

		stored = val & (1U << bit_nr);
		if (stored == irq->pending_latch)
			continue;

		if (irq->pending_latch)
			val |= 1 << bit_nr;
		else
			val &= ~(1 << bit_nr);

		ret = kvm_write_guest(kvm, ptr, &val, 1);
		if (ret)
			return ret;
	}
	return 0;
}

/*
 * Check for overlapping regions and for regions crossing the end of memory
 * for base addresses which have already been set.
 */
bool vgic_v3_check_base(struct kvm *kvm)
{
	struct vgic_dist *d = &kvm->arch.vgic;
	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;

	redist_size *= atomic_read(&kvm->online_vcpus);

	if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
	    d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
		return false;

	if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
	    d->vgic_redist_base + redist_size < d->vgic_redist_base)
		return false;

	/* Both base addresses must be set to check if they overlap */
	if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
		return true;

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
		return true;
	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
		return true;

	return false;
}

int vgic_v3_map_resources(struct kvm *kvm)
{
	int ret = 0;
	struct vgic_dist *dist = &kvm->arch.vgic;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
		kvm_err("Need to set vgic distributor addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v3_check_base(kvm)) {
		kvm_err("VGIC redist and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * For a VGICv3 we require the userland to explicitly initialize
	 * the VGIC before we need to use it.
	 */
	if (!vgic_initialized(kvm)) {
		ret = -EBUSY;
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	if (ret) {
		kvm_err("Unable to register VGICv3 dist MMIO regions\n");
		goto out;
	}

	dist->ready = true;

out:
	return ret;
}

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv3 has been found, returns an error code otherwise
 */
int vgic_v3_probe(const struct gic_kvm_info *info)
{
	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	int ret;

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	kvm_vgic_global_state.can_emulate_gicv2 = false;
	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;

	if (!info->vcpu.start) {
		kvm_info("GICv3: no GICV resource entry\n");
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)info->vcpu.start);
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&info->vcpu),
			PAGE_SIZE);
		kvm_vgic_global_state.vcpu_base = 0;
	} else {
		kvm_vgic_global_state.vcpu_base = info->vcpu.start;
		kvm_vgic_global_state.can_emulate_gicv2 = true;
		ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
		if (ret) {
			kvm_err("Cannot register GICv2 KVM device.\n");
			return ret;
		}
		kvm_info("vgic-v2@%llx\n", info->vcpu.start);
	}
	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	if (ret) {
		kvm_err("Cannot register GICv3 KVM device.\n");
		kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
		return ret;
	}

	if (kvm_vgic_global_state.vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");

	kvm_vgic_global_state.vctrl_base = NULL;
	kvm_vgic_global_state.type = VGIC_V3;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;

	return 0;
}

void vgic_v3_load(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
	 * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
	 * VMCR_EL2 save/restore in the world switch.
	 */
	if (likely(cpu_if->vgic_sre))
		kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
}

void vgic_v3_put(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;

	if (likely(cpu_if->vgic_sre))
		cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
}
Commit	Line	Data
59529f69 MZ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License version 2 as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	13	*/
	14
	15	#include <linux/irqchip/arm-gic-v3.h>
	16	#include <linux/kvm.h>
	17	#include <linux/kvm_host.h>
90977732 EA	18	#include <kvm/arm_vgic.h>
	19	#include <asm/kvm_mmu.h>
	20	#include <asm/kvm_asm.h>
59529f69 MZ	21
	22	#include "vgic.h"
	23
af061499	24	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
59529f69 MZ	25	{
59529f69 MZ	26	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
59529f69	27
af061499	28	cpuif->vgic_hcr \|= ICH_HCR_UIE;
59529f69 MZ	29	}
59529f69 MZ	30
af061499	31	static bool lr_signals_eoi_mi(u64 lr_val)
59529f69	32	{
af061499 CD	33	return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
af061499 CD	34	!(lr_val & ICH_LR_HW);
59529f69 MZ	35	}
	36
	37	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
	38	{
8ac76ef4 CD	39	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
8ac76ef4 CD	40	struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
59529f69 MZ	41	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	42	int lr;
	43
af061499 CD	44	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
af061499 CD	45
8ac76ef4	46	for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
59529f69 MZ	47	u64 val = cpuif->vgic_lr[lr];
	48	u32 intid;
	49	struct vgic_irq *irq;
	50
	51	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	52	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	53	else
	54	intid = val & GICH_LR_VIRTUALID;
af061499 CD	55
	56	/* Notify fds when the guest EOI'ed a level-triggered IRQ */
	57	if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
	58	kvm_notify_acked_irq(vcpu->kvm, 0,
	59	intid - VGIC_NR_PRIVATE_IRQS);
	60
59529f69	61	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
3802411d AP	62	if (!irq) /* An LPI could have been unmapped. */
3802411d AP	63	continue;
59529f69 MZ	64
	65	spin_lock(&irq->irq_lock);
	66
	67	/* Always preserve the active bit */
	68	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
	69
	70	/* Edge is the only case where we preserve the pending bit */
	71	if (irq->config == VGIC_CONFIG_EDGE &&
	72	(val & ICH_LR_PENDING_BIT)) {
8694e4da	73	irq->pending_latch = true;
59529f69 MZ	74
	75	if (vgic_irq_is_sgi(intid) &&
	76	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	77	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
	78
	79	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
	80	irq->source \|= (1 << cpuid);
	81	}
	82	}
	83
637d122b MZ	84	/*
	85	* Clear soft pending state when level irqs have been acked.
	86	* Always regenerate the pending state.
	87	*/
	88	if (irq->config == VGIC_CONFIG_LEVEL) {
	89	if (!(val & ICH_LR_PENDING_BIT))
8694e4da	90	irq->pending_latch = false;
59529f69 MZ	91	}
	92
	93	spin_unlock(&irq->irq_lock);
5dd4b924	94	vgic_put_irq(vcpu->kvm, irq);
59529f69	95	}
8ac76ef4 CD	96
8ac76ef4 CD	97	vgic_cpu->used_lrs = 0;
59529f69 MZ	98	}
	99
	100	/* Requires the irq to be locked already */
	101	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	102	{
	103	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	104	u64 val = irq->intid;
	105
8694e4da	106	if (irq_is_pending(irq)) {
59529f69 MZ	107	val \|= ICH_LR_PENDING_BIT;
	108
	109	if (irq->config == VGIC_CONFIG_EDGE)
8694e4da	110	irq->pending_latch = false;
59529f69 MZ	111
	112	if (vgic_irq_is_sgi(irq->intid) &&
	113	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	114	u32 src = ffs(irq->source);
	115
	116	BUG_ON(!src);
	117	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	118	irq->source &= ~(1 << (src - 1));
	119	if (irq->source)
8694e4da	120	irq->pending_latch = true;
59529f69 MZ	121	}
	122	}
	123
	124	if (irq->active)
	125	val \|= ICH_LR_ACTIVE_BIT;
	126
	127	if (irq->hw) {
	128	val \|= ICH_LR_HW;
	129	val \|= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
3d6e77ad MZ	130	/*
	131	* Never set pending+active on a HW interrupt, as the
	132	* pending state is kept at the physical distributor
	133	* level.
	134	*/
	135	if (irq->active && irq_is_pending(irq))
	136	val &= ~ICH_LR_PENDING_BIT;
59529f69 MZ	137	} else {
	138	if (irq->config == VGIC_CONFIG_LEVEL)
	139	val \|= ICH_LR_EOI;
	140	}
	141
	142	/*
	143	* We currently only support Group1 interrupts, which is a
	144	* known defect. This needs to be addressed at some point.
	145	*/
	146	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	147	val \|= ICH_LR_GROUP;
	148
	149	val \|= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
	150
	151	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
	152	}
	153
	154	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
	155	{
	156	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
	157	}
e4823a7a AP	158
	159	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	160	{
328e5664	161	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
28232a43	162	u32 model = vcpu->kvm->arch.vgic.vgic_model;
e4823a7a AP	163	u32 vmcr;
e4823a7a AP	164
28232a43 CD	165	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	166	vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
	167	ICH_VMCR_ACK_CTL_MASK;
	168	vmcr \|= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
	169	ICH_VMCR_FIQ_EN_MASK;
	170	} else {
	171	/*
	172	* When emulating GICv3 on GICv3 with SRE=1 on the
	173	* VFIQEn bit is RES1 and the VAckCtl bit is RES0.
	174	*/
	175	vmcr = ICH_VMCR_FIQ_EN_MASK;
	176	}
	177
	178	vmcr \|= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
	179	vmcr \|= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
e4823a7a AP	180	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	181	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	182	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
5fb247d7 VK	183	vmcr \|= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
5fb247d7 VK	184	vmcr \|= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
e4823a7a	185
328e5664	186	cpu_if->vgic_vmcr = vmcr;
e4823a7a AP	187	}
	188
	189	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	190	{
328e5664	191	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
28232a43	192	u32 model = vcpu->kvm->arch.vgic.vgic_model;
328e5664 CD	193	u32 vmcr;
	194
	195	vmcr = cpu_if->vgic_vmcr;
e4823a7a	196
28232a43 CD	197	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	198	vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
	199	ICH_VMCR_ACK_CTL_SHIFT;
	200	vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
	201	ICH_VMCR_FIQ_EN_SHIFT;
	202	} else {
	203	/*
	204	* When emulating GICv3 on GICv3 with SRE=1 on the
	205	* VFIQEn bit is RES1 and the VAckCtl bit is RES0.
	206	*/
	207	vmcrp->fiqen = 1;
	208	vmcrp->ackctl = 0;
	209	}
	210
	211	vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
	212	vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
e4823a7a AP	213	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	214	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	215	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
5fb247d7 VK	216	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
5fb247d7 VK	217	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
e4823a7a	218	}
90977732	219
0aa1de57 AP	220	#define INITIAL_PENDBASER_VALUE \
	221	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) \| \
	222	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) \| \
	223	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
	224
ad275b8b EA	225	void vgic_v3_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	226	{
f7b6985c EA	227	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
	228
	229	/*
	230	* By forcing VMCR to zero, the GIC will restore the binary
	231	* points to their reset values. Anything else resets to zero
	232	* anyway.
	233	*/
	234	vgic_v3->vgic_vmcr = 0;
	235	vgic_v3->vgic_elrsr = ~0;
	236
	237	/*
	238	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	239	* way, so we force SRE to 1 to demonstrate this to the guest.
4dfc0505	240	* Also, we don't support any form of IRQ/FIQ bypass.
f7b6985c EA	241	* This goes with the spec allowing the value to be RAO/WI.
f7b6985c EA	242	*/
0aa1de57	243	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
4dfc0505 MZ	244	vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB \|
	245	ICC_SRE_EL1_DFB \|
	246	ICC_SRE_EL1_SRE);
0aa1de57 AP	247	vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
0aa1de57 AP	248	} else {
f7b6985c	249	vgic_v3->vgic_sre = 0;
0aa1de57	250	}
f7b6985c	251
d017d7b0 VK	252	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
	253	ICH_VTR_ID_BITS_MASK) >>
	254	ICH_VTR_ID_BITS_SHIFT;
	255	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
	256	ICH_VTR_PRI_BITS_MASK) >>
	257	ICH_VTR_PRI_BITS_SHIFT) + 1;
	258
f7b6985c EA	259	/* Get the show on the road... */
f7b6985c EA	260	vgic_v3->vgic_hcr = ICH_HCR_EN;
ad275b8b EA	261	}
ad275b8b EA	262
44de9d68 EA	263	int vgic_v3_lpi_sync_pending_status(struct kvm kvm, struct vgic_irq irq)
	264	{
	265	struct kvm_vcpu *vcpu;
	266	int byte_offset, bit_nr;
	267	gpa_t pendbase, ptr;
	268	bool status;
	269	u8 val;
	270	int ret;
	271
	272	retry:
	273	vcpu = irq->target_vcpu;
	274	if (!vcpu)
	275	return 0;
	276
	277	pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
	278
	279	byte_offset = irq->intid / BITS_PER_BYTE;
	280	bit_nr = irq->intid % BITS_PER_BYTE;
	281	ptr = pendbase + byte_offset;
	282
	283	ret = kvm_read_guest(kvm, ptr, &val, 1);
	284	if (ret)
	285	return ret;
	286
	287	status = val & (1 << bit_nr);
	288
	289	spin_lock(&irq->irq_lock);
	290	if (irq->target_vcpu != vcpu) {
	291	spin_unlock(&irq->irq_lock);
	292	goto retry;
	293	}
	294	irq->pending_latch = status;
	295	vgic_queue_irq_unlock(vcpu->kvm, irq);
	296
	297	if (status) {
	298	/* clear consumed data */
	299	val &= ~(1 << bit_nr);
	300	ret = kvm_write_guest(kvm, ptr, &val, 1);
	301	if (ret)
	302	return ret;
	303	}
	304	return 0;
	305	}
	306
28077125 EA	307	/**
	308	* vgic_its_save_pending_tables - Save the pending tables into guest RAM
	309	* kvm lock and all vcpu lock must be held
	310	*/
	311	int vgic_v3_save_pending_tables(struct kvm *kvm)
	312	{
	313	struct vgic_dist *dist = &kvm->arch.vgic;
	314	int last_byte_offset = -1;
	315	struct vgic_irq *irq;
	316	int ret;
	317
	318	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
	319	int byte_offset, bit_nr;
	320	struct kvm_vcpu *vcpu;
	321	gpa_t pendbase, ptr;
	322	bool stored;
	323	u8 val;
	324
	325	vcpu = irq->target_vcpu;
	326	if (!vcpu)
	327	continue;
	328
	329	pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
	330
	331	byte_offset = irq->intid / BITS_PER_BYTE;
	332	bit_nr = irq->intid % BITS_PER_BYTE;
	333	ptr = pendbase + byte_offset;
	334
	335	if (byte_offset != last_byte_offset) {
	336	ret = kvm_read_guest(kvm, ptr, &val, 1);
	337	if (ret)
	338	return ret;
	339	last_byte_offset = byte_offset;
	340	}
	341
	342	stored = val & (1U << bit_nr);
	343	if (stored == irq->pending_latch)
	344	continue;
	345
	346	if (irq->pending_latch)
	347	val \|= 1 << bit_nr;
	348	else
	349	val &= ~(1 << bit_nr);
	350
	351	ret = kvm_write_guest(kvm, ptr, &val, 1);
	352	if (ret)
	353	return ret;
	354	}
	355	return 0;
	356	}
	357
9a746d75 CD	358	/*
	359	* Check for overlapping regions and for regions crossing the end of memory
	360	* for base addresses which have already been set.
	361	*/
	362	bool vgic_v3_check_base(struct kvm *kvm)
b0442ee2 EA	363	{
	364	struct vgic_dist *d = &kvm->arch.vgic;
	365	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
	366
	367	redist_size *= atomic_read(&kvm->online_vcpus);
	368
9a746d75 CD	369	if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
9a746d75 CD	370	d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
b0442ee2	371	return false;
9a746d75 CD	372
	373	if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
	374	d->vgic_redist_base + redist_size < d->vgic_redist_base)
b0442ee2 EA	375	return false;
b0442ee2 EA	376
9a746d75 CD	377	/* Both base addresses must be set to check if they overlap */
	378	if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) \|\|
	379	IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
	380	return true;
	381
b0442ee2 EA	382	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
	383	return true;
	384	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
	385	return true;
	386
	387	return false;
	388	}
	389
	390	int vgic_v3_map_resources(struct kvm *kvm)
	391	{
	392	int ret = 0;
	393	struct vgic_dist *dist = &kvm->arch.vgic;
	394
	395	if (vgic_ready(kvm))
	396	goto out;
	397
	398	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	399	IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
	400	kvm_err("Need to set vgic distributor addresses first\n");
	401	ret = -ENXIO;
	402	goto out;
	403	}
	404
	405	if (!vgic_v3_check_base(kvm)) {
	406	kvm_err("VGIC redist and dist frames overlap\n");
	407	ret = -EINVAL;
	408	goto out;
	409	}
	410
	411	/*
	412	* For a VGICv3 we require the userland to explicitly initialize
	413	* the VGIC before we need to use it.
	414	*/
	415	if (!vgic_initialized(kvm)) {
	416	ret = -EBUSY;
	417	goto out;
	418	}
	419
	420	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	421	if (ret) {
	422	kvm_err("Unable to register VGICv3 dist MMIO regions\n");
	423	goto out;
	424	}
	425
b0442ee2 EA	426	dist->ready = true;
	427
	428	out:
b0442ee2 EA	429	return ret;
	430	}
	431
90977732 EA	432	/**
	433	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
	434	* @node: pointer to the DT node
	435	*
	436	* Returns 0 if a GICv3 has been found, returns an error code otherwise
	437	*/
	438	int vgic_v3_probe(const struct gic_kvm_info *info)
	439	{
	440	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
42c8870f	441	int ret;
90977732 EA	442
	443	/*
	444	* The ListRegs field is 5 bits, but there is a architectural
	445	* maximum of 16 list registers. Just ignore bit 4...
	446	*/
	447	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	448	kvm_vgic_global_state.can_emulate_gicv2 = false;
d017d7b0	449	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
90977732 EA	450
	451	if (!info->vcpu.start) {
	452	kvm_info("GICv3: no GICV resource entry\n");
	453	kvm_vgic_global_state.vcpu_base = 0;
	454	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
	455	pr_warn("GICV physical address 0x%llx not page aligned\n",
	456	(unsigned long long)info->vcpu.start);
	457	kvm_vgic_global_state.vcpu_base = 0;
	458	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	459	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
	460	(unsigned long long)resource_size(&info->vcpu),
	461	PAGE_SIZE);
	462	kvm_vgic_global_state.vcpu_base = 0;
	463	} else {
	464	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	465	kvm_vgic_global_state.can_emulate_gicv2 = true;
42c8870f AP	466	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	467	if (ret) {
	468	kvm_err("Cannot register GICv2 KVM device.\n");
	469	return ret;
	470	}
90977732 EA	471	kvm_info("vgic-v2@%llx\n", info->vcpu.start);
90977732 EA	472	}
42c8870f AP	473	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	474	if (ret) {
	475	kvm_err("Cannot register GICv3 KVM device.\n");
	476	kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
	477	return ret;
	478	}
	479
90977732 EA	480	if (kvm_vgic_global_state.vcpu_base == 0)
90977732 EA	481	kvm_info("disabling GICv2 emulation\n");
90977732 EA	482
	483	kvm_vgic_global_state.vctrl_base = NULL;
	484	kvm_vgic_global_state.type = VGIC_V3;
	485	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
	486
	487	return 0;
	488	}
328e5664 CD	489
	490	void vgic_v3_load(struct kvm_vcpu *vcpu)
	491	{
	492	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	493
ff567614 MZ	494	/*
	495	* If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
	496	* is dependent on ICC_SRE_EL1.SRE, and we have to perform the
	497	* VMCR_EL2 save/restore in the world switch.
	498	*/
	499	if (likely(cpu_if->vgic_sre))
	500	kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
328e5664 CD	501	}
	502
	503	void vgic_v3_put(struct kvm_vcpu *vcpu)
	504	{
	505	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	506
ff567614 MZ	507	if (likely(cpu_if->vgic_sre))
ff567614 MZ	508	cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
328e5664	509	}