[mirror_ubuntu-focal-kernel.git] / virt / kvm / arm / vgic / vgic-v3.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_asm.h>

#include "vgic.h"

void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;

	if (cpuif->vgic_misr & ICH_MISR_EOI) {
		unsigned long eisr_bmap = cpuif->vgic_eisr;
		int lr;

		for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
			u32 intid;
			u64 val = cpuif->vgic_lr[lr];

			if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
				intid = val & ICH_LR_VIRTUAL_ID_MASK;
			else
				intid = val & GICH_LR_VIRTUALID;

			WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);

			/* Only SPIs require notification */
			if (vgic_valid_spi(vcpu->kvm, intid))
				kvm_notify_acked_irq(vcpu->kvm, 0,
						     intid - VGIC_NR_PRIVATE_IRQS);
		}

		/*
		 * In the next iterations of the vcpu loop, if we sync
		 * the vgic state after flushing it, but before
		 * entering the guest (this happens for pending
		 * signals and vmid rollovers), then make sure we
		 * don't pick up any old maintenance interrupts here.
		 */
		cpuif->vgic_eisr = 0;
	}

	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
}

void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;

	cpuif->vgic_hcr |= ICH_HCR_UIE;
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	int lr;

	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
		u64 val = cpuif->vgic_lr[lr];
		u32 intid;
		struct vgic_irq *irq;

		if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
			intid = val & ICH_LR_VIRTUAL_ID_MASK;
		else
			intid = val & GICH_LR_VIRTUALID;
		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
		if (!irq)	/* An LPI could have been unmapped. */
			continue;

		spin_lock(&irq->irq_lock);

		/* Always preserve the active bit */
		irq->active = !!(val & ICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & ICH_LR_PENDING_BIT)) {
			irq->pending_latch = true;

			if (vgic_irq_is_sgi(intid) &&
			    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & ICH_LR_PENDING_BIT))
				irq->pending_latch = false;
		}

		spin_unlock(&irq->irq_lock);
		vgic_put_irq(vcpu->kvm, irq);
	}
}

/* Requires the irq to be locked already */
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u64 val = irq->intid;

	if (irq_is_pending(irq)) {
		val |= ICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending_latch = false;

		if (vgic_irq_is_sgi(irq->intid) &&
		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending_latch = true;
		}
	}

	if (irq->active)
		val |= ICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= ICH_LR_HW;
		val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= ICH_LR_EOI;
	}

	/*
	 * We currently only support Group1 interrupts, which is a
	 * known defect. This needs to be addressed at some point.
	 */
	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
		val |= ICH_LR_GROUP;

	val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
}

void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}

void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	/*
	 * Ignore the FIQen bit, because GIC emulation always implies
	 * SRE=1 which means the vFIQEn bit is also RES1.
	 */
	vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
		 ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
	vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
	vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
}

void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;

	/*
	 * Ignore the FIQen bit, because GIC emulation always implies
	 * SRE=1 which means the vFIQEn bit is also RES1.
	 */
	vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
			ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
	vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
}

#define INITIAL_PENDBASER_VALUE						  \
	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)		| \
	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)	| \
	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))

void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * Also, we don't support any form of IRQ/FIQ bypass.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
		vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
				     ICC_SRE_EL1_DFB |
				     ICC_SRE_EL1_SRE);
		vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
	} else {
		vgic_v3->vgic_sre = 0;
	}

	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
					   ICH_VTR_ID_BITS_MASK) >>
					   ICH_VTR_ID_BITS_SHIFT;
	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
					    ICH_VTR_PRI_BITS_MASK) >>
					    ICH_VTR_PRI_BITS_SHIFT) + 1;

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
}

/* check for overlapping regions and for regions crossing the end of memory */
static bool vgic_v3_check_base(struct kvm *kvm)
{
	struct vgic_dist *d = &kvm->arch.vgic;
	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;

	redist_size *= atomic_read(&kvm->online_vcpus);

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
		return false;
	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
		return false;

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
		return true;
	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
		return true;

	return false;
}

int vgic_v3_map_resources(struct kvm *kvm)
{
	int ret = 0;
	struct vgic_dist *dist = &kvm->arch.vgic;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
		kvm_err("Need to set vgic distributor addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v3_check_base(kvm)) {
		kvm_err("VGIC redist and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * For a VGICv3 we require the userland to explicitly initialize
	 * the VGIC before we need to use it.
	 */
	if (!vgic_initialized(kvm)) {
		ret = -EBUSY;
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	if (ret) {
		kvm_err("Unable to register VGICv3 dist MMIO regions\n");
		goto out;
	}

	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	if (ret) {
		kvm_err("Unable to register VGICv3 redist MMIO regions\n");
		goto out;
	}

	if (vgic_has_its(kvm)) {
		ret = vgic_register_its_iodevs(kvm);
		if (ret) {
			kvm_err("Unable to register VGIC ITS MMIO regions\n");
			goto out;
		}
	}

	dist->ready = true;

out:
	return ret;
}

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv3 has been found, returns an error code otherwise
 */
int vgic_v3_probe(const struct gic_kvm_info *info)
{
	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	int ret;

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	kvm_vgic_global_state.can_emulate_gicv2 = false;
	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;

	if (!info->vcpu.start) {
		kvm_info("GICv3: no GICV resource entry\n");
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)info->vcpu.start);
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&info->vcpu),
			PAGE_SIZE);
		kvm_vgic_global_state.vcpu_base = 0;
	} else {
		kvm_vgic_global_state.vcpu_base = info->vcpu.start;
		kvm_vgic_global_state.can_emulate_gicv2 = true;
		ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
		if (ret) {
			kvm_err("Cannot register GICv2 KVM device.\n");
			return ret;
		}
		kvm_info("vgic-v2@%llx\n", info->vcpu.start);
	}
	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	if (ret) {
		kvm_err("Cannot register GICv3 KVM device.\n");
		kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
		return ret;
	}

	if (kvm_vgic_global_state.vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");

	kvm_vgic_global_state.vctrl_base = NULL;
	kvm_vgic_global_state.type = VGIC_V3;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;

	return 0;
}
Commit	Line	Data
59529f69 MZ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License version 2 as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	13	*/
	14
	15	#include <linux/irqchip/arm-gic-v3.h>
	16	#include <linux/kvm.h>
	17	#include <linux/kvm_host.h>
90977732 EA	18	#include <kvm/arm_vgic.h>
	19	#include <asm/kvm_mmu.h>
	20	#include <asm/kvm_asm.h>
59529f69 MZ	21
	22	#include "vgic.h"
	23
	24	void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
	25	{
	26	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	27	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	28
	29	if (cpuif->vgic_misr & ICH_MISR_EOI) {
	30	unsigned long eisr_bmap = cpuif->vgic_eisr;
	31	int lr;
	32
	33	for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
	34	u32 intid;
	35	u64 val = cpuif->vgic_lr[lr];
	36
	37	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	38	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	39	else
	40	intid = val & GICH_LR_VIRTUALID;
	41
	42	WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
	43
8ca18eec MZ	44	/* Only SPIs require notification */
	45	if (vgic_valid_spi(vcpu->kvm, intid))
	46	kvm_notify_acked_irq(vcpu->kvm, 0,
	47	intid - VGIC_NR_PRIVATE_IRQS);
59529f69 MZ	48	}
	49
	50	/*
	51	* In the next iterations of the vcpu loop, if we sync
	52	* the vgic state after flushing it, but before
	53	* entering the guest (this happens for pending
	54	* signals and vmid rollovers), then make sure we
	55	* don't pick up any old maintenance interrupts here.
	56	*/
	57	cpuif->vgic_eisr = 0;
	58	}
	59
	60	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
	61	}
	62
	63	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
	64	{
	65	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	66
	67	cpuif->vgic_hcr \|= ICH_HCR_UIE;
	68	}
	69
	70	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
	71	{
	72	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	73	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	74	int lr;
	75
	76	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
	77	u64 val = cpuif->vgic_lr[lr];
	78	u32 intid;
	79	struct vgic_irq *irq;
	80
	81	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	82	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	83	else
	84	intid = val & GICH_LR_VIRTUALID;
	85	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
3802411d AP	86	if (!irq) /* An LPI could have been unmapped. */
3802411d AP	87	continue;
59529f69 MZ	88
	89	spin_lock(&irq->irq_lock);
	90
	91	/* Always preserve the active bit */
	92	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
	93
	94	/* Edge is the only case where we preserve the pending bit */
	95	if (irq->config == VGIC_CONFIG_EDGE &&
	96	(val & ICH_LR_PENDING_BIT)) {
8694e4da	97	irq->pending_latch = true;
59529f69 MZ	98
	99	if (vgic_irq_is_sgi(intid) &&
	100	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	101	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
	102
	103	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
	104	irq->source \|= (1 << cpuid);
	105	}
	106	}
	107
637d122b MZ	108	/*
	109	* Clear soft pending state when level irqs have been acked.
	110	* Always regenerate the pending state.
	111	*/
	112	if (irq->config == VGIC_CONFIG_LEVEL) {
	113	if (!(val & ICH_LR_PENDING_BIT))
8694e4da	114	irq->pending_latch = false;
59529f69 MZ	115	}
	116
	117	spin_unlock(&irq->irq_lock);
5dd4b924	118	vgic_put_irq(vcpu->kvm, irq);
59529f69 MZ	119	}
	120	}
	121
	122	/* Requires the irq to be locked already */
	123	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	124	{
	125	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	126	u64 val = irq->intid;
	127
8694e4da	128	if (irq_is_pending(irq)) {
59529f69 MZ	129	val \|= ICH_LR_PENDING_BIT;
	130
	131	if (irq->config == VGIC_CONFIG_EDGE)
8694e4da	132	irq->pending_latch = false;
59529f69 MZ	133
	134	if (vgic_irq_is_sgi(irq->intid) &&
	135	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	136	u32 src = ffs(irq->source);
	137
	138	BUG_ON(!src);
	139	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	140	irq->source &= ~(1 << (src - 1));
	141	if (irq->source)
8694e4da	142	irq->pending_latch = true;
59529f69 MZ	143	}
	144	}
	145
	146	if (irq->active)
	147	val \|= ICH_LR_ACTIVE_BIT;
	148
	149	if (irq->hw) {
	150	val \|= ICH_LR_HW;
	151	val \|= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	152	} else {
	153	if (irq->config == VGIC_CONFIG_LEVEL)
	154	val \|= ICH_LR_EOI;
	155	}
	156
	157	/*
	158	* We currently only support Group1 interrupts, which is a
	159	* known defect. This needs to be addressed at some point.
	160	*/
	161	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	162	val \|= ICH_LR_GROUP;
	163
	164	val \|= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
	165
	166	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
	167	}
	168
	169	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
	170	{
	171	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
	172	}
e4823a7a AP	173
	174	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	175	{
	176	u32 vmcr;
	177
5fb247d7 VK	178	/*
	179	* Ignore the FIQen bit, because GIC emulation always implies
	180	* SRE=1 which means the vFIQEn bit is also RES1.
	181	*/
	182	vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
	183	ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
	184	vmcr \|= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
e4823a7a AP	185	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	186	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	187	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
5fb247d7 VK	188	vmcr \|= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
5fb247d7 VK	189	vmcr \|= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
e4823a7a AP	190
	191	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
	192	}
	193
	194	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	195	{
	196	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
	197
5fb247d7 VK	198	/*
	199	* Ignore the FIQen bit, because GIC emulation always implies
	200	* SRE=1 which means the vFIQEn bit is also RES1.
	201	*/
	202	vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
	203	ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
	204	vmcrp->ctlr \|= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
e4823a7a AP	205	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	206	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	207	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
5fb247d7 VK	208	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
5fb247d7 VK	209	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
e4823a7a	210	}
90977732	211
0aa1de57 AP	212	#define INITIAL_PENDBASER_VALUE \
	213	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) \| \
	214	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) \| \
	215	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
	216
ad275b8b EA	217	void vgic_v3_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	218	{
f7b6985c EA	219	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
	220
	221	/*
	222	* By forcing VMCR to zero, the GIC will restore the binary
	223	* points to their reset values. Anything else resets to zero
	224	* anyway.
	225	*/
	226	vgic_v3->vgic_vmcr = 0;
	227	vgic_v3->vgic_elrsr = ~0;
	228
	229	/*
	230	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	231	* way, so we force SRE to 1 to demonstrate this to the guest.
4dfc0505	232	* Also, we don't support any form of IRQ/FIQ bypass.
f7b6985c EA	233	* This goes with the spec allowing the value to be RAO/WI.
f7b6985c EA	234	*/
0aa1de57	235	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
4dfc0505 MZ	236	vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB \|
	237	ICC_SRE_EL1_DFB \|
	238	ICC_SRE_EL1_SRE);
0aa1de57 AP	239	vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
0aa1de57 AP	240	} else {
f7b6985c	241	vgic_v3->vgic_sre = 0;
0aa1de57	242	}
f7b6985c	243
d017d7b0 VK	244	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
	245	ICH_VTR_ID_BITS_MASK) >>
	246	ICH_VTR_ID_BITS_SHIFT;
	247	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
	248	ICH_VTR_PRI_BITS_MASK) >>
	249	ICH_VTR_PRI_BITS_SHIFT) + 1;
	250
f7b6985c EA	251	/* Get the show on the road... */
f7b6985c EA	252	vgic_v3->vgic_hcr = ICH_HCR_EN;
ad275b8b EA	253	}
ad275b8b EA	254
b0442ee2 EA	255	/* check for overlapping regions and for regions crossing the end of memory */
	256	static bool vgic_v3_check_base(struct kvm *kvm)
	257	{
	258	struct vgic_dist *d = &kvm->arch.vgic;
	259	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
	260
	261	redist_size *= atomic_read(&kvm->online_vcpus);
	262
	263	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
	264	return false;
	265	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
	266	return false;
	267
	268	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
	269	return true;
	270	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
	271	return true;
	272
	273	return false;
	274	}
	275
	276	int vgic_v3_map_resources(struct kvm *kvm)
	277	{
	278	int ret = 0;
	279	struct vgic_dist *dist = &kvm->arch.vgic;
	280
	281	if (vgic_ready(kvm))
	282	goto out;
	283
	284	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	285	IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
	286	kvm_err("Need to set vgic distributor addresses first\n");
	287	ret = -ENXIO;
	288	goto out;
	289	}
	290
	291	if (!vgic_v3_check_base(kvm)) {
	292	kvm_err("VGIC redist and dist frames overlap\n");
	293	ret = -EINVAL;
	294	goto out;
	295	}
	296
	297	/*
	298	* For a VGICv3 we require the userland to explicitly initialize
	299	* the VGIC before we need to use it.
	300	*/
	301	if (!vgic_initialized(kvm)) {
	302	ret = -EBUSY;
	303	goto out;
	304	}
	305
	306	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	307	if (ret) {
	308	kvm_err("Unable to register VGICv3 dist MMIO regions\n");
	309	goto out;
	310	}
	311
	312	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	313	if (ret) {
	314	kvm_err("Unable to register VGICv3 redist MMIO regions\n");
	315	goto out;
	316	}
	317
c7735769 AP	318	if (vgic_has_its(kvm)) {
	319	ret = vgic_register_its_iodevs(kvm);
	320	if (ret) {
	321	kvm_err("Unable to register VGIC ITS MMIO regions\n");
	322	goto out;
	323	}
	324	}
	325
b0442ee2 EA	326	dist->ready = true;
	327
	328	out:
b0442ee2 EA	329	return ret;
	330	}
	331
90977732 EA	332	/**
	333	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
	334	* @node: pointer to the DT node
	335	*
	336	* Returns 0 if a GICv3 has been found, returns an error code otherwise
	337	*/
	338	int vgic_v3_probe(const struct gic_kvm_info *info)
	339	{
	340	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
42c8870f	341	int ret;
90977732 EA	342
	343	/*
	344	* The ListRegs field is 5 bits, but there is a architectural
	345	* maximum of 16 list registers. Just ignore bit 4...
	346	*/
	347	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	348	kvm_vgic_global_state.can_emulate_gicv2 = false;
d017d7b0	349	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
90977732 EA	350
	351	if (!info->vcpu.start) {
	352	kvm_info("GICv3: no GICV resource entry\n");
	353	kvm_vgic_global_state.vcpu_base = 0;
	354	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
	355	pr_warn("GICV physical address 0x%llx not page aligned\n",
	356	(unsigned long long)info->vcpu.start);
	357	kvm_vgic_global_state.vcpu_base = 0;
	358	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	359	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
	360	(unsigned long long)resource_size(&info->vcpu),
	361	PAGE_SIZE);
	362	kvm_vgic_global_state.vcpu_base = 0;
	363	} else {
	364	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	365	kvm_vgic_global_state.can_emulate_gicv2 = true;
42c8870f AP	366	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	367	if (ret) {
	368	kvm_err("Cannot register GICv2 KVM device.\n");
	369	return ret;
	370	}
90977732 EA	371	kvm_info("vgic-v2@%llx\n", info->vcpu.start);
90977732 EA	372	}
42c8870f AP	373	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	374	if (ret) {
	375	kvm_err("Cannot register GICv3 KVM device.\n");
	376	kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
	377	return ret;
	378	}
	379
90977732 EA	380	if (kvm_vgic_global_state.vcpu_base == 0)
90977732 EA	381	kvm_info("disabling GICv2 emulation\n");
90977732 EA	382
	383	kvm_vgic_global_state.vctrl_base = NULL;
	384	kvm_vgic_global_state.type = VGIC_V3;
	385	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
	386
	387	return 0;
	388	}