[mirror_ubuntu-bionic-kernel.git] / virt / kvm / arm / vgic / vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_NEW_H__
#define __KVM_ARM_VGIC_NEW_H__

#include <linux/irqchip/arm-gic-common.h>

#define PRODUCT_ID_KVM		0x4b	/* ASCII code K */
#define IMPLEMENTER_ARM		0x43b

#define VGIC_ADDR_UNDEF		(-1)
#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)

#define INTERRUPT_ID_BITS_SPIS	10
#define INTERRUPT_ID_BITS_ITS	16
#define VGIC_PRI_BITS		5

#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)

#define VGIC_AFFINITY_0_SHIFT 0
#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
#define VGIC_AFFINITY_1_SHIFT 8
#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
#define VGIC_AFFINITY_2_SHIFT 16
#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
#define VGIC_AFFINITY_3_SHIFT 24
#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)

#define VGIC_AFFINITY_LEVEL(reg, level) \
	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))

/*
 * The Userspace encodes the affinity differently from the MPIDR,
 * Below macro converts vgic userspace format to MPIDR reg format.
 */
#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
			    VGIC_AFFINITY_LEVEL(val, 1) | \
			    VGIC_AFFINITY_LEVEL(val, 2) | \
			    VGIC_AFFINITY_LEVEL(val, 3))

/*
 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
 * below macros are defined for CPUREG encoding.
 */
#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0

#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)

/*
 * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
 * below macros are defined for ITS table entry encoding.
 */
#define KVM_ITS_CTE_VALID_SHIFT		63
#define KVM_ITS_CTE_VALID_MASK		BIT_ULL(63)
#define KVM_ITS_CTE_RDBASE_SHIFT	16
#define KVM_ITS_CTE_ICID_MASK		GENMASK_ULL(15, 0)
#define KVM_ITS_ITE_NEXT_SHIFT		48
#define KVM_ITS_ITE_PINTID_SHIFT	16
#define KVM_ITS_ITE_PINTID_MASK		GENMASK_ULL(47, 16)
#define KVM_ITS_ITE_ICID_MASK		GENMASK_ULL(15, 0)
#define KVM_ITS_DTE_VALID_SHIFT		63
#define KVM_ITS_DTE_VALID_MASK		BIT_ULL(63)
#define KVM_ITS_DTE_NEXT_SHIFT		49
#define KVM_ITS_DTE_NEXT_MASK		GENMASK_ULL(62, 49)
#define KVM_ITS_DTE_ITTADDR_SHIFT	5
#define KVM_ITS_DTE_ITTADDR_MASK	GENMASK_ULL(48, 5)
#define KVM_ITS_DTE_SIZE_MASK		GENMASK_ULL(4, 0)
#define KVM_ITS_L1E_VALID_MASK		BIT_ULL(63)
/* we only support 64 kB translation table page size */
#define KVM_ITS_L1E_ADDR_MASK		GENMASK_ULL(51, 16)

/* Requires the irq_lock to be held by the caller. */
static inline bool irq_is_pending(struct vgic_irq *irq)
{
	if (irq->config == VGIC_CONFIG_EDGE)
		return irq->pending_latch;
	else
		return irq->pending_latch || irq->line_level;
}

/*
 * This struct provides an intermediate representation of the fields contained
 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
 * state to userspace can generate either GICv2 or GICv3 CPU interface
 * registers regardless of the hardware backed GIC used.
 */
struct vgic_vmcr {
	u32	grpen0;
	u32	grpen1;

	u32	ackctl;
	u32	fiqen;
	u32	cbpr;
	u32	eoim;

	u32	abpr;
	u32	bpr;
	u32	pmr;  /* Priority mask field in the GICC_PMR and
		       * ICC_PMR_EL1 priority field format */
};

struct vgic_reg_attr {
	struct kvm_vcpu *vcpu;
	gpa_t addr;
};

int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
const struct vgic_register_region *
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
		     gpa_t addr, int len);
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
			      u32 intid);
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
			   unsigned long flags);
void vgic_kick_vcpus(struct kvm *kvm);

int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
		      phys_addr_t addr, phys_addr_t alignment);

void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			  int offset, u32 *val);
void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_enable(struct kvm_vcpu *vcpu);
int vgic_v2_probe(const struct gic_kvm_info *info);
int vgic_v2_map_resources(struct kvm *kvm);
int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
			     enum vgic_type);

void vgic_v2_init_lrs(void);
void vgic_v2_load(struct kvm_vcpu *vcpu);
void vgic_v2_put(struct kvm_vcpu *vcpu);

static inline void vgic_get_irq_kref(struct vgic_irq *irq)
{
	if (irq->intid < VGIC_MIN_LPI)
		return;

	kref_get(&irq->refcount);
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_enable(struct kvm_vcpu *vcpu);
int vgic_v3_probe(const struct gic_kvm_info *info);
int vgic_v3_map_resources(struct kvm *kvm);
int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
int vgic_v3_save_pending_tables(struct kvm *kvm);
int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
bool vgic_v3_check_base(struct kvm *kvm);

void vgic_v3_load(struct kvm_vcpu *vcpu);
void vgic_v3_put(struct kvm_vcpu *vcpu);

bool vgic_has_its(struct kvm *kvm);
int kvm_vgic_register_its_device(void);
void vgic_enable_lpis(struct kvm_vcpu *vcpu);
int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 u64 id, u64 *val);
int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
				u64 *reg);
int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
				    u32 intid, u64 *val);
int kvm_register_vgic_device(unsigned long type);
void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
int vgic_lazy_init(struct kvm *kvm);
int vgic_init(struct kvm *kvm);

int vgic_debug_init(struct kvm *kvm);
int vgic_debug_destroy(struct kvm *kvm);

bool lock_all_vcpus(struct kvm *kvm);
void unlock_all_vcpus(struct kvm *kvm);

static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
{
	struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;

	/*
	 * num_pri_bits are initialized with HW supported values.
	 * We can rely safely on num_pri_bits even if VM has not
	 * restored ICC_CTLR_EL1 before restoring APnR registers.
	 */
	switch (cpu_if->num_pri_bits) {
	case 7: return 3;
	case 6: return 1;
	default: return 0;
	}
}

int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
			 u32 devid, u32 eventid, struct vgic_irq **irq);
struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);

bool vgic_supports_direct_msis(struct kvm *kvm);
int vgic_v4_init(struct kvm *kvm);
void vgic_v4_teardown(struct kvm *kvm);
int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);

#endif
Commit	Line	Data
64a959d6 CD	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __KVM_ARM_VGIC_NEW_H__
	17	#define __KVM_ARM_VGIC_NEW_H__
	18
90977732 EA	19	#include <linux/irqchip/arm-gic-common.h>
90977732 EA	20
2b0cda87 MZ	21	#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
	22	#define IMPLEMENTER_ARM 0x43b
	23
e2c1f9ab EA	24	#define VGIC_ADDR_UNDEF (-1)
	25	#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
	26
fd59ed3b	27	#define INTERRUPT_ID_BITS_SPIS 10
33d3bc95	28	#define INTERRUPT_ID_BITS_ITS 16
055658bf AP	29	#define VGIC_PRI_BITS 5
055658bf AP	30
0919e84c MZ	31	#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
0919e84c MZ	32
94574c94 VK	33	#define VGIC_AFFINITY_0_SHIFT 0
	34	#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
	35	#define VGIC_AFFINITY_1_SHIFT 8
	36	#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
	37	#define VGIC_AFFINITY_2_SHIFT 16
	38	#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
	39	#define VGIC_AFFINITY_3_SHIFT 24
	40	#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
	41
	42	#define VGIC_AFFINITY_LEVEL(reg, level) \
	43	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	44	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
	45
	46	/*
	47	* The Userspace encodes the affinity differently from the MPIDR,
	48	* Below macro converts vgic userspace format to MPIDR reg format.
	49	*/
	50	#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) \| \
	51	VGIC_AFFINITY_LEVEL(val, 1) \| \
	52	VGIC_AFFINITY_LEVEL(val, 2) \| \
	53	VGIC_AFFINITY_LEVEL(val, 3))
	54
d017d7b0 VK	55	/*
	56	* As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
	57	* below macros are defined for CPUREG encoding.
	58	*/
	59	#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
	60	#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
	61	#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
	62	#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
	63	#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
	64	#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
	65	#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
	66	#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
	67	#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
	68	#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
	69
	70	#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK \| \
	71	KVM_REG_ARM_VGIC_SYSREG_OP1_MASK \| \
	72	KVM_REG_ARM_VGIC_SYSREG_CRN_MASK \| \
	73	KVM_REG_ARM_VGIC_SYSREG_CRM_MASK \| \
	74	KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
	75
ea1ad53e EA	76	/*
	77	* As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
	78	* below macros are defined for ITS table entry encoding.
	79	*/
	80	#define KVM_ITS_CTE_VALID_SHIFT 63
	81	#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
	82	#define KVM_ITS_CTE_RDBASE_SHIFT 16
	83	#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
eff484e0 EA	84	#define KVM_ITS_ITE_NEXT_SHIFT 48
	85	#define KVM_ITS_ITE_PINTID_SHIFT 16
	86	#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
	87	#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
57a9a117 EA	88	#define KVM_ITS_DTE_VALID_SHIFT 63
	89	#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
	90	#define KVM_ITS_DTE_NEXT_SHIFT 49
	91	#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
	92	#define KVM_ITS_DTE_ITTADDR_SHIFT 5
	93	#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
	94	#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
	95	#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
	96	/* we only support 64 kB translation table page size */
	97	#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
ea1ad53e	98
be4d20a9	99	/* Requires the irq_lock to be held by the caller. */
8694e4da CD	100	static inline bool irq_is_pending(struct vgic_irq *irq)
	101	{
	102	if (irq->config == VGIC_CONFIG_EDGE)
	103	return irq->pending_latch;
	104	else
	105	return irq->pending_latch \|\| irq->line_level;
	106	}
	107
6d56111c CD	108	/*
	109	* This struct provides an intermediate representation of the fields contained
	110	* in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
	111	* state to userspace can generate either GICv2 or GICv3 CPU interface
	112	* registers regardless of the hardware backed GIC used.
	113	*/
e4823a7a	114	struct vgic_vmcr {
28232a43 CD	115	u32 grpen0;
	116	u32 grpen1;
	117
	118	u32 ackctl;
	119	u32 fiqen;
	120	u32 cbpr;
	121	u32 eoim;
	122
e4823a7a AP	123	u32 abpr;
e4823a7a AP	124	u32 bpr;
6d56111c CD	125	u32 pmr; /* Priority mask field in the GICC_PMR and
6d56111c CD	126	* ICC_PMR_EL1 priority field format */
e4823a7a AP	127	};
e4823a7a AP	128
94574c94 VK	129	struct vgic_reg_attr {
	130	struct kvm_vcpu *vcpu;
	131	gpa_t addr;
	132	};
	133
	134	int vgic_v3_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	135	struct vgic_reg_attr *reg_attr);
	136	int vgic_v2_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	137	struct vgic_reg_attr *reg_attr);
	138	const struct vgic_register_region *
	139	vgic_get_mmio_region(struct kvm_vcpu vcpu, struct vgic_io_device iodev,
	140	gpa_t addr, int len);
64a959d6 CD	141	struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu,
64a959d6 CD	142	u32 intid);
5dd4b924	143	void vgic_put_irq(struct kvm kvm, struct vgic_irq irq);
006df0f3 CD	144	bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq,
006df0f3 CD	145	unsigned long flags);
2b0cda87	146	void vgic_kick_vcpus(struct kvm *kvm);
64a959d6	147
1085fdc6 AP	148	int vgic_check_ioaddr(struct kvm kvm, phys_addr_t ioaddr,
	149	phys_addr_t addr, phys_addr_t alignment);
	150
140b086d MZ	151	void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
	152	void vgic_v2_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	153	void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
	154	void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
9c2a3e60	155	void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
f94591e2	156	int vgic_v2_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
c3199f28 CD	157	int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
c3199f28 CD	158	int offset, u32 *val);
878c569e AP	159	int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
878c569e AP	160	int offset, u32 *val);
e4823a7a AP	161	void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
e4823a7a AP	162	void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b	163	void vgic_v2_enable(struct kvm_vcpu *vcpu);
90977732	164	int vgic_v2_probe(const struct gic_kvm_info *info);
b0442ee2	165	int vgic_v2_map_resources(struct kvm *kvm);
fb848db3 AP	166	int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
fb848db3 AP	167	enum vgic_type);
140b086d	168
5b0d2cc2	169	void vgic_v2_init_lrs(void);
328e5664 CD	170	void vgic_v2_load(struct kvm_vcpu *vcpu);
328e5664 CD	171	void vgic_v2_put(struct kvm_vcpu *vcpu);
5b0d2cc2	172
d97594e6 MZ	173	static inline void vgic_get_irq_kref(struct vgic_irq *irq)
	174	{
	175	if (irq->intid < VGIC_MIN_LPI)
	176	return;
	177
	178	kref_get(&irq->refcount);
	179	}
	180
59529f69 MZ	181	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
	182	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	183	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
	184	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
9c2a3e60	185	void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
e4823a7a AP	186	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
e4823a7a AP	187	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b	188	void vgic_v3_enable(struct kvm_vcpu *vcpu);
90977732	189	int vgic_v3_probe(const struct gic_kvm_info *info);
b0442ee2	190	int vgic_v3_map_resources(struct kvm *kvm);
44de9d68	191	int vgic_v3_lpi_sync_pending_status(struct kvm kvm, struct vgic_irq irq);
28077125	192	int vgic_v3_save_pending_tables(struct kvm *kvm);
1aab6f46 CD	193	int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
1aab6f46 CD	194	int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
9a746d75	195	bool vgic_v3_check_base(struct kvm *kvm);
7a1ff708	196
328e5664 CD	197	void vgic_v3_load(struct kvm_vcpu *vcpu);
	198	void vgic_v3_put(struct kvm_vcpu *vcpu);
	199
59c5ab40	200	bool vgic_has_its(struct kvm *kvm);
0e4e82f1	201	int kvm_vgic_register_its_device(void);
33d3bc95	202	void vgic_enable_lpis(struct kvm_vcpu *vcpu);
2891a7df	203	int vgic_its_inject_msi(struct kvm kvm, struct kvm_msi msi);
94574c94 VK	204	int vgic_v3_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
	205	int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	206	int offset, u32 *val);
	207	int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	208	int offset, u32 *val);
d017d7b0 VK	209	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	210	u64 id, u64 *val);
	211	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	212	u64 *reg);
e96a006c VK	213	int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
e96a006c VK	214	u32 intid, u64 *val);
42c8870f	215	int kvm_register_vgic_device(unsigned long type);
5fb247d7 VK	216	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
5fb247d7 VK	217	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b EA	218	int vgic_lazy_init(struct kvm *kvm);
ad275b8b EA	219	int vgic_init(struct kvm *kvm);
c86c7721	220
10f92c4c CD	221	int vgic_debug_init(struct kvm *kvm);
	222	int vgic_debug_destroy(struct kvm *kvm);
	223
dfc99f85 EA	224	bool lock_all_vcpus(struct kvm *kvm);
	225	void unlock_all_vcpus(struct kvm *kvm);
	226
50f5bd57 CD	227	static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
	228	{
	229	struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
	230
	231	/*
	232	* num_pri_bits are initialized with HW supported values.
	233	* We can rely safely on num_pri_bits even if VM has not
	234	* restored ICC_CTLR_EL1 before restoring APnR registers.
	235	*/
	236	switch (cpu_if->num_pri_bits) {
	237	case 7: return 3;
	238	case 6: return 1;
	239	default: return 0;
	240	}
	241	}
	242
bebfd2a2 MZ	243	int vgic_its_resolve_lpi(struct kvm kvm, struct vgic_its its,
	244	u32 devid, u32 eventid, struct vgic_irq **irq);
	245	struct vgic_its vgic_msi_to_its(struct kvm kvm, struct kvm_msi *msi);
	246
e7c48059	247	bool vgic_supports_direct_msis(struct kvm *kvm);
74fe55dc MZ	248	int vgic_v4_init(struct kvm *kvm);
74fe55dc MZ	249	void vgic_v4_teardown(struct kvm *kvm);
62775797 MZ	250	int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
62775797 MZ	251	int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);
e7c48059	252
64a959d6	253	#endif