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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
6c3d63c9 | 27 | #include <linux/rculist.h> |
2a2f3e26 | 28 | #include <linux/uaccess.h> |
01ac5e34 | 29 | |
1a89dd91 | 30 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
31 | #include <asm/kvm_arm.h> |
32 | #include <asm/kvm_mmu.h> | |
174178fe | 33 | #include <trace/events/kvm.h> |
6777f77f AP |
34 | #include <asm/kvm.h> |
35 | #include <kvm/iodev.h> | |
1a89dd91 | 36 | |
b47ef92a MZ |
37 | /* |
38 | * How the whole thing works (courtesy of Christoffer Dall): | |
39 | * | |
40 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
7e362919 CD |
41 | * something is pending on the CPU interface. |
42 | * - Interrupts that are pending on the distributor are stored on the | |
43 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land | |
44 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the | |
45 | * arch. timers). | |
b47ef92a MZ |
46 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
47 | * recalculated | |
48 | * - To calculate the oracle, we need info for each cpu from | |
49 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
50 | * - PPI: dist->irq_pending & dist->irq_enable |
51 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
7e362919 | 52 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
b47ef92a MZ |
53 | * registers, stored on each vcpu. We only keep one bit of |
54 | * information per interrupt, making sure that only one vcpu can | |
55 | * accept the interrupt. | |
7e362919 | 56 | * - If any of the above state changes, we must recalculate the oracle. |
b47ef92a MZ |
57 | * - The same is true when injecting an interrupt, except that we only |
58 | * consider a single interrupt at a time. The irq_spi_cpu array | |
59 | * contains the target CPU for each SPI. | |
60 | * | |
61 | * The handling of level interrupts adds some extra complexity. We | |
62 | * need to track when the interrupt has been EOIed, so we can sample | |
63 | * the 'line' again. This is achieved as such: | |
64 | * | |
65 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 66 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
67 | * will be ignored for further interrupts. The interrupt is injected |
68 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
69 | * maintenance interrupt on EOI). | |
70 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 71 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 72 | * interrupt line to be sampled again. |
faa1b46c CD |
73 | * - Note that level-triggered interrupts can also be set to pending from |
74 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
75 | * cause the interrupt to become inactive in such a situation. | |
76 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
77 | * inactive as long as the external input line is held high. | |
6c3d63c9 MZ |
78 | * |
79 | * | |
80 | * Initialization rules: there are multiple stages to the vgic | |
81 | * initialization, both for the distributor and the CPU interfaces. | |
82 | * | |
83 | * Distributor: | |
84 | * | |
85 | * - kvm_vgic_early_init(): initialization of static data that doesn't | |
86 | * depend on any sizing information or emulation type. No allocation | |
87 | * is allowed there. | |
88 | * | |
89 | * - vgic_init(): allocation and initialization of the generic data | |
90 | * structures that depend on sizing information (number of CPUs, | |
91 | * number of interrupts). Also initializes the vcpu specific data | |
92 | * structures. Can be executed lazily for GICv2. | |
93 | * [to be renamed to kvm_vgic_init??] | |
94 | * | |
95 | * CPU Interface: | |
96 | * | |
97 | * - kvm_vgic_cpu_early_init(): initialization of static data that | |
98 | * doesn't depend on any sizing information or emulation type. No | |
99 | * allocation is allowed there. | |
b47ef92a MZ |
100 | */ |
101 | ||
83215812 | 102 | #include "vgic.h" |
330690cd | 103 | |
a1fcb44e | 104 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 105 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
106 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
107 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
6c3d63c9 MZ |
108 | static struct irq_phys_map *vgic_irq_map_search(struct kvm_vcpu *vcpu, |
109 | int virt_irq); | |
01ac5e34 | 110 | |
8f186d52 MZ |
111 | static const struct vgic_ops *vgic_ops; |
112 | static const struct vgic_params *vgic; | |
b47ef92a | 113 | |
b26e5fda AP |
114 | static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
115 | { | |
116 | vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source); | |
117 | } | |
118 | ||
119 | static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
120 | { | |
121 | return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); | |
122 | } | |
123 | ||
124 | int kvm_vgic_map_resources(struct kvm *kvm) | |
125 | { | |
126 | return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); | |
127 | } | |
128 | ||
9662fb48 | 129 | /* |
c1bfb577 MZ |
130 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
131 | * extracts u32s out of them. | |
9662fb48 VK |
132 | * |
133 | * This does not work on 64-bit BE systems, because the bitmap access | |
134 | * will store two consecutive 32-bit words with the higher-addressed | |
135 | * register's bits at the lower index and the lower-addressed register's | |
136 | * bits at the higher index. | |
137 | * | |
138 | * Therefore, swizzle the register index when accessing the 32-bit word | |
139 | * registers to access the right register's value. | |
140 | */ | |
141 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
142 | #define REG_OFFSET_SWIZZLE 1 | |
143 | #else | |
144 | #define REG_OFFSET_SWIZZLE 0 | |
145 | #endif | |
b47ef92a | 146 | |
c1bfb577 MZ |
147 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
148 | { | |
149 | int nr_longs; | |
150 | ||
151 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); | |
152 | ||
153 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); | |
154 | if (!b->private) | |
155 | return -ENOMEM; | |
156 | ||
157 | b->shared = b->private + nr_cpus; | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static void vgic_free_bitmap(struct vgic_bitmap *b) | |
163 | { | |
164 | kfree(b->private); | |
165 | b->private = NULL; | |
166 | b->shared = NULL; | |
167 | } | |
168 | ||
2df36a5d CD |
169 | /* |
170 | * Call this function to convert a u64 value to an unsigned long * bitmask | |
171 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. | |
172 | * | |
173 | * Warning: Calling this function may modify *val. | |
174 | */ | |
175 | static unsigned long *u64_to_bitmask(u64 *val) | |
176 | { | |
177 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 | |
178 | *val = (*val >> 32) | (*val << 32); | |
179 | #endif | |
180 | return (unsigned long *)val; | |
181 | } | |
182 | ||
83215812 | 183 | u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) |
b47ef92a MZ |
184 | { |
185 | offset >>= 2; | |
186 | if (!offset) | |
c1bfb577 | 187 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
b47ef92a | 188 | else |
c1bfb577 | 189 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
190 | } |
191 | ||
192 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
193 | int cpuid, int irq) | |
194 | { | |
195 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
c1bfb577 | 196 | return test_bit(irq, x->private + cpuid); |
b47ef92a | 197 | |
c1bfb577 | 198 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
b47ef92a MZ |
199 | } |
200 | ||
83215812 AP |
201 | void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, |
202 | int irq, int val) | |
b47ef92a MZ |
203 | { |
204 | unsigned long *reg; | |
205 | ||
206 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
c1bfb577 | 207 | reg = x->private + cpuid; |
b47ef92a | 208 | } else { |
c1bfb577 | 209 | reg = x->shared; |
b47ef92a MZ |
210 | irq -= VGIC_NR_PRIVATE_IRQS; |
211 | } | |
212 | ||
213 | if (val) | |
214 | set_bit(irq, reg); | |
215 | else | |
216 | clear_bit(irq, reg); | |
217 | } | |
218 | ||
219 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
220 | { | |
c1bfb577 | 221 | return x->private + cpuid; |
b47ef92a MZ |
222 | } |
223 | ||
83215812 | 224 | unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) |
b47ef92a | 225 | { |
c1bfb577 MZ |
226 | return x->shared; |
227 | } | |
228 | ||
229 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) | |
230 | { | |
231 | int size; | |
232 | ||
233 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; | |
234 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
235 | ||
236 | x->private = kzalloc(size, GFP_KERNEL); | |
237 | if (!x->private) | |
238 | return -ENOMEM; | |
239 | ||
240 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static void vgic_free_bytemap(struct vgic_bytemap *b) | |
245 | { | |
246 | kfree(b->private); | |
247 | b->private = NULL; | |
248 | b->shared = NULL; | |
b47ef92a MZ |
249 | } |
250 | ||
83215812 | 251 | u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) |
b47ef92a | 252 | { |
c1bfb577 MZ |
253 | u32 *reg; |
254 | ||
255 | if (offset < VGIC_NR_PRIVATE_IRQS) { | |
256 | reg = x->private; | |
257 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; | |
258 | } else { | |
259 | reg = x->shared; | |
260 | offset -= VGIC_NR_PRIVATE_IRQS; | |
261 | } | |
262 | ||
263 | return reg + (offset / sizeof(u32)); | |
b47ef92a MZ |
264 | } |
265 | ||
266 | #define VGIC_CFG_LEVEL 0 | |
267 | #define VGIC_CFG_EDGE 1 | |
268 | ||
269 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
270 | { | |
271 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
272 | int irq_val; | |
273 | ||
274 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
275 | return irq_val == VGIC_CFG_EDGE; | |
276 | } | |
277 | ||
278 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
279 | { | |
280 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
281 | ||
282 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
283 | } | |
284 | ||
dbf20f9d | 285 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
286 | { |
287 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
288 | ||
dbf20f9d | 289 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
290 | } |
291 | ||
47a98b15 CD |
292 | static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq) |
293 | { | |
294 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
295 | ||
296 | return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq); | |
297 | } | |
298 | ||
dbf20f9d | 299 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
300 | { |
301 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
302 | ||
dbf20f9d | 303 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
304 | } |
305 | ||
dbf20f9d | 306 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
307 | { |
308 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
309 | ||
dbf20f9d | 310 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
311 | } |
312 | ||
47a98b15 CD |
313 | static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq) |
314 | { | |
315 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
316 | ||
317 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1); | |
318 | } | |
319 | ||
320 | static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq) | |
321 | { | |
322 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
323 | ||
324 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0); | |
325 | } | |
326 | ||
faa1b46c CD |
327 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
328 | { | |
329 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
330 | ||
331 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
332 | } | |
333 | ||
334 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
335 | { | |
336 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
337 | ||
338 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
339 | } | |
340 | ||
341 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
342 | { | |
343 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
344 | ||
345 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
346 | } | |
347 | ||
348 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
349 | { | |
350 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
351 | ||
352 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
353 | } | |
354 | ||
355 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
356 | { | |
357 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
358 | ||
359 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
360 | } | |
361 | ||
9d949dce MZ |
362 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
363 | { | |
364 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
365 | ||
227844f5 | 366 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
367 | } |
368 | ||
83215812 | 369 | void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
370 | { |
371 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
372 | ||
227844f5 | 373 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
374 | } |
375 | ||
83215812 | 376 | void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
377 | { |
378 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
379 | ||
227844f5 | 380 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
381 | } |
382 | ||
383 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
384 | { | |
385 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
386 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
387 | else | |
388 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
389 | vcpu->arch.vgic_cpu.pending_shared); | |
390 | } | |
391 | ||
83215812 | 392 | void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
393 | { |
394 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
395 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
396 | else | |
397 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
398 | vcpu->arch.vgic_cpu.pending_shared); | |
399 | } | |
400 | ||
dbf20f9d CD |
401 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
402 | { | |
7a67b4b7 | 403 | return !vgic_irq_is_queued(vcpu, irq); |
dbf20f9d CD |
404 | } |
405 | ||
1a89dd91 MZ |
406 | /** |
407 | * vgic_reg_access - access vgic register | |
408 | * @mmio: pointer to the data describing the mmio access | |
409 | * @reg: pointer to the virtual backing of vgic distributor data | |
410 | * @offset: least significant 2 bits used for word offset | |
411 | * @mode: ACCESS_ mode (see defines above) | |
412 | * | |
413 | * Helper to make vgic register access easier using one of the access | |
414 | * modes defined for vgic register access | |
415 | * (read,raz,write-ignored,setbit,clearbit,write) | |
416 | */ | |
83215812 AP |
417 | void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, |
418 | phys_addr_t offset, int mode) | |
1a89dd91 MZ |
419 | { |
420 | int word_offset = (offset & 3) * 8; | |
421 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
422 | u32 regval; | |
423 | ||
424 | /* | |
425 | * Any alignment fault should have been delivered to the guest | |
426 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
427 | */ | |
428 | ||
429 | if (reg) { | |
430 | regval = *reg; | |
431 | } else { | |
432 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
433 | regval = 0; | |
434 | } | |
435 | ||
436 | if (mmio->is_write) { | |
437 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
438 | switch (ACCESS_WRITE_MASK(mode)) { | |
439 | case ACCESS_WRITE_IGNORED: | |
440 | return; | |
441 | ||
442 | case ACCESS_WRITE_SETBIT: | |
443 | regval |= data; | |
444 | break; | |
445 | ||
446 | case ACCESS_WRITE_CLEARBIT: | |
447 | regval &= ~data; | |
448 | break; | |
449 | ||
450 | case ACCESS_WRITE_VALUE: | |
451 | regval = (regval & ~(mask << word_offset)) | data; | |
452 | break; | |
453 | } | |
454 | *reg = regval; | |
455 | } else { | |
456 | switch (ACCESS_READ_MASK(mode)) { | |
457 | case ACCESS_READ_RAZ: | |
458 | regval = 0; | |
459 | /* fall through */ | |
460 | ||
461 | case ACCESS_READ_VALUE: | |
462 | mmio_data_write(mmio, mask, regval >> word_offset); | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
83215812 AP |
467 | bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
468 | phys_addr_t offset) | |
b47ef92a MZ |
469 | { |
470 | vgic_reg_access(mmio, NULL, offset, | |
471 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
472 | return false; | |
473 | } | |
474 | ||
83215812 AP |
475 | bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, |
476 | phys_addr_t offset, int vcpu_id, int access) | |
b47ef92a | 477 | { |
d97f683d AP |
478 | u32 *reg; |
479 | int mode = ACCESS_READ_VALUE | access; | |
480 | struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id); | |
481 | ||
482 | reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset); | |
483 | vgic_reg_access(mmio, reg, offset, mode); | |
b47ef92a | 484 | if (mmio->is_write) { |
d97f683d AP |
485 | if (access & ACCESS_WRITE_CLEARBIT) { |
486 | if (offset < 4) /* Force SGI enabled */ | |
487 | *reg |= 0xffff; | |
488 | vgic_retire_disabled_irqs(target_vcpu); | |
489 | } | |
490 | vgic_update_state(kvm); | |
b47ef92a MZ |
491 | return true; |
492 | } | |
493 | ||
494 | return false; | |
495 | } | |
496 | ||
83215812 AP |
497 | bool vgic_handle_set_pending_reg(struct kvm *kvm, |
498 | struct kvm_exit_mmio *mmio, | |
499 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 500 | { |
9da48b55 | 501 | u32 *reg, orig; |
faa1b46c | 502 | u32 level_mask; |
d97f683d AP |
503 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT; |
504 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 505 | |
d97f683d | 506 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset); |
faa1b46c CD |
507 | level_mask = (~(*reg)); |
508 | ||
509 | /* Mark both level and edge triggered irqs as pending */ | |
d97f683d | 510 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 511 | orig = *reg; |
d97f683d | 512 | vgic_reg_access(mmio, reg, offset, mode); |
faa1b46c | 513 | |
b47ef92a | 514 | if (mmio->is_write) { |
faa1b46c CD |
515 | /* Set the soft-pending flag only for level-triggered irqs */ |
516 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
517 | vcpu_id, offset); |
518 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c CD |
519 | *reg &= level_mask; |
520 | ||
9da48b55 CD |
521 | /* Ignore writes to SGIs */ |
522 | if (offset < 2) { | |
523 | *reg &= ~0xffff; | |
524 | *reg |= orig & 0xffff; | |
525 | } | |
526 | ||
d97f683d | 527 | vgic_update_state(kvm); |
b47ef92a MZ |
528 | return true; |
529 | } | |
530 | ||
531 | return false; | |
532 | } | |
533 | ||
83215812 AP |
534 | bool vgic_handle_clear_pending_reg(struct kvm *kvm, |
535 | struct kvm_exit_mmio *mmio, | |
536 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 537 | { |
faa1b46c | 538 | u32 *level_active; |
9da48b55 | 539 | u32 *reg, orig; |
d97f683d AP |
540 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT; |
541 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 542 | |
d97f683d | 543 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 544 | orig = *reg; |
d97f683d | 545 | vgic_reg_access(mmio, reg, offset, mode); |
b47ef92a | 546 | if (mmio->is_write) { |
faa1b46c CD |
547 | /* Re-set level triggered level-active interrupts */ |
548 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
d97f683d AP |
549 | vcpu_id, offset); |
550 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); | |
faa1b46c CD |
551 | *reg |= *level_active; |
552 | ||
9da48b55 CD |
553 | /* Ignore writes to SGIs */ |
554 | if (offset < 2) { | |
555 | *reg &= ~0xffff; | |
556 | *reg |= orig & 0xffff; | |
557 | } | |
558 | ||
faa1b46c CD |
559 | /* Clear soft-pending flags */ |
560 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
561 | vcpu_id, offset); |
562 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c | 563 | |
d97f683d | 564 | vgic_update_state(kvm); |
b47ef92a MZ |
565 | return true; |
566 | } | |
b47ef92a MZ |
567 | return false; |
568 | } | |
569 | ||
47a98b15 CD |
570 | bool vgic_handle_set_active_reg(struct kvm *kvm, |
571 | struct kvm_exit_mmio *mmio, | |
572 | phys_addr_t offset, int vcpu_id) | |
573 | { | |
574 | u32 *reg; | |
575 | struct vgic_dist *dist = &kvm->arch.vgic; | |
576 | ||
577 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); | |
578 | vgic_reg_access(mmio, reg, offset, | |
579 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
580 | ||
581 | if (mmio->is_write) { | |
582 | vgic_update_state(kvm); | |
583 | return true; | |
584 | } | |
585 | ||
586 | return false; | |
587 | } | |
588 | ||
589 | bool vgic_handle_clear_active_reg(struct kvm *kvm, | |
590 | struct kvm_exit_mmio *mmio, | |
591 | phys_addr_t offset, int vcpu_id) | |
592 | { | |
593 | u32 *reg; | |
594 | struct vgic_dist *dist = &kvm->arch.vgic; | |
595 | ||
596 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); | |
597 | vgic_reg_access(mmio, reg, offset, | |
598 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
599 | ||
600 | if (mmio->is_write) { | |
601 | vgic_update_state(kvm); | |
602 | return true; | |
603 | } | |
604 | ||
605 | return false; | |
606 | } | |
607 | ||
b47ef92a MZ |
608 | static u32 vgic_cfg_expand(u16 val) |
609 | { | |
610 | u32 res = 0; | |
611 | int i; | |
612 | ||
613 | /* | |
614 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
615 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
616 | */ | |
617 | for (i = 0; i < 16; i++) | |
618 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
619 | ||
620 | return res; | |
621 | } | |
622 | ||
623 | static u16 vgic_cfg_compress(u32 val) | |
624 | { | |
625 | u16 res = 0; | |
626 | int i; | |
627 | ||
628 | /* | |
629 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
630 | * abcd...mnop which is what we really care about. | |
631 | */ | |
632 | for (i = 0; i < 16; i++) | |
633 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
634 | ||
635 | return res; | |
636 | } | |
637 | ||
638 | /* | |
639 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
640 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
641 | * two above functions to compress/expand the bits | |
642 | */ | |
83215812 AP |
643 | bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, |
644 | phys_addr_t offset) | |
b47ef92a MZ |
645 | { |
646 | u32 val; | |
6545eae3 | 647 | |
f2ae85b2 | 648 | if (offset & 4) |
b47ef92a MZ |
649 | val = *reg >> 16; |
650 | else | |
651 | val = *reg & 0xffff; | |
652 | ||
653 | val = vgic_cfg_expand(val); | |
654 | vgic_reg_access(mmio, &val, offset, | |
655 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
656 | if (mmio->is_write) { | |
f2ae85b2 | 657 | if (offset < 8) { |
b47ef92a MZ |
658 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
659 | return false; | |
660 | } | |
661 | ||
662 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 663 | if (offset & 4) { |
b47ef92a MZ |
664 | *reg &= 0xffff; |
665 | *reg |= val << 16; | |
666 | } else { | |
667 | *reg &= 0xffff << 16; | |
668 | *reg |= val; | |
669 | } | |
670 | } | |
671 | ||
672 | return false; | |
673 | } | |
674 | ||
cbd333a4 | 675 | /** |
47a98b15 | 676 | * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor |
cbd333a4 CD |
677 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs |
678 | * | |
47a98b15 | 679 | * Move any IRQs that have already been assigned to LRs back to the |
cbd333a4 CD |
680 | * emulated distributor state so that the complete emulated state can be read |
681 | * from the main emulation structures without investigating the LRs. | |
cbd333a4 | 682 | */ |
83215812 | 683 | void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) |
cbd333a4 | 684 | { |
cbd333a4 | 685 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
8d5c6b06 | 686 | int i; |
cbd333a4 CD |
687 | |
688 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 689 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
690 | |
691 | /* | |
692 | * There are three options for the state bits: | |
693 | * | |
694 | * 01: pending | |
695 | * 10: active | |
696 | * 11: pending and active | |
cbd333a4 | 697 | */ |
47a98b15 CD |
698 | BUG_ON(!(lr.state & LR_STATE_MASK)); |
699 | ||
700 | /* Reestablish SGI source for pending and active IRQs */ | |
701 | if (lr.irq < VGIC_NR_SGIS) | |
702 | add_sgi_source(vcpu, lr.irq, lr.source); | |
703 | ||
704 | /* | |
705 | * If the LR holds an active (10) or a pending and active (11) | |
706 | * interrupt then move the active state to the | |
707 | * distributor tracking bit. | |
708 | */ | |
709 | if (lr.state & LR_STATE_ACTIVE) { | |
710 | vgic_irq_set_active(vcpu, lr.irq); | |
711 | lr.state &= ~LR_STATE_ACTIVE; | |
712 | } | |
cbd333a4 CD |
713 | |
714 | /* | |
715 | * Reestablish the pending state on the distributor and the | |
716 | * CPU interface. It may have already been pending, but that | |
717 | * is fine, then we are only setting a few bits that were | |
718 | * already set. | |
719 | */ | |
47a98b15 CD |
720 | if (lr.state & LR_STATE_PENDING) { |
721 | vgic_dist_irq_set_pending(vcpu, lr.irq); | |
722 | lr.state &= ~LR_STATE_PENDING; | |
723 | } | |
724 | ||
8d5c6b06 | 725 | vgic_set_lr(vcpu, i, lr); |
cbd333a4 CD |
726 | |
727 | /* | |
47a98b15 | 728 | * Mark the LR as free for other use. |
cbd333a4 | 729 | */ |
47a98b15 CD |
730 | BUG_ON(lr.state & LR_STATE_MASK); |
731 | vgic_retire_lr(i, lr.irq, vcpu); | |
732 | vgic_irq_clear_queued(vcpu, lr.irq); | |
cbd333a4 CD |
733 | |
734 | /* Finally update the VGIC state. */ | |
735 | vgic_update_state(vcpu->kvm); | |
736 | } | |
737 | } | |
738 | ||
83215812 | 739 | const |
cf50a1eb | 740 | struct vgic_io_range *vgic_find_range(const struct vgic_io_range *ranges, |
9f199d0a | 741 | int len, gpa_t offset) |
1a89dd91 | 742 | { |
9f199d0a AP |
743 | while (ranges->len) { |
744 | if (offset >= ranges->base && | |
745 | (offset + len) <= (ranges->base + ranges->len)) | |
746 | return ranges; | |
747 | ranges++; | |
1a89dd91 MZ |
748 | } |
749 | ||
750 | return NULL; | |
751 | } | |
752 | ||
c3c91836 | 753 | static bool vgic_validate_access(const struct vgic_dist *dist, |
cf50a1eb | 754 | const struct vgic_io_range *range, |
c3c91836 MZ |
755 | unsigned long offset) |
756 | { | |
757 | int irq; | |
758 | ||
759 | if (!range->bits_per_irq) | |
760 | return true; /* Not an irq-based access */ | |
761 | ||
762 | irq = offset * 8 / range->bits_per_irq; | |
763 | if (irq >= dist->nr_irqs) | |
764 | return false; | |
765 | ||
766 | return true; | |
767 | } | |
768 | ||
05bc8aaf AP |
769 | /* |
770 | * Call the respective handler function for the given range. | |
771 | * We split up any 64 bit accesses into two consecutive 32 bit | |
772 | * handler calls and merge the result afterwards. | |
773 | * We do this in a little endian fashion regardless of the host's | |
774 | * or guest's endianness, because the GIC is always LE and the rest of | |
775 | * the code (vgic_reg_access) also puts it in a LE fashion already. | |
776 | * At this point we have already identified the handle function, so | |
777 | * range points to that one entry and offset is relative to this. | |
778 | */ | |
779 | static bool call_range_handler(struct kvm_vcpu *vcpu, | |
780 | struct kvm_exit_mmio *mmio, | |
781 | unsigned long offset, | |
cf50a1eb | 782 | const struct vgic_io_range *range) |
05bc8aaf | 783 | { |
05bc8aaf AP |
784 | struct kvm_exit_mmio mmio32; |
785 | bool ret; | |
786 | ||
787 | if (likely(mmio->len <= 4)) | |
788 | return range->handle_mmio(vcpu, mmio, offset); | |
789 | ||
790 | /* | |
791 | * Any access bigger than 4 bytes (that we currently handle in KVM) | |
792 | * is actually 8 bytes long, caused by a 64-bit access | |
793 | */ | |
794 | ||
795 | mmio32.len = 4; | |
796 | mmio32.is_write = mmio->is_write; | |
9fedf146 | 797 | mmio32.private = mmio->private; |
05bc8aaf AP |
798 | |
799 | mmio32.phys_addr = mmio->phys_addr + 4; | |
950324ab | 800 | mmio32.data = &((u32 *)mmio->data)[1]; |
05bc8aaf | 801 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); |
05bc8aaf AP |
802 | |
803 | mmio32.phys_addr = mmio->phys_addr; | |
950324ab | 804 | mmio32.data = &((u32 *)mmio->data)[0]; |
05bc8aaf | 805 | ret |= range->handle_mmio(vcpu, &mmio32, offset); |
05bc8aaf AP |
806 | |
807 | return ret; | |
808 | } | |
809 | ||
1a89dd91 | 810 | /** |
6777f77f AP |
811 | * vgic_handle_mmio_access - handle an in-kernel MMIO access |
812 | * This is called by the read/write KVM IO device wrappers below. | |
1a89dd91 | 813 | * @vcpu: pointer to the vcpu performing the access |
6777f77f AP |
814 | * @this: pointer to the KVM IO device in charge |
815 | * @addr: guest physical address of the access | |
816 | * @len: size of the access | |
817 | * @val: pointer to the data region | |
818 | * @is_write: read or write access | |
1a89dd91 | 819 | * |
96415257 | 820 | * returns true if the MMIO access could be performed |
1a89dd91 | 821 | */ |
6777f77f AP |
822 | static int vgic_handle_mmio_access(struct kvm_vcpu *vcpu, |
823 | struct kvm_io_device *this, gpa_t addr, | |
824 | int len, void *val, bool is_write) | |
1a89dd91 | 825 | { |
b47ef92a | 826 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
6777f77f AP |
827 | struct vgic_io_device *iodev = container_of(this, |
828 | struct vgic_io_device, dev); | |
829 | struct kvm_run *run = vcpu->run; | |
830 | const struct vgic_io_range *range; | |
831 | struct kvm_exit_mmio mmio; | |
b47ef92a | 832 | bool updated_state; |
6777f77f | 833 | gpa_t offset; |
b47ef92a | 834 | |
6777f77f AP |
835 | offset = addr - iodev->addr; |
836 | range = vgic_find_range(iodev->reg_ranges, len, offset); | |
b47ef92a | 837 | if (unlikely(!range || !range->handle_mmio)) { |
6777f77f AP |
838 | pr_warn("Unhandled access %d %08llx %d\n", is_write, addr, len); |
839 | return -ENXIO; | |
b47ef92a MZ |
840 | } |
841 | ||
6777f77f AP |
842 | mmio.phys_addr = addr; |
843 | mmio.len = len; | |
844 | mmio.is_write = is_write; | |
950324ab | 845 | mmio.data = val; |
6777f77f AP |
846 | mmio.private = iodev->redist_vcpu; |
847 | ||
848 | spin_lock(&dist->lock); | |
96415257 | 849 | offset -= range->base; |
c3c91836 | 850 | if (vgic_validate_access(dist, range, offset)) { |
6777f77f | 851 | updated_state = call_range_handler(vcpu, &mmio, offset, range); |
c3c91836 | 852 | } else { |
6777f77f AP |
853 | if (!is_write) |
854 | memset(val, 0, len); | |
c3c91836 MZ |
855 | updated_state = false; |
856 | } | |
6777f77f | 857 | spin_unlock(&dist->lock); |
950324ab AP |
858 | run->mmio.is_write = is_write; |
859 | run->mmio.len = len; | |
860 | run->mmio.phys_addr = addr; | |
861 | memcpy(run->mmio.data, val, len); | |
862 | ||
b47ef92a MZ |
863 | kvm_handle_mmio_return(vcpu, run); |
864 | ||
5863c2ce MZ |
865 | if (updated_state) |
866 | vgic_kick_vcpus(vcpu->kvm); | |
867 | ||
6777f77f AP |
868 | return 0; |
869 | } | |
870 | ||
6777f77f AP |
871 | static int vgic_handle_mmio_read(struct kvm_vcpu *vcpu, |
872 | struct kvm_io_device *this, | |
873 | gpa_t addr, int len, void *val) | |
874 | { | |
875 | return vgic_handle_mmio_access(vcpu, this, addr, len, val, false); | |
b47ef92a MZ |
876 | } |
877 | ||
6777f77f AP |
878 | static int vgic_handle_mmio_write(struct kvm_vcpu *vcpu, |
879 | struct kvm_io_device *this, | |
880 | gpa_t addr, int len, const void *val) | |
881 | { | |
882 | return vgic_handle_mmio_access(vcpu, this, addr, len, (void *)val, | |
883 | true); | |
884 | } | |
885 | ||
886 | struct kvm_io_device_ops vgic_io_ops = { | |
887 | .read = vgic_handle_mmio_read, | |
888 | .write = vgic_handle_mmio_write, | |
889 | }; | |
890 | ||
96415257 | 891 | /** |
6777f77f AP |
892 | * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus |
893 | * @kvm: The VM structure pointer | |
894 | * @base: The (guest) base address for the register frame | |
895 | * @len: Length of the register frame window | |
896 | * @ranges: Describing the handler functions for each register | |
897 | * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call | |
898 | * @iodev: Points to memory to be passed on to the handler | |
96415257 | 899 | * |
6777f77f AP |
900 | * @iodev stores the parameters of this function to be usable by the handler |
901 | * respectively the dispatcher function (since the KVM I/O bus framework lacks | |
902 | * an opaque parameter). Initialization is done in this function, but the | |
903 | * reference should be valid and unique for the whole VGIC lifetime. | |
904 | * If the register frame is not mapped for a specific VCPU, pass -1 to | |
905 | * @redist_vcpu_id. | |
96415257 | 906 | */ |
6777f77f AP |
907 | int vgic_register_kvm_io_dev(struct kvm *kvm, gpa_t base, int len, |
908 | const struct vgic_io_range *ranges, | |
909 | int redist_vcpu_id, | |
910 | struct vgic_io_device *iodev) | |
96415257 | 911 | { |
6777f77f AP |
912 | struct kvm_vcpu *vcpu = NULL; |
913 | int ret; | |
96415257 | 914 | |
6777f77f AP |
915 | if (redist_vcpu_id >= 0) |
916 | vcpu = kvm_get_vcpu(kvm, redist_vcpu_id); | |
917 | ||
918 | iodev->addr = base; | |
919 | iodev->len = len; | |
920 | iodev->reg_ranges = ranges; | |
921 | iodev->redist_vcpu = vcpu; | |
922 | ||
923 | kvm_iodevice_init(&iodev->dev, &vgic_io_ops); | |
924 | ||
925 | mutex_lock(&kvm->slots_lock); | |
926 | ||
927 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, base, len, | |
928 | &iodev->dev); | |
929 | mutex_unlock(&kvm->slots_lock); | |
930 | ||
931 | /* Mark the iodev as invalid if registration fails. */ | |
932 | if (ret) | |
933 | iodev->dev.ops = NULL; | |
934 | ||
935 | return ret; | |
96415257 AP |
936 | } |
937 | ||
fb65ab63 MZ |
938 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
939 | { | |
940 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
941 | } | |
942 | ||
47a98b15 CD |
943 | static int compute_active_for_cpu(struct kvm_vcpu *vcpu) |
944 | { | |
945 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
946 | unsigned long *active, *enabled, *act_percpu, *act_shared; | |
947 | unsigned long active_private, active_shared; | |
948 | int nr_shared = vgic_nr_shared_irqs(dist); | |
949 | int vcpu_id; | |
950 | ||
951 | vcpu_id = vcpu->vcpu_id; | |
952 | act_percpu = vcpu->arch.vgic_cpu.active_percpu; | |
953 | act_shared = vcpu->arch.vgic_cpu.active_shared; | |
954 | ||
955 | active = vgic_bitmap_get_cpu_map(&dist->irq_active, vcpu_id); | |
956 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); | |
957 | bitmap_and(act_percpu, active, enabled, VGIC_NR_PRIVATE_IRQS); | |
958 | ||
959 | active = vgic_bitmap_get_shared_map(&dist->irq_active); | |
960 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); | |
961 | bitmap_and(act_shared, active, enabled, nr_shared); | |
962 | bitmap_and(act_shared, act_shared, | |
963 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
964 | nr_shared); | |
965 | ||
966 | active_private = find_first_bit(act_percpu, VGIC_NR_PRIVATE_IRQS); | |
967 | active_shared = find_first_bit(act_shared, nr_shared); | |
968 | ||
969 | return (active_private < VGIC_NR_PRIVATE_IRQS || | |
970 | active_shared < nr_shared); | |
971 | } | |
972 | ||
b47ef92a MZ |
973 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
974 | { | |
9d949dce MZ |
975 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
976 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
977 | unsigned long pending_private, pending_shared; | |
fb65ab63 | 978 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
979 | int vcpu_id; |
980 | ||
981 | vcpu_id = vcpu->vcpu_id; | |
982 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
983 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
984 | ||
227844f5 | 985 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
986 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
987 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
988 | ||
227844f5 | 989 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce | 990 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
fb65ab63 | 991 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
9d949dce MZ |
992 | bitmap_and(pend_shared, pend_shared, |
993 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
fb65ab63 | 994 | nr_shared); |
9d949dce MZ |
995 | |
996 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
fb65ab63 | 997 | pending_shared = find_first_bit(pend_shared, nr_shared); |
9d949dce | 998 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
fb65ab63 | 999 | pending_shared < vgic_nr_shared_irqs(dist)); |
b47ef92a MZ |
1000 | } |
1001 | ||
1002 | /* | |
1003 | * Update the interrupt state and determine which CPUs have pending | |
47a98b15 | 1004 | * or active interrupts. Must be called with distributor lock held. |
b47ef92a | 1005 | */ |
83215812 | 1006 | void vgic_update_state(struct kvm *kvm) |
b47ef92a MZ |
1007 | { |
1008 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1009 | struct kvm_vcpu *vcpu; | |
1010 | int c; | |
1011 | ||
1012 | if (!dist->enabled) { | |
c1bfb577 | 1013 | set_bit(0, dist->irq_pending_on_cpu); |
b47ef92a MZ |
1014 | return; |
1015 | } | |
1016 | ||
1017 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
47a98b15 | 1018 | if (compute_pending_for_cpu(vcpu)) |
c1bfb577 | 1019 | set_bit(c, dist->irq_pending_on_cpu); |
47a98b15 CD |
1020 | |
1021 | if (compute_active_for_cpu(vcpu)) | |
1022 | set_bit(c, dist->irq_active_on_cpu); | |
1023 | else | |
1024 | clear_bit(c, dist->irq_active_on_cpu); | |
b47ef92a | 1025 | } |
1a89dd91 | 1026 | } |
330690cd | 1027 | |
8d5c6b06 MZ |
1028 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
1029 | { | |
8f186d52 | 1030 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
1031 | } |
1032 | ||
1033 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
1034 | struct vgic_lr vlr) | |
1035 | { | |
8f186d52 | 1036 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
1037 | } |
1038 | ||
69bb2c9f MZ |
1039 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
1040 | struct vgic_lr vlr) | |
1041 | { | |
8f186d52 | 1042 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
1043 | } |
1044 | ||
1045 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
1046 | { | |
8f186d52 | 1047 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
1048 | } |
1049 | ||
8d6a0313 MZ |
1050 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
1051 | { | |
8f186d52 | 1052 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1053 | } |
1054 | ||
ae705930 CD |
1055 | static inline void vgic_clear_eisr(struct kvm_vcpu *vcpu) |
1056 | { | |
1057 | vgic_ops->clear_eisr(vcpu); | |
1058 | } | |
1059 | ||
495dd859 MZ |
1060 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1061 | { | |
8f186d52 | 1062 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1063 | } |
1064 | ||
909d9b50 MZ |
1065 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1066 | { | |
8f186d52 | 1067 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1068 | } |
1069 | ||
1070 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1071 | { | |
8f186d52 | 1072 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1073 | } |
1074 | ||
83215812 | 1075 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 1076 | { |
8f186d52 | 1077 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1078 | } |
1079 | ||
83215812 | 1080 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 1081 | { |
8f186d52 | 1082 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1083 | } |
1084 | ||
da8dafd1 MZ |
1085 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1086 | { | |
8f186d52 | 1087 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1088 | } |
1089 | ||
8d5c6b06 MZ |
1090 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1091 | { | |
1092 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1093 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1094 | ||
1095 | vlr.state = 0; | |
1096 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1097 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1098 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
ae705930 | 1099 | vgic_sync_lr_elrsr(vcpu, lr_nr, vlr); |
8d5c6b06 | 1100 | } |
a1fcb44e MZ |
1101 | |
1102 | /* | |
1103 | * An interrupt may have been disabled after being made pending on the | |
1104 | * CPU interface (the classic case is a timer running while we're | |
1105 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1106 | * interface gets enabled, with deadly consequences). | |
1107 | * | |
1108 | * The solution is to examine already active LRs, and check the | |
1109 | * interrupt is still enabled. If not, just retire it. | |
1110 | */ | |
1111 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1112 | { | |
1113 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1114 | int lr; | |
1115 | ||
8f186d52 | 1116 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1117 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1118 | |
8d5c6b06 MZ |
1119 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1120 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1121 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1122 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1123 | } |
1124 | } | |
1125 | } | |
1126 | ||
71760950 AB |
1127 | static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, |
1128 | int lr_nr, struct vgic_lr vlr) | |
1129 | { | |
47a98b15 CD |
1130 | if (vgic_irq_is_active(vcpu, irq)) { |
1131 | vlr.state |= LR_STATE_ACTIVE; | |
1132 | kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state); | |
1133 | vgic_irq_clear_active(vcpu, irq); | |
1134 | vgic_update_state(vcpu->kvm); | |
1135 | } else if (vgic_dist_irq_is_pending(vcpu, irq)) { | |
71760950 AB |
1136 | vlr.state |= LR_STATE_PENDING; |
1137 | kvm_debug("Set pending: 0x%x\n", vlr.state); | |
1138 | } | |
1139 | ||
1140 | if (!vgic_irq_is_edge(vcpu, irq)) | |
1141 | vlr.state |= LR_EOI_INT; | |
1142 | ||
08fd6461 MZ |
1143 | if (vlr.irq >= VGIC_NR_SGIS) { |
1144 | struct irq_phys_map *map; | |
1145 | map = vgic_irq_map_search(vcpu, irq); | |
1146 | ||
08fd6461 | 1147 | if (map) { |
08fd6461 MZ |
1148 | vlr.hwirq = map->phys_irq; |
1149 | vlr.state |= LR_HW; | |
1150 | vlr.state &= ~LR_EOI_INT; | |
1151 | ||
08fd6461 MZ |
1152 | /* |
1153 | * Make sure we're not going to sample this | |
1154 | * again, as a HW-backed interrupt cannot be | |
1155 | * in the PENDING_ACTIVE stage. | |
1156 | */ | |
1157 | vgic_irq_set_queued(vcpu, irq); | |
1158 | } | |
1159 | } | |
1160 | ||
71760950 | 1161 | vgic_set_lr(vcpu, lr_nr, vlr); |
bf0fb67c | 1162 | vgic_sync_lr_elrsr(vcpu, lr_nr, vlr); |
71760950 AB |
1163 | } |
1164 | ||
9d949dce MZ |
1165 | /* |
1166 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1167 | * or false if it wasn't possible to queue it. | |
1d916229 | 1168 | * sgi_source must be zero for any non-SGI interrupts. |
9d949dce | 1169 | */ |
83215812 | 1170 | bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) |
9d949dce MZ |
1171 | { |
1172 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
5fb66da6 | 1173 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
8d5c6b06 | 1174 | struct vgic_lr vlr; |
9d949dce MZ |
1175 | int lr; |
1176 | ||
1177 | /* Sanitize the input... */ | |
1178 | BUG_ON(sgi_source_id & ~7); | |
1179 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
5fb66da6 | 1180 | BUG_ON(irq >= dist->nr_irqs); |
9d949dce MZ |
1181 | |
1182 | kvm_debug("Queue IRQ%d\n", irq); | |
1183 | ||
1184 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1185 | ||
1186 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1187 | if (lr != LR_EMPTY) { |
1188 | vlr = vgic_get_lr(vcpu, lr); | |
1189 | if (vlr.source == sgi_source_id) { | |
1190 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1191 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
71760950 | 1192 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); |
8d5c6b06 MZ |
1193 | return true; |
1194 | } | |
9d949dce MZ |
1195 | } |
1196 | ||
1197 | /* Try to use another LR for this interrupt */ | |
1198 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1199 | vgic->nr_lr); |
1200 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1201 | return false; |
1202 | ||
1203 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1204 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1205 | set_bit(lr, vgic_cpu->lr_used); | |
1206 | ||
8d5c6b06 MZ |
1207 | vlr.irq = irq; |
1208 | vlr.source = sgi_source_id; | |
71760950 AB |
1209 | vlr.state = 0; |
1210 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); | |
9d949dce MZ |
1211 | |
1212 | return true; | |
1213 | } | |
1214 | ||
9d949dce MZ |
1215 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) |
1216 | { | |
dbf20f9d | 1217 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1218 | return true; /* level interrupt, already queued */ |
1219 | ||
1220 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1221 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1222 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1223 | vgic_cpu_irq_clear(vcpu, irq); |
1224 | } else { | |
dbf20f9d | 1225 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1226 | } |
1227 | ||
1228 | return true; | |
1229 | } | |
1230 | ||
1231 | return false; | |
1232 | } | |
1233 | ||
1234 | /* | |
1235 | * Fill the list registers with pending interrupts before running the | |
1236 | * guest. | |
1237 | */ | |
1238 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1239 | { | |
1240 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1241 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
47a98b15 | 1242 | unsigned long *pa_percpu, *pa_shared; |
04bdfa8a | 1243 | int i, vcpu_id, lr, ret; |
9d949dce | 1244 | int overflow = 0; |
47a98b15 | 1245 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
1246 | |
1247 | vcpu_id = vcpu->vcpu_id; | |
1248 | ||
47a98b15 CD |
1249 | pa_percpu = vcpu->arch.vgic_cpu.pend_act_percpu; |
1250 | pa_shared = vcpu->arch.vgic_cpu.pend_act_shared; | |
1251 | ||
1252 | bitmap_or(pa_percpu, vgic_cpu->pending_percpu, vgic_cpu->active_percpu, | |
1253 | VGIC_NR_PRIVATE_IRQS); | |
1254 | bitmap_or(pa_shared, vgic_cpu->pending_shared, vgic_cpu->active_shared, | |
1255 | nr_shared); | |
9d949dce MZ |
1256 | /* |
1257 | * We may not have any pending interrupt, or the interrupts | |
1258 | * may have been serviced from another vcpu. In all cases, | |
1259 | * move along. | |
1260 | */ | |
47a98b15 | 1261 | if (!kvm_vgic_vcpu_pending_irq(vcpu) && !kvm_vgic_vcpu_active_irq(vcpu)) |
9d949dce | 1262 | goto epilog; |
9d949dce MZ |
1263 | |
1264 | /* SGIs */ | |
47a98b15 | 1265 | for_each_set_bit(i, pa_percpu, VGIC_NR_SGIS) { |
b26e5fda | 1266 | if (!queue_sgi(vcpu, i)) |
9d949dce MZ |
1267 | overflow = 1; |
1268 | } | |
1269 | ||
1270 | /* PPIs */ | |
47a98b15 | 1271 | for_each_set_bit_from(i, pa_percpu, VGIC_NR_PRIVATE_IRQS) { |
9d949dce MZ |
1272 | if (!vgic_queue_hwirq(vcpu, i)) |
1273 | overflow = 1; | |
1274 | } | |
1275 | ||
1276 | /* SPIs */ | |
47a98b15 | 1277 | for_each_set_bit(i, pa_shared, nr_shared) { |
9d949dce MZ |
1278 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
1279 | overflow = 1; | |
1280 | } | |
1281 | ||
47a98b15 CD |
1282 | |
1283 | ||
1284 | ||
9d949dce MZ |
1285 | epilog: |
1286 | if (overflow) { | |
909d9b50 | 1287 | vgic_enable_underflow(vcpu); |
9d949dce | 1288 | } else { |
909d9b50 | 1289 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1290 | /* |
1291 | * We're about to run this VCPU, and we've consumed | |
1292 | * everything the distributor had in store for | |
1293 | * us. Claim we don't have anything pending. We'll | |
1294 | * adjust that if needed while exiting. | |
1295 | */ | |
c1bfb577 | 1296 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
9d949dce | 1297 | } |
04bdfa8a CD |
1298 | |
1299 | for (lr = 0; lr < vgic->nr_lr; lr++) { | |
1300 | struct vgic_lr vlr; | |
1301 | ||
1302 | if (!test_bit(lr, vgic_cpu->lr_used)) | |
1303 | continue; | |
1304 | ||
1305 | vlr = vgic_get_lr(vcpu, lr); | |
1306 | ||
1307 | /* | |
1308 | * If we have a mapping, and the virtual interrupt is | |
1309 | * presented to the guest (as pending or active), then we must | |
1310 | * set the state to active in the physical world. See | |
1311 | * Documentation/virtual/kvm/arm/vgic-mapped-irqs.txt. | |
1312 | */ | |
1313 | if (vlr.state & LR_HW) { | |
1314 | struct irq_phys_map *map; | |
1315 | map = vgic_irq_map_search(vcpu, vlr.irq); | |
1316 | ||
1317 | ret = irq_set_irqchip_state(map->irq, | |
1318 | IRQCHIP_STATE_ACTIVE, | |
1319 | true); | |
1320 | WARN_ON(ret); | |
1321 | } | |
1322 | } | |
9d949dce MZ |
1323 | } |
1324 | ||
1325 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1326 | { | |
495dd859 | 1327 | u32 status = vgic_get_interrupt_status(vcpu); |
649cf739 | 1328 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
9d949dce | 1329 | bool level_pending = false; |
174178fe | 1330 | struct kvm *kvm = vcpu->kvm; |
9d949dce | 1331 | |
495dd859 | 1332 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1333 | |
495dd859 | 1334 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1335 | /* |
1336 | * Some level interrupts have been EOIed. Clear their | |
1337 | * active bit. | |
1338 | */ | |
8d6a0313 | 1339 | u64 eisr = vgic_get_eisr(vcpu); |
2df36a5d | 1340 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
8d5c6b06 | 1341 | int lr; |
9d949dce | 1342 | |
8f186d52 | 1343 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1344 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1345 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1346 | |
649cf739 | 1347 | spin_lock(&dist->lock); |
dbf20f9d | 1348 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1349 | WARN_ON(vlr.state & LR_STATE_MASK); |
1350 | vlr.state = 0; | |
1351 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1352 | |
faa1b46c CD |
1353 | /* |
1354 | * If the IRQ was EOIed it was also ACKed and we we | |
1355 | * therefore assume we can clear the soft pending | |
1356 | * state (should it had been set) for this interrupt. | |
1357 | * | |
1358 | * Note: if the IRQ soft pending state was set after | |
1359 | * the IRQ was acked, it actually shouldn't be | |
1360 | * cleared, but we have no way of knowing that unless | |
1361 | * we start trapping ACKs when the soft-pending state | |
1362 | * is set. | |
1363 | */ | |
1364 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1365 | ||
174178fe EA |
1366 | /* |
1367 | * kvm_notify_acked_irq calls kvm_set_irq() | |
1368 | * to reset the IRQ level. Need to release the | |
1369 | * lock for kvm_set_irq to grab it. | |
1370 | */ | |
1371 | spin_unlock(&dist->lock); | |
1372 | ||
1373 | kvm_notify_acked_irq(kvm, 0, | |
1374 | vlr.irq - VGIC_NR_PRIVATE_IRQS); | |
1375 | spin_lock(&dist->lock); | |
1376 | ||
9d949dce | 1377 | /* Any additional pending interrupt? */ |
faa1b46c | 1378 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1379 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1380 | level_pending = true; |
1381 | } else { | |
faa1b46c | 1382 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1383 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1384 | } |
75da01e1 | 1385 | |
649cf739 EA |
1386 | spin_unlock(&dist->lock); |
1387 | ||
75da01e1 MZ |
1388 | /* |
1389 | * Despite being EOIed, the LR may not have | |
1390 | * been marked as empty. | |
1391 | */ | |
69bb2c9f | 1392 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1393 | } |
1394 | } | |
1395 | ||
495dd859 | 1396 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1397 | vgic_disable_underflow(vcpu); |
9d949dce | 1398 | |
ae705930 CD |
1399 | /* |
1400 | * In the next iterations of the vcpu loop, if we sync the vgic state | |
1401 | * after flushing it, but before entering the guest (this happens for | |
1402 | * pending signals and vmid rollovers), then make sure we don't pick | |
1403 | * up any old maintenance interrupts here. | |
1404 | */ | |
1405 | vgic_clear_eisr(vcpu); | |
1406 | ||
9d949dce MZ |
1407 | return level_pending; |
1408 | } | |
1409 | ||
08fd6461 MZ |
1410 | /* |
1411 | * Save the physical active state, and reset it to inactive. | |
1412 | * | |
1413 | * Return 1 if HW interrupt went from active to inactive, and 0 otherwise. | |
1414 | */ | |
1415 | static int vgic_sync_hwirq(struct kvm_vcpu *vcpu, struct vgic_lr vlr) | |
1416 | { | |
1417 | struct irq_phys_map *map; | |
1418 | int ret; | |
1419 | ||
1420 | if (!(vlr.state & LR_HW)) | |
1421 | return 0; | |
1422 | ||
1423 | map = vgic_irq_map_search(vcpu, vlr.irq); | |
1424 | BUG_ON(!map || !map->active); | |
1425 | ||
1426 | ret = irq_get_irqchip_state(map->irq, | |
1427 | IRQCHIP_STATE_ACTIVE, | |
1428 | &map->active); | |
1429 | ||
1430 | WARN_ON(ret); | |
1431 | ||
1432 | if (map->active) { | |
1433 | ret = irq_set_irqchip_state(map->irq, | |
1434 | IRQCHIP_STATE_ACTIVE, | |
1435 | false); | |
1436 | WARN_ON(ret); | |
1437 | return 0; | |
1438 | } | |
1439 | ||
1440 | return 1; | |
1441 | } | |
1442 | ||
649cf739 | 1443 | /* Sync back the VGIC state after a guest run */ |
9d949dce MZ |
1444 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
1445 | { | |
1446 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1447 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1448 | u64 elrsr; |
1449 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1450 | int lr, pending; |
1451 | bool level_pending; | |
1452 | ||
1453 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f | 1454 | elrsr = vgic_get_elrsr(vcpu); |
2df36a5d | 1455 | elrsr_ptr = u64_to_bitmask(&elrsr); |
9d949dce | 1456 | |
08fd6461 MZ |
1457 | /* Deal with HW interrupts, and clear mappings for empty LRs */ |
1458 | for (lr = 0; lr < vgic->nr_lr; lr++) { | |
8d5c6b06 | 1459 | struct vgic_lr vlr; |
9d949dce | 1460 | |
08fd6461 | 1461 | if (!test_bit(lr, vgic_cpu->lr_used)) |
9d949dce MZ |
1462 | continue; |
1463 | ||
8d5c6b06 | 1464 | vlr = vgic_get_lr(vcpu, lr); |
08fd6461 MZ |
1465 | if (vgic_sync_hwirq(vcpu, vlr)) { |
1466 | /* | |
1467 | * So this is a HW interrupt that the guest | |
1468 | * EOI-ed. Clean the LR state and allow the | |
1469 | * interrupt to be sampled again. | |
1470 | */ | |
1471 | vlr.state = 0; | |
1472 | vlr.hwirq = 0; | |
1473 | vgic_set_lr(vcpu, lr, vlr); | |
1474 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
1475 | set_bit(lr, elrsr_ptr); | |
1476 | } | |
1477 | ||
1478 | if (!test_bit(lr, elrsr_ptr)) | |
1479 | continue; | |
1480 | ||
1481 | clear_bit(lr, vgic_cpu->lr_used); | |
9d949dce | 1482 | |
5fb66da6 | 1483 | BUG_ON(vlr.irq >= dist->nr_irqs); |
8d5c6b06 | 1484 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
9d949dce MZ |
1485 | } |
1486 | ||
1487 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1488 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1489 | if (level_pending || pending < vgic->nr_lr) | |
c1bfb577 | 1490 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1491 | } |
1492 | ||
1493 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1494 | { | |
1495 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1496 | ||
1497 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1498 | return; | |
1499 | ||
1500 | spin_lock(&dist->lock); | |
1501 | __kvm_vgic_flush_hwstate(vcpu); | |
1502 | spin_unlock(&dist->lock); | |
1503 | } | |
1504 | ||
1505 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1506 | { | |
1507 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1508 | return; | |
1509 | ||
1510 | __kvm_vgic_sync_hwstate(vcpu); | |
1511 | } | |
1512 | ||
1513 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1514 | { | |
1515 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1516 | ||
1517 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1518 | return 0; | |
1519 | ||
c1bfb577 | 1520 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1521 | } |
1522 | ||
47a98b15 CD |
1523 | int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu) |
1524 | { | |
1525 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1526 | ||
1527 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1528 | return 0; | |
1529 | ||
1530 | return test_bit(vcpu->vcpu_id, dist->irq_active_on_cpu); | |
1531 | } | |
1532 | ||
1533 | ||
83215812 | 1534 | void vgic_kick_vcpus(struct kvm *kvm) |
5863c2ce MZ |
1535 | { |
1536 | struct kvm_vcpu *vcpu; | |
1537 | int c; | |
1538 | ||
1539 | /* | |
1540 | * We've injected an interrupt, time to find out who deserves | |
1541 | * a good kick... | |
1542 | */ | |
1543 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1544 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1545 | kvm_vcpu_kick(vcpu); | |
1546 | } | |
1547 | } | |
1548 | ||
1549 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1550 | { | |
227844f5 | 1551 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1552 | |
1553 | /* | |
1554 | * Only inject an interrupt if: | |
1555 | * - edge triggered and we have a rising edge | |
1556 | * - level triggered and we change level | |
1557 | */ | |
faa1b46c CD |
1558 | if (edge_triggered) { |
1559 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1560 | return level > state; |
faa1b46c CD |
1561 | } else { |
1562 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1563 | return level != state; |
faa1b46c | 1564 | } |
5863c2ce MZ |
1565 | } |
1566 | ||
016ed39c | 1567 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
773299a5 MZ |
1568 | struct irq_phys_map *map, |
1569 | unsigned int irq_num, bool level) | |
5863c2ce MZ |
1570 | { |
1571 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1572 | struct kvm_vcpu *vcpu; | |
227844f5 | 1573 | int edge_triggered, level_triggered; |
5863c2ce | 1574 | int enabled; |
a0675c25 | 1575 | bool ret = true, can_inject = true; |
5863c2ce | 1576 | |
773299a5 MZ |
1577 | if (irq_num >= min(kvm->arch.vgic.nr_irqs, 1020)) |
1578 | return -EINVAL; | |
1579 | ||
5863c2ce MZ |
1580 | spin_lock(&dist->lock); |
1581 | ||
1582 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1583 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1584 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1585 | |
1586 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1587 | ret = false; | |
1588 | goto out; | |
1589 | } | |
1590 | ||
1591 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1592 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
a0675c25 AP |
1593 | if (cpuid == VCPU_NOT_ALLOCATED) { |
1594 | /* Pretend we use CPU0, and prevent injection */ | |
1595 | cpuid = 0; | |
1596 | can_inject = false; | |
1597 | } | |
5863c2ce MZ |
1598 | vcpu = kvm_get_vcpu(kvm, cpuid); |
1599 | } | |
1600 | ||
1601 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1602 | ||
faa1b46c CD |
1603 | if (level) { |
1604 | if (level_triggered) | |
1605 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1606 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1607 | } else { |
1608 | if (level_triggered) { | |
1609 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1610 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1611 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
faa1b46c | 1612 | } |
7d39f9e3 | 1613 | |
1614 | ret = false; | |
1615 | goto out; | |
faa1b46c | 1616 | } |
5863c2ce MZ |
1617 | |
1618 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1619 | ||
a0675c25 | 1620 | if (!enabled || !can_inject) { |
5863c2ce MZ |
1621 | ret = false; |
1622 | goto out; | |
1623 | } | |
1624 | ||
dbf20f9d | 1625 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1626 | /* |
1627 | * Level interrupt in progress, will be picked up | |
1628 | * when EOId. | |
1629 | */ | |
1630 | ret = false; | |
1631 | goto out; | |
1632 | } | |
1633 | ||
1634 | if (level) { | |
1635 | vgic_cpu_irq_set(vcpu, irq_num); | |
c1bfb577 | 1636 | set_bit(cpuid, dist->irq_pending_on_cpu); |
5863c2ce MZ |
1637 | } |
1638 | ||
1639 | out: | |
1640 | spin_unlock(&dist->lock); | |
1641 | ||
773299a5 MZ |
1642 | if (ret) { |
1643 | /* kick the specified vcpu */ | |
1644 | kvm_vcpu_kick(kvm_get_vcpu(kvm, cpuid)); | |
1645 | } | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | static int vgic_lazy_init(struct kvm *kvm) | |
1651 | { | |
1652 | int ret = 0; | |
1653 | ||
1654 | if (unlikely(!vgic_initialized(kvm))) { | |
1655 | /* | |
1656 | * We only provide the automatic initialization of the VGIC | |
1657 | * for the legacy case of a GICv2. Any other type must | |
1658 | * be explicitly initialized once setup with the respective | |
1659 | * KVM device call. | |
1660 | */ | |
1661 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) | |
1662 | return -EBUSY; | |
1663 | ||
1664 | mutex_lock(&kvm->lock); | |
1665 | ret = vgic_init(kvm); | |
1666 | mutex_unlock(&kvm->lock); | |
1667 | } | |
1668 | ||
1669 | return ret; | |
5863c2ce MZ |
1670 | } |
1671 | ||
1672 | /** | |
1673 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1674 | * @kvm: The VM structure pointer | |
1675 | * @cpuid: The CPU for PPIs | |
773299a5 MZ |
1676 | * @irq_num: The IRQ number that is assigned to the device. This IRQ |
1677 | * must not be mapped to a HW interrupt. | |
5863c2ce MZ |
1678 | * @level: Edge-triggered: true: to trigger the interrupt |
1679 | * false: to ignore the call | |
773299a5 MZ |
1680 | * Level-sensitive true: raise the input signal |
1681 | * false: lower the input signal | |
5863c2ce MZ |
1682 | * |
1683 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1684 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1685 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1686 | */ | |
1687 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1688 | bool level) | |
1689 | { | |
773299a5 MZ |
1690 | struct irq_phys_map *map; |
1691 | int ret; | |
ca7d9c82 | 1692 | |
773299a5 MZ |
1693 | ret = vgic_lazy_init(kvm); |
1694 | if (ret) | |
1695 | return ret; | |
5863c2ce | 1696 | |
773299a5 MZ |
1697 | map = vgic_irq_map_search(kvm_get_vcpu(kvm, cpuid), irq_num); |
1698 | if (map) | |
fd1d0ddf AP |
1699 | return -EINVAL; |
1700 | ||
773299a5 MZ |
1701 | return vgic_update_irq_pending(kvm, cpuid, NULL, irq_num, level); |
1702 | } | |
ca7d9c82 | 1703 | |
773299a5 MZ |
1704 | /** |
1705 | * kvm_vgic_inject_mapped_irq - Inject a physically mapped IRQ to the vgic | |
1706 | * @kvm: The VM structure pointer | |
1707 | * @cpuid: The CPU for PPIs | |
1708 | * @map: Pointer to a irq_phys_map structure describing the mapping | |
1709 | * @level: Edge-triggered: true: to trigger the interrupt | |
1710 | * false: to ignore the call | |
1711 | * Level-sensitive true: raise the input signal | |
1712 | * false: lower the input signal | |
1713 | * | |
1714 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1715 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1716 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1717 | */ | |
1718 | int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, | |
1719 | struct irq_phys_map *map, bool level) | |
1720 | { | |
1721 | int ret; | |
1722 | ||
1723 | ret = vgic_lazy_init(kvm); | |
1724 | if (ret) | |
1725 | return ret; | |
1726 | ||
1727 | return vgic_update_irq_pending(kvm, cpuid, map, map->virt_irq, level); | |
5863c2ce MZ |
1728 | } |
1729 | ||
01ac5e34 MZ |
1730 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1731 | { | |
1732 | /* | |
1733 | * We cannot rely on the vgic maintenance interrupt to be | |
1734 | * delivered synchronously. This means we can only use it to | |
1735 | * exit the VM, and we perform the handling of EOIed | |
1736 | * interrupts on the exit path (see vgic_process_maintenance). | |
1737 | */ | |
1738 | return IRQ_HANDLED; | |
1739 | } | |
1740 | ||
6c3d63c9 MZ |
1741 | static struct list_head *vgic_get_irq_phys_map_list(struct kvm_vcpu *vcpu, |
1742 | int virt_irq) | |
1743 | { | |
1744 | if (virt_irq < VGIC_NR_PRIVATE_IRQS) | |
1745 | return &vcpu->arch.vgic_cpu.irq_phys_map_list; | |
1746 | else | |
1747 | return &vcpu->kvm->arch.vgic.irq_phys_map_list; | |
1748 | } | |
1749 | ||
1750 | /** | |
1751 | * kvm_vgic_map_phys_irq - map a virtual IRQ to a physical IRQ | |
1752 | * @vcpu: The VCPU pointer | |
1753 | * @virt_irq: The virtual irq number | |
1754 | * @irq: The Linux IRQ number | |
1755 | * | |
1756 | * Establish a mapping between a guest visible irq (@virt_irq) and a | |
1757 | * Linux irq (@irq). On injection, @virt_irq will be associated with | |
1758 | * the physical interrupt represented by @irq. This mapping can be | |
1759 | * established multiple times as long as the parameters are the same. | |
1760 | * | |
1761 | * Returns a valid pointer on success, and an error pointer otherwise | |
1762 | */ | |
1763 | struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, | |
1764 | int virt_irq, int irq) | |
1765 | { | |
1766 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1767 | struct list_head *root = vgic_get_irq_phys_map_list(vcpu, virt_irq); | |
1768 | struct irq_phys_map *map; | |
1769 | struct irq_phys_map_entry *entry; | |
1770 | struct irq_desc *desc; | |
1771 | struct irq_data *data; | |
1772 | int phys_irq; | |
1773 | ||
1774 | desc = irq_to_desc(irq); | |
1775 | if (!desc) { | |
1776 | kvm_err("%s: no interrupt descriptor\n", __func__); | |
1777 | return ERR_PTR(-EINVAL); | |
1778 | } | |
1779 | ||
1780 | data = irq_desc_get_irq_data(desc); | |
1781 | while (data->parent_data) | |
1782 | data = data->parent_data; | |
1783 | ||
1784 | phys_irq = data->hwirq; | |
1785 | ||
1786 | /* Create a new mapping */ | |
1787 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); | |
1788 | if (!entry) | |
1789 | return ERR_PTR(-ENOMEM); | |
1790 | ||
1791 | spin_lock(&dist->irq_phys_map_lock); | |
1792 | ||
1793 | /* Try to match an existing mapping */ | |
1794 | map = vgic_irq_map_search(vcpu, virt_irq); | |
1795 | if (map) { | |
1796 | /* Make sure this mapping matches */ | |
1797 | if (map->phys_irq != phys_irq || | |
1798 | map->irq != irq) | |
1799 | map = ERR_PTR(-EINVAL); | |
1800 | ||
1801 | /* Found an existing, valid mapping */ | |
1802 | goto out; | |
1803 | } | |
1804 | ||
1805 | map = &entry->map; | |
1806 | map->virt_irq = virt_irq; | |
1807 | map->phys_irq = phys_irq; | |
1808 | map->irq = irq; | |
1809 | ||
1810 | list_add_tail_rcu(&entry->entry, root); | |
1811 | ||
1812 | out: | |
1813 | spin_unlock(&dist->irq_phys_map_lock); | |
1814 | /* If we've found a hit in the existing list, free the useless | |
1815 | * entry */ | |
1816 | if (IS_ERR(map) || map != &entry->map) | |
1817 | kfree(entry); | |
1818 | return map; | |
1819 | } | |
1820 | ||
1821 | static struct irq_phys_map *vgic_irq_map_search(struct kvm_vcpu *vcpu, | |
1822 | int virt_irq) | |
1823 | { | |
1824 | struct list_head *root = vgic_get_irq_phys_map_list(vcpu, virt_irq); | |
1825 | struct irq_phys_map_entry *entry; | |
1826 | struct irq_phys_map *map; | |
1827 | ||
1828 | rcu_read_lock(); | |
1829 | ||
1830 | list_for_each_entry_rcu(entry, root, entry) { | |
1831 | map = &entry->map; | |
1832 | if (map->virt_irq == virt_irq) { | |
1833 | rcu_read_unlock(); | |
1834 | return map; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | rcu_read_unlock(); | |
1839 | ||
1840 | return NULL; | |
1841 | } | |
1842 | ||
1843 | static void vgic_free_phys_irq_map_rcu(struct rcu_head *rcu) | |
1844 | { | |
1845 | struct irq_phys_map_entry *entry; | |
1846 | ||
1847 | entry = container_of(rcu, struct irq_phys_map_entry, rcu); | |
1848 | kfree(entry); | |
1849 | } | |
1850 | ||
6e84e0e0 MZ |
1851 | /** |
1852 | * kvm_vgic_get_phys_irq_active - Return the active state of a mapped IRQ | |
1853 | * | |
1854 | * Return the logical active state of a mapped interrupt. This doesn't | |
1855 | * necessarily reflects the current HW state. | |
1856 | */ | |
1857 | bool kvm_vgic_get_phys_irq_active(struct irq_phys_map *map) | |
1858 | { | |
1859 | BUG_ON(!map); | |
1860 | return map->active; | |
1861 | } | |
1862 | ||
1863 | /** | |
1864 | * kvm_vgic_set_phys_irq_active - Set the active state of a mapped IRQ | |
1865 | * | |
1866 | * Set the logical active state of a mapped interrupt. This doesn't | |
1867 | * immediately affects the HW state. | |
1868 | */ | |
1869 | void kvm_vgic_set_phys_irq_active(struct irq_phys_map *map, bool active) | |
1870 | { | |
1871 | BUG_ON(!map); | |
1872 | map->active = active; | |
1873 | } | |
1874 | ||
6c3d63c9 MZ |
1875 | /** |
1876 | * kvm_vgic_unmap_phys_irq - Remove a virtual to physical IRQ mapping | |
1877 | * @vcpu: The VCPU pointer | |
1878 | * @map: The pointer to a mapping obtained through kvm_vgic_map_phys_irq | |
1879 | * | |
1880 | * Remove an existing mapping between virtual and physical interrupts. | |
1881 | */ | |
1882 | int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map) | |
1883 | { | |
1884 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1885 | struct irq_phys_map_entry *entry; | |
1886 | struct list_head *root; | |
1887 | ||
1888 | if (!map) | |
1889 | return -EINVAL; | |
1890 | ||
1891 | root = vgic_get_irq_phys_map_list(vcpu, map->virt_irq); | |
1892 | ||
1893 | spin_lock(&dist->irq_phys_map_lock); | |
1894 | ||
1895 | list_for_each_entry(entry, root, entry) { | |
1896 | if (&entry->map == map) { | |
1897 | list_del_rcu(&entry->entry); | |
1898 | call_rcu(&entry->rcu, vgic_free_phys_irq_map_rcu); | |
1899 | break; | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | spin_unlock(&dist->irq_phys_map_lock); | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | static void vgic_destroy_irq_phys_map(struct kvm *kvm, struct list_head *root) | |
1909 | { | |
1910 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1911 | struct irq_phys_map_entry *entry; | |
1912 | ||
1913 | spin_lock(&dist->irq_phys_map_lock); | |
1914 | ||
1915 | list_for_each_entry(entry, root, entry) { | |
1916 | list_del_rcu(&entry->entry); | |
1917 | call_rcu(&entry->rcu, vgic_free_phys_irq_map_rcu); | |
1918 | } | |
1919 | ||
1920 | spin_unlock(&dist->irq_phys_map_lock); | |
1921 | } | |
1922 | ||
c1bfb577 MZ |
1923 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
1924 | { | |
1925 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1926 | ||
1927 | kfree(vgic_cpu->pending_shared); | |
47a98b15 CD |
1928 | kfree(vgic_cpu->active_shared); |
1929 | kfree(vgic_cpu->pend_act_shared); | |
c1bfb577 | 1930 | kfree(vgic_cpu->vgic_irq_lr_map); |
6c3d63c9 | 1931 | vgic_destroy_irq_phys_map(vcpu->kvm, &vgic_cpu->irq_phys_map_list); |
c1bfb577 | 1932 | vgic_cpu->pending_shared = NULL; |
47a98b15 CD |
1933 | vgic_cpu->active_shared = NULL; |
1934 | vgic_cpu->pend_act_shared = NULL; | |
c1bfb577 MZ |
1935 | vgic_cpu->vgic_irq_lr_map = NULL; |
1936 | } | |
1937 | ||
1938 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) | |
1939 | { | |
1940 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1941 | ||
1942 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; | |
1943 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); | |
47a98b15 CD |
1944 | vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL); |
1945 | vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL); | |
6d3cfbe2 | 1946 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
c1bfb577 | 1947 | |
47a98b15 CD |
1948 | if (!vgic_cpu->pending_shared |
1949 | || !vgic_cpu->active_shared | |
1950 | || !vgic_cpu->pend_act_shared | |
1951 | || !vgic_cpu->vgic_irq_lr_map) { | |
c1bfb577 MZ |
1952 | kvm_vgic_vcpu_destroy(vcpu); |
1953 | return -ENOMEM; | |
1954 | } | |
1955 | ||
6d3cfbe2 | 1956 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
01ac5e34 MZ |
1957 | |
1958 | /* | |
ca85f623 MZ |
1959 | * Store the number of LRs per vcpu, so we don't have to go |
1960 | * all the way to the distributor structure to find out. Only | |
1961 | * assembly code should use this one. | |
01ac5e34 | 1962 | */ |
8f186d52 | 1963 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1964 | |
6d3cfbe2 | 1965 | return 0; |
01ac5e34 MZ |
1966 | } |
1967 | ||
6c3d63c9 MZ |
1968 | /** |
1969 | * kvm_vgic_vcpu_early_init - Earliest possible per-vcpu vgic init stage | |
1970 | * | |
1971 | * No memory allocation should be performed here, only static init. | |
1972 | */ | |
1973 | void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu) | |
1974 | { | |
1975 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1976 | INIT_LIST_HEAD(&vgic_cpu->irq_phys_map_list); | |
1977 | } | |
1978 | ||
3caa2d8c AP |
1979 | /** |
1980 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW | |
1981 | * | |
1982 | * The host's GIC naturally limits the maximum amount of VCPUs a guest | |
1983 | * can use. | |
1984 | */ | |
1985 | int kvm_vgic_get_max_vcpus(void) | |
1986 | { | |
1987 | return vgic->max_gic_vcpus; | |
1988 | } | |
1989 | ||
c1bfb577 MZ |
1990 | void kvm_vgic_destroy(struct kvm *kvm) |
1991 | { | |
1992 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1993 | struct kvm_vcpu *vcpu; | |
1994 | int i; | |
1995 | ||
1996 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1997 | kvm_vgic_vcpu_destroy(vcpu); | |
1998 | ||
1999 | vgic_free_bitmap(&dist->irq_enabled); | |
2000 | vgic_free_bitmap(&dist->irq_level); | |
2001 | vgic_free_bitmap(&dist->irq_pending); | |
2002 | vgic_free_bitmap(&dist->irq_soft_pend); | |
2003 | vgic_free_bitmap(&dist->irq_queued); | |
2004 | vgic_free_bitmap(&dist->irq_cfg); | |
2005 | vgic_free_bytemap(&dist->irq_priority); | |
2006 | if (dist->irq_spi_target) { | |
2007 | for (i = 0; i < dist->nr_cpus; i++) | |
2008 | vgic_free_bitmap(&dist->irq_spi_target[i]); | |
2009 | } | |
2010 | kfree(dist->irq_sgi_sources); | |
2011 | kfree(dist->irq_spi_cpu); | |
a0675c25 | 2012 | kfree(dist->irq_spi_mpidr); |
c1bfb577 MZ |
2013 | kfree(dist->irq_spi_target); |
2014 | kfree(dist->irq_pending_on_cpu); | |
47a98b15 | 2015 | kfree(dist->irq_active_on_cpu); |
6c3d63c9 | 2016 | vgic_destroy_irq_phys_map(kvm, &dist->irq_phys_map_list); |
c1bfb577 MZ |
2017 | dist->irq_sgi_sources = NULL; |
2018 | dist->irq_spi_cpu = NULL; | |
2019 | dist->irq_spi_target = NULL; | |
2020 | dist->irq_pending_on_cpu = NULL; | |
47a98b15 | 2021 | dist->irq_active_on_cpu = NULL; |
1f57be28 | 2022 | dist->nr_cpus = 0; |
c1bfb577 MZ |
2023 | } |
2024 | ||
2025 | /* | |
2026 | * Allocate and initialize the various data structures. Must be called | |
2027 | * with kvm->lock held! | |
2028 | */ | |
83215812 | 2029 | int vgic_init(struct kvm *kvm) |
c1bfb577 MZ |
2030 | { |
2031 | struct vgic_dist *dist = &kvm->arch.vgic; | |
2032 | struct kvm_vcpu *vcpu; | |
2033 | int nr_cpus, nr_irqs; | |
6d3cfbe2 | 2034 | int ret, i, vcpu_id; |
c1bfb577 | 2035 | |
1f57be28 | 2036 | if (vgic_initialized(kvm)) |
4956f2bc MZ |
2037 | return 0; |
2038 | ||
2039 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); | |
2040 | if (!nr_cpus) /* No vcpus? Can't be good... */ | |
66b030e4 | 2041 | return -ENODEV; |
5fb66da6 | 2042 | |
4956f2bc MZ |
2043 | /* |
2044 | * If nobody configured the number of interrupts, use the | |
2045 | * legacy one. | |
2046 | */ | |
5fb66da6 MZ |
2047 | if (!dist->nr_irqs) |
2048 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; | |
2049 | ||
2050 | nr_irqs = dist->nr_irqs; | |
c1bfb577 MZ |
2051 | |
2052 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); | |
2053 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); | |
2054 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); | |
2055 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); | |
2056 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); | |
47a98b15 | 2057 | ret |= vgic_init_bitmap(&dist->irq_active, nr_cpus, nr_irqs); |
c1bfb577 MZ |
2058 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); |
2059 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); | |
2060 | ||
2061 | if (ret) | |
2062 | goto out; | |
2063 | ||
2064 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); | |
2065 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); | |
2066 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, | |
2067 | GFP_KERNEL); | |
2068 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), | |
2069 | GFP_KERNEL); | |
47a98b15 CD |
2070 | dist->irq_active_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), |
2071 | GFP_KERNEL); | |
c1bfb577 MZ |
2072 | if (!dist->irq_sgi_sources || |
2073 | !dist->irq_spi_cpu || | |
2074 | !dist->irq_spi_target || | |
47a98b15 CD |
2075 | !dist->irq_pending_on_cpu || |
2076 | !dist->irq_active_on_cpu) { | |
c1bfb577 MZ |
2077 | ret = -ENOMEM; |
2078 | goto out; | |
2079 | } | |
2080 | ||
2081 | for (i = 0; i < nr_cpus; i++) | |
2082 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], | |
2083 | nr_cpus, nr_irqs); | |
2084 | ||
2085 | if (ret) | |
2086 | goto out; | |
2087 | ||
b26e5fda AP |
2088 | ret = kvm->arch.vgic.vm_ops.init_model(kvm); |
2089 | if (ret) | |
2090 | goto out; | |
6d3cfbe2 PM |
2091 | |
2092 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { | |
c1bfb577 MZ |
2093 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
2094 | if (ret) { | |
2095 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); | |
2096 | break; | |
2097 | } | |
c1bfb577 | 2098 | |
6d3cfbe2 PM |
2099 | for (i = 0; i < dist->nr_irqs; i++) { |
2100 | if (i < VGIC_NR_PPIS) | |
2101 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
2102 | vcpu->vcpu_id, i, 1); | |
2103 | if (i < VGIC_NR_PRIVATE_IRQS) | |
2104 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
2105 | vcpu->vcpu_id, i, | |
2106 | VGIC_CFG_EDGE); | |
2107 | } | |
2108 | ||
2109 | vgic_enable(vcpu); | |
2110 | } | |
4956f2bc | 2111 | |
c1bfb577 MZ |
2112 | out: |
2113 | if (ret) | |
2114 | kvm_vgic_destroy(kvm); | |
2115 | ||
2116 | return ret; | |
2117 | } | |
2118 | ||
b26e5fda AP |
2119 | static int init_vgic_model(struct kvm *kvm, int type) |
2120 | { | |
2121 | switch (type) { | |
2122 | case KVM_DEV_TYPE_ARM_VGIC_V2: | |
2123 | vgic_v2_init_emulation(kvm); | |
2124 | break; | |
b5d84ff6 AP |
2125 | #ifdef CONFIG_ARM_GIC_V3 |
2126 | case KVM_DEV_TYPE_ARM_VGIC_V3: | |
2127 | vgic_v3_init_emulation(kvm); | |
2128 | break; | |
2129 | #endif | |
b26e5fda AP |
2130 | default: |
2131 | return -ENODEV; | |
2132 | } | |
2133 | ||
3caa2d8c AP |
2134 | if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus) |
2135 | return -E2BIG; | |
2136 | ||
b26e5fda AP |
2137 | return 0; |
2138 | } | |
2139 | ||
6c3d63c9 MZ |
2140 | /** |
2141 | * kvm_vgic_early_init - Earliest possible vgic initialization stage | |
2142 | * | |
2143 | * No memory allocation should be performed here, only static init. | |
2144 | */ | |
2145 | void kvm_vgic_early_init(struct kvm *kvm) | |
2146 | { | |
2147 | spin_lock_init(&kvm->arch.vgic.lock); | |
2148 | spin_lock_init(&kvm->arch.vgic.irq_phys_map_lock); | |
2149 | INIT_LIST_HEAD(&kvm->arch.vgic.irq_phys_map_list); | |
2150 | } | |
2151 | ||
59892136 | 2152 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
01ac5e34 | 2153 | { |
6b50f540 | 2154 | int i, vcpu_lock_idx = -1, ret; |
7330672b | 2155 | struct kvm_vcpu *vcpu; |
01ac5e34 MZ |
2156 | |
2157 | mutex_lock(&kvm->lock); | |
2158 | ||
4ce7ebdf | 2159 | if (irqchip_in_kernel(kvm)) { |
01ac5e34 MZ |
2160 | ret = -EEXIST; |
2161 | goto out; | |
2162 | } | |
2163 | ||
b5d84ff6 AP |
2164 | /* |
2165 | * This function is also called by the KVM_CREATE_IRQCHIP handler, | |
2166 | * which had no chance yet to check the availability of the GICv2 | |
2167 | * emulation. So check this here again. KVM_CREATE_DEVICE does | |
2168 | * the proper checks already. | |
2169 | */ | |
b52104e5 WY |
2170 | if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) { |
2171 | ret = -ENODEV; | |
2172 | goto out; | |
2173 | } | |
b5d84ff6 | 2174 | |
7330672b CD |
2175 | /* |
2176 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
2177 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
2178 | * that no other VCPUs are run while we create the vgic. | |
2179 | */ | |
6b50f540 | 2180 | ret = -EBUSY; |
7330672b CD |
2181 | kvm_for_each_vcpu(i, vcpu, kvm) { |
2182 | if (!mutex_trylock(&vcpu->mutex)) | |
2183 | goto out_unlock; | |
2184 | vcpu_lock_idx = i; | |
2185 | } | |
2186 | ||
2187 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6b50f540 | 2188 | if (vcpu->arch.has_run_once) |
7330672b | 2189 | goto out_unlock; |
7330672b | 2190 | } |
6b50f540 | 2191 | ret = 0; |
7330672b | 2192 | |
b26e5fda AP |
2193 | ret = init_vgic_model(kvm, type); |
2194 | if (ret) | |
2195 | goto out_unlock; | |
2196 | ||
f982cf4e | 2197 | kvm->arch.vgic.in_kernel = true; |
59892136 | 2198 | kvm->arch.vgic.vgic_model = type; |
8f186d52 | 2199 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
2200 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
2201 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
a0675c25 | 2202 | kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; |
01ac5e34 | 2203 | |
7330672b CD |
2204 | out_unlock: |
2205 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
2206 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
2207 | mutex_unlock(&vcpu->mutex); | |
2208 | } | |
2209 | ||
01ac5e34 MZ |
2210 | out: |
2211 | mutex_unlock(&kvm->lock); | |
2212 | return ret; | |
2213 | } | |
2214 | ||
1fa451bc | 2215 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
2216 | { |
2217 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
2218 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
2219 | ||
2220 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
2221 | return 0; | |
2222 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
2223 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
2224 | return -EBUSY; | |
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
2229 | phys_addr_t addr, phys_addr_t size) | |
2230 | { | |
2231 | int ret; | |
2232 | ||
ce01e4e8 CD |
2233 | if (addr & ~KVM_PHYS_MASK) |
2234 | return -E2BIG; | |
2235 | ||
2236 | if (addr & (SZ_4K - 1)) | |
2237 | return -EINVAL; | |
2238 | ||
330690cd CD |
2239 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
2240 | return -EEXIST; | |
2241 | if (addr + size < addr) | |
2242 | return -EINVAL; | |
2243 | ||
30c21170 | 2244 | *ioaddr = addr; |
330690cd CD |
2245 | ret = vgic_ioaddr_overlap(kvm); |
2246 | if (ret) | |
30c21170 HW |
2247 | *ioaddr = VGIC_ADDR_UNDEF; |
2248 | ||
330690cd CD |
2249 | return ret; |
2250 | } | |
2251 | ||
ce01e4e8 CD |
2252 | /** |
2253 | * kvm_vgic_addr - set or get vgic VM base addresses | |
2254 | * @kvm: pointer to the vm struct | |
ac3d3735 | 2255 | * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX |
ce01e4e8 CD |
2256 | * @addr: pointer to address value |
2257 | * @write: if true set the address in the VM address space, if false read the | |
2258 | * address | |
2259 | * | |
2260 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
2261 | * interface in the VM physical address space. These addresses are properties | |
2262 | * of the emulated core/SoC and therefore user space initially knows this | |
2263 | * information. | |
2264 | */ | |
2265 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
2266 | { |
2267 | int r = 0; | |
2268 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
ac3d3735 AP |
2269 | int type_needed; |
2270 | phys_addr_t *addr_ptr, block_size; | |
4fa96afd | 2271 | phys_addr_t alignment; |
330690cd | 2272 | |
330690cd CD |
2273 | mutex_lock(&kvm->lock); |
2274 | switch (type) { | |
2275 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ac3d3735 AP |
2276 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
2277 | addr_ptr = &vgic->vgic_dist_base; | |
2278 | block_size = KVM_VGIC_V2_DIST_SIZE; | |
4fa96afd | 2279 | alignment = SZ_4K; |
330690cd CD |
2280 | break; |
2281 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ac3d3735 AP |
2282 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
2283 | addr_ptr = &vgic->vgic_cpu_base; | |
2284 | block_size = KVM_VGIC_V2_CPU_SIZE; | |
4fa96afd | 2285 | alignment = SZ_4K; |
330690cd | 2286 | break; |
ac3d3735 AP |
2287 | #ifdef CONFIG_ARM_GIC_V3 |
2288 | case KVM_VGIC_V3_ADDR_TYPE_DIST: | |
2289 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
2290 | addr_ptr = &vgic->vgic_dist_base; | |
2291 | block_size = KVM_VGIC_V3_DIST_SIZE; | |
4fa96afd | 2292 | alignment = SZ_64K; |
ac3d3735 AP |
2293 | break; |
2294 | case KVM_VGIC_V3_ADDR_TYPE_REDIST: | |
2295 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
2296 | addr_ptr = &vgic->vgic_redist_base; | |
2297 | block_size = KVM_VGIC_V3_REDIST_SIZE; | |
4fa96afd | 2298 | alignment = SZ_64K; |
ac3d3735 AP |
2299 | break; |
2300 | #endif | |
330690cd CD |
2301 | default: |
2302 | r = -ENODEV; | |
ac3d3735 AP |
2303 | goto out; |
2304 | } | |
2305 | ||
2306 | if (vgic->vgic_model != type_needed) { | |
2307 | r = -ENODEV; | |
2308 | goto out; | |
330690cd CD |
2309 | } |
2310 | ||
4fa96afd AP |
2311 | if (write) { |
2312 | if (!IS_ALIGNED(*addr, alignment)) | |
2313 | r = -EINVAL; | |
2314 | else | |
2315 | r = vgic_ioaddr_assign(kvm, addr_ptr, *addr, | |
2316 | block_size); | |
2317 | } else { | |
ac3d3735 | 2318 | *addr = *addr_ptr; |
4fa96afd | 2319 | } |
ac3d3735 AP |
2320 | |
2321 | out: | |
330690cd CD |
2322 | mutex_unlock(&kvm->lock); |
2323 | return r; | |
2324 | } | |
7330672b | 2325 | |
83215812 | 2326 | int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 2327 | { |
ce01e4e8 CD |
2328 | int r; |
2329 | ||
2330 | switch (attr->group) { | |
2331 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2332 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2333 | u64 addr; | |
2334 | unsigned long type = (unsigned long)attr->attr; | |
2335 | ||
2336 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
2337 | return -EFAULT; | |
2338 | ||
2339 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
2340 | return (r == -ENODEV) ? -ENXIO : r; | |
2341 | } | |
a98f26f1 MZ |
2342 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
2343 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2344 | u32 val; | |
2345 | int ret = 0; | |
2346 | ||
2347 | if (get_user(val, uaddr)) | |
2348 | return -EFAULT; | |
2349 | ||
2350 | /* | |
2351 | * We require: | |
2352 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs | |
2353 | * - at most 1024 interrupts | |
2354 | * - a multiple of 32 interrupts | |
2355 | */ | |
2356 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || | |
2357 | val > VGIC_MAX_IRQS || | |
2358 | (val & 31)) | |
2359 | return -EINVAL; | |
2360 | ||
2361 | mutex_lock(&dev->kvm->lock); | |
2362 | ||
c52edf5f | 2363 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
a98f26f1 MZ |
2364 | ret = -EBUSY; |
2365 | else | |
2366 | dev->kvm->arch.vgic.nr_irqs = val; | |
2367 | ||
2368 | mutex_unlock(&dev->kvm->lock); | |
2369 | ||
2370 | return ret; | |
2371 | } | |
065c0034 EA |
2372 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
2373 | switch (attr->attr) { | |
2374 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
2375 | r = vgic_init(dev->kvm); | |
2376 | return r; | |
2377 | } | |
2378 | break; | |
2379 | } | |
ce01e4e8 CD |
2380 | } |
2381 | ||
7330672b CD |
2382 | return -ENXIO; |
2383 | } | |
2384 | ||
83215812 | 2385 | int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 2386 | { |
ce01e4e8 CD |
2387 | int r = -ENXIO; |
2388 | ||
2389 | switch (attr->group) { | |
2390 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2391 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2392 | u64 addr; | |
2393 | unsigned long type = (unsigned long)attr->attr; | |
2394 | ||
2395 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
2396 | if (r) | |
2397 | return (r == -ENODEV) ? -ENXIO : r; | |
2398 | ||
2399 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
2400 | return -EFAULT; | |
c07a0191 CD |
2401 | break; |
2402 | } | |
b60da146 AP |
2403 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
2404 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2405 | ||
2406 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); | |
2407 | break; | |
2408 | } | |
2409 | ||
2410 | } | |
2411 | ||
2412 | return r; | |
2413 | } | |
2414 | ||
cf50a1eb | 2415 | int vgic_has_attr_regs(const struct vgic_io_range *ranges, phys_addr_t offset) |
c07a0191 | 2416 | { |
9f199d0a | 2417 | if (vgic_find_range(ranges, 4, offset)) |
c07a0191 CD |
2418 | return 0; |
2419 | else | |
2420 | return -ENXIO; | |
2421 | } | |
2422 | ||
c06a841b WD |
2423 | static void vgic_init_maintenance_interrupt(void *info) |
2424 | { | |
2425 | enable_percpu_irq(vgic->maint_irq, 0); | |
2426 | } | |
2427 | ||
2428 | static int vgic_cpu_notify(struct notifier_block *self, | |
2429 | unsigned long action, void *cpu) | |
2430 | { | |
2431 | switch (action) { | |
2432 | case CPU_STARTING: | |
2433 | case CPU_STARTING_FROZEN: | |
2434 | vgic_init_maintenance_interrupt(NULL); | |
2435 | break; | |
2436 | case CPU_DYING: | |
2437 | case CPU_DYING_FROZEN: | |
2438 | disable_percpu_irq(vgic->maint_irq); | |
2439 | break; | |
2440 | } | |
2441 | ||
2442 | return NOTIFY_OK; | |
2443 | } | |
2444 | ||
2445 | static struct notifier_block vgic_cpu_nb = { | |
2446 | .notifier_call = vgic_cpu_notify, | |
2447 | }; | |
2448 | ||
2449 | static const struct of_device_id vgic_ids[] = { | |
0f372475 MR |
2450 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, |
2451 | { .compatible = "arm,cortex-a7-gic", .data = vgic_v2_probe, }, | |
2452 | { .compatible = "arm,gic-400", .data = vgic_v2_probe, }, | |
2453 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
c06a841b WD |
2454 | {}, |
2455 | }; | |
2456 | ||
2457 | int kvm_vgic_hyp_init(void) | |
2458 | { | |
2459 | const struct of_device_id *matched_id; | |
a875dafc CD |
2460 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2461 | const struct vgic_params **); | |
c06a841b WD |
2462 | struct device_node *vgic_node; |
2463 | int ret; | |
2464 | ||
2465 | vgic_node = of_find_matching_node_and_match(NULL, | |
2466 | vgic_ids, &matched_id); | |
2467 | if (!vgic_node) { | |
2468 | kvm_err("error: no compatible GIC node found\n"); | |
2469 | return -ENODEV; | |
2470 | } | |
2471 | ||
2472 | vgic_probe = matched_id->data; | |
2473 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2474 | if (ret) | |
2475 | return ret; | |
2476 | ||
2477 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2478 | "vgic", kvm_get_running_vcpus()); | |
2479 | if (ret) { | |
2480 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2481 | return ret; | |
2482 | } | |
2483 | ||
2484 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2485 | if (ret) { | |
2486 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2487 | goto out_free_irq; | |
2488 | } | |
2489 | ||
c06a841b WD |
2490 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); |
2491 | ||
ea2f83a7 | 2492 | return 0; |
c06a841b WD |
2493 | |
2494 | out_free_irq: | |
2495 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2496 | return ret; | |
2497 | } | |
174178fe EA |
2498 | |
2499 | int kvm_irq_map_gsi(struct kvm *kvm, | |
2500 | struct kvm_kernel_irq_routing_entry *entries, | |
2501 | int gsi) | |
2502 | { | |
0b3289eb | 2503 | return 0; |
174178fe EA |
2504 | } |
2505 | ||
2506 | int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin) | |
2507 | { | |
2508 | return pin; | |
2509 | } | |
2510 | ||
2511 | int kvm_set_irq(struct kvm *kvm, int irq_source_id, | |
2512 | u32 irq, int level, bool line_status) | |
2513 | { | |
2514 | unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS; | |
2515 | ||
2516 | trace_kvm_set_irq(irq, level, irq_source_id); | |
2517 | ||
2518 | BUG_ON(!vgic_initialized(kvm)); | |
2519 | ||
174178fe | 2520 | return kvm_vgic_inject_irq(kvm, 0, spi, level); |
174178fe EA |
2521 | } |
2522 | ||
2523 | /* MSI not implemented yet */ | |
2524 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, | |
2525 | struct kvm *kvm, int irq_source_id, | |
2526 | int level, bool line_status) | |
2527 | { | |
2528 | return 0; | |
2529 | } |