[mirror_ubuntu-bionic-kernel.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}

	return injected;
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		mask_before = ioapic->redirtbl[index].fields.mask;
		if (ioapic->ioregsel & 1) {
			ioapic->redirtbl[index].bits &= 0xffffffff;
			ioapic->redirtbl[index].bits |= (u64) val << 32;
		} else {
			ioapic->redirtbl[index].bits &= ~0xffffffffULL;
			ioapic->redirtbl[index].bits |= (u32) val;
			ioapic->redirtbl[index].fields.remote_irr = 0;
		}
		mask_after = ioapic->redirtbl[index].fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
		if (ioapic->redirtbl[index].fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;

#ifdef CONFIG_X86
	/* Always delivery PIT interrupt to vcpu 0 */
	if (irq == 0) {
		irqe.dest_mode = 0; /* Physical mode. */
		irqe.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
	}
#endif
	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
{
	u32 old_irr = ioapic->irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret = 1;

	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
		entry = ioapic->redirtbl[irq];
		level ^= entry.fields.polarity;
		if (!level)
			ioapic->irr &= ~mask;
		else {
			int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
			ioapic->irr |= mask;
			if ((edge && old_irr != ioapic->irr) ||
			    (!edge && !entry.fields.remote_irr))
				ret = ioapic_service(ioapic, irq);
		}
	}
	return ret;
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
				    int trigger_mode)
{
	union kvm_ioapic_redirect_entry *ent;

	ent = &ioapic->redirtbl[pin];

	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);

	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
			ioapic_service(ioapic, pin);
	}
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		if (ioapic->redirtbl[i].fields.vector == vector)
			__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
}

static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
			   int len, int is_write)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;

	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			     void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 result;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
}

static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			      const void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 data;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */
	if (len == 4 || len == 8)
		data = *(u32 *) val;
	else {
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return;
	}

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data;
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
}

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	ioapic->dev.read = ioapic_mmio_read;
	ioapic->dev.write = ioapic_mmio_write;
	ioapic->dev.in_range = ioapic_in_range;
	ioapic->dev.private = ioapic;
	ioapic->kvm = kvm;
	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
	2	* Copyright (C) 2001 MandrakeSoft S.A.
	3	*
	4	* MandrakeSoft S.A.
	5	* 43, rue d'Aboukir
	6	* 75002 Paris - France
	7	* http://www.linux-mandrake.com/
	8	* http://www.mandrakesoft.com/
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Yunhong Jiang <yunhong.jiang@intel.com>
	25	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	26	* Based on Xen 3.1 code.
	27	*/
	28
edf88417	29	#include <linux/kvm_host.h>
1fd4f2a5 ED	30	#include <linux/kvm.h>
	31	#include <linux/mm.h>
	32	#include <linux/highmem.h>
	33	#include <linux/smp.h>
	34	#include <linux/hrtimer.h>
	35	#include <linux/io.h>
	36	#include <asm/processor.h>
1fd4f2a5 ED	37	#include <asm/page.h>
1fd4f2a5 ED	38	#include <asm/current.h>
82470196 ZX	39
	40	#include "ioapic.h"
	41	#include "lapic.h"
f5244726	42	#include "irq.h"
82470196	43
e25e3ed5 LV	44	#if 0
	45	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	46	#else
1fd4f2a5	47	#define ioapic_debug(fmt, arg...)
e25e3ed5	48	#endif
ff4b9df8	49	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	50
	51	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	52	unsigned long addr,
	53	unsigned long length)
	54	{
	55	unsigned long result = 0;
	56
	57	switch (ioapic->ioregsel) {
	58	case IOAPIC_REG_VERSION:
	59	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	60	\| (IOAPIC_VERSION_ID & 0xff));
	61	break;
	62
	63	case IOAPIC_REG_APIC_ID:
	64	case IOAPIC_REG_ARB_ID:
	65	result = ((ioapic->id & 0xf) << 24);
	66	break;
	67
	68	default:
	69	{
	70	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	71	u64 redir_content;
	72
	73	ASSERT(redir_index < IOAPIC_NUM_PINS);
	74
	75	redir_content = ioapic->redirtbl[redir_index].bits;
	76	result = (ioapic->ioregsel & 0x1) ?
	77	(redir_content >> 32) & 0xffffffff :
	78	redir_content & 0xffffffff;
	79	break;
	80	}
	81	}
	82
	83	return result;
	84	}
	85
4925663a	86	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	87	{
cf9e4e15	88	union kvm_ioapic_redirect_entry *pent;
4925663a	89	int injected = -1;
1fd4f2a5 ED	90
	91	pent = &ioapic->redirtbl[idx];
	92
	93	if (!pent->fields.mask) {
4925663a	94	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	95	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	96	pent->fields.remote_irr = 1;
1fd4f2a5 ED	97	}
4925663a GN	98
4925663a GN	99	return injected;
1fd4f2a5 ED	100	}
	101
	102	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	103	{
	104	unsigned index;
75858a84	105	bool mask_before, mask_after;
1fd4f2a5 ED	106
	107	switch (ioapic->ioregsel) {
	108	case IOAPIC_REG_VERSION:
	109	/* Writes are ignored. */
	110	break;
	111
	112	case IOAPIC_REG_APIC_ID:
	113	ioapic->id = (val >> 24) & 0xf;
	114	break;
	115
	116	case IOAPIC_REG_ARB_ID:
	117	break;
	118
	119	default:
	120	index = (ioapic->ioregsel - 0x10) >> 1;
	121
e25e3ed5	122	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	123	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	124	return;
75858a84	125	mask_before = ioapic->redirtbl[index].fields.mask;
1fd4f2a5 ED	126	if (ioapic->ioregsel & 1) {
	127	ioapic->redirtbl[index].bits &= 0xffffffff;
	128	ioapic->redirtbl[index].bits \|= (u64) val << 32;
	129	} else {
	130	ioapic->redirtbl[index].bits &= ~0xffffffffULL;
	131	ioapic->redirtbl[index].bits \|= (u32) val;
	132	ioapic->redirtbl[index].fields.remote_irr = 0;
	133	}
75858a84 AK	134	mask_after = ioapic->redirtbl[index].fields.mask;
	135	if (mask_before != mask_after)
	136	kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
b4a2f5e7 GN	137	if (ioapic->redirtbl[index].fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7 GN	138	&& ioapic->irr & (1 << index))
1fd4f2a5 ED	139	ioapic_service(ioapic, index);
	140	break;
	141	}
	142	}
	143
a53c17d2 GN	144	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
a53c17d2 GN	145	{
58c2dde1 GN	146	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	147	struct kvm_lapic_irq irqe;
a53c17d2 GN	148
	149	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
	150	"vector=%x trig_mode=%x\n",
58c2dde1 GN	151	entry->fields.dest, entry->fields.dest_mode,
	152	entry->fields.delivery_mode, entry->fields.vector,
	153	entry->fields.trig_mode);
	154
	155	irqe.dest_id = entry->fields.dest_id;
	156	irqe.vector = entry->fields.vector;
	157	irqe.dest_mode = entry->fields.dest_mode;
	158	irqe.trig_mode = entry->fields.trig_mode;
	159	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	160	irqe.level = 1;
	161	irqe.shorthand = 0;
a53c17d2 GN	162
	163	#ifdef CONFIG_X86
	164	/* Always delivery PIT interrupt to vcpu 0 */
	165	if (irq == 0) {
58c2dde1 GN	166	irqe.dest_mode = 0; /* Physical mode. */
58c2dde1 GN	167	irqe.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
a53c17d2 GN	168	}
a53c17d2 GN	169	#endif
58c2dde1	170	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
a53c17d2 GN	171	}
a53c17d2 GN	172
4925663a	173	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
1fd4f2a5 ED	174	{
	175	u32 old_irr = ioapic->irr;
	176	u32 mask = 1 << irq;
cf9e4e15	177	union kvm_ioapic_redirect_entry entry;
4925663a	178	int ret = 1;
1fd4f2a5 ED	179
	180	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
	181	entry = ioapic->redirtbl[irq];
	182	level ^= entry.fields.polarity;
	183	if (!level)
	184	ioapic->irr &= ~mask;
	185	else {
b4a2f5e7	186	int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
1fd4f2a5	187	ioapic->irr \|= mask;
b4a2f5e7 GN	188	if ((edge && old_irr != ioapic->irr) \|\|
b4a2f5e7 GN	189	(!edge && !entry.fields.remote_irr))
4925663a	190	ret = ioapic_service(ioapic, irq);
1fd4f2a5 ED	191	}
1fd4f2a5 ED	192	}
4925663a	193	return ret;
1fd4f2a5 ED	194	}
1fd4f2a5 ED	195
44882eed	196	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
f5244726	197	int trigger_mode)
1fd4f2a5	198	{
cf9e4e15	199	union kvm_ioapic_redirect_entry *ent;
1fd4f2a5	200
44882eed	201	ent = &ioapic->redirtbl[pin];
1fd4f2a5	202
44882eed	203	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
f5244726 MT	204
	205	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
	206	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
	207	ent->fields.remote_irr = 0;
44882eed MT	208	if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
44882eed MT	209	ioapic_service(ioapic, pin);
f5244726	210	}
1fd4f2a5 ED	211	}
1fd4f2a5 ED	212
f5244726	213	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	214	{
	215	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	216	int i;
	217
	218	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	219	if (ioapic->redirtbl[i].fields.vector == vector)
f5244726	220	__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
4fa6b9c5 AK	221	}
4fa6b9c5 AK	222
92760499 LV	223	static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	224	int len, int is_write)
1fd4f2a5 ED	225	{
	226	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	227
	228	return ((addr >= ioapic->base_address &&
	229	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	230	}
	231
	232	static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
	233	void *val)
	234	{
	235	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	236	u32 result;
	237
e25e3ed5	238	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	239	ASSERT(!(addr & 0xf)); /* check alignment */
	240
	241	addr &= 0xff;
	242	switch (addr) {
	243	case IOAPIC_REG_SELECT:
	244	result = ioapic->ioregsel;
	245	break;
	246
	247	case IOAPIC_REG_WINDOW:
	248	result = ioapic_read_indirect(ioapic, addr, len);
	249	break;
	250
	251	default:
	252	result = 0;
	253	break;
	254	}
	255	switch (len) {
	256	case 8:
	257	(u64 ) val = result;
	258	break;
	259	case 1:
	260	case 2:
	261	case 4:
	262	memcpy(val, (char *)&result, len);
	263	break;
	264	default:
	265	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	266	}
	267	}
	268
	269	static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
	270	const void *val)
	271	{
	272	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	273	u32 data;
	274
e25e3ed5 LV	275	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	276	(void*)addr, len, val);
1fd4f2a5 ED	277	ASSERT(!(addr & 0xf)); /* check alignment */
	278	if (len == 4 \|\| len == 8)
	279	data = (u32 ) val;
	280	else {
	281	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
	282	return;
	283	}
	284
	285	addr &= 0xff;
	286	switch (addr) {
	287	case IOAPIC_REG_SELECT:
	288	ioapic->ioregsel = data;
	289	break;
	290
	291	case IOAPIC_REG_WINDOW:
	292	ioapic_write_indirect(ioapic, data);
	293	break;
b1fd3d30 ZX	294	#ifdef CONFIG_IA64
b1fd3d30 ZX	295	case IOAPIC_REG_EOI:
26815a64	296	kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	297	break;
b1fd3d30 ZX	298	#endif
1fd4f2a5 ED	299
	300	default:
	301	break;
	302	}
	303	}
	304
8c392696 ED	305	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	306	{
	307	int i;
	308
	309	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	310	ioapic->redirtbl[i].fields.mask = 1;
	311	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	312	ioapic->ioregsel = 0;
	313	ioapic->irr = 0;
	314	ioapic->id = 0;
	315	}
	316
1fd4f2a5 ED	317	int kvm_ioapic_init(struct kvm *kvm)
	318	{
	319	struct kvm_ioapic *ioapic;
1fd4f2a5 ED	320
	321	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	322	if (!ioapic)
	323	return -ENOMEM;
d7deeeb0	324	kvm->arch.vioapic = ioapic;
8c392696	325	kvm_ioapic_reset(ioapic);
1fd4f2a5 ED	326	ioapic->dev.read = ioapic_mmio_read;
	327	ioapic->dev.write = ioapic_mmio_write;
	328	ioapic->dev.in_range = ioapic_in_range;
	329	ioapic->dev.private = ioapic;
	330	ioapic->kvm = kvm;
	331	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	332	return 0;
	333	}
75858a84	334