[mirror_ubuntu-artful-kernel.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>
#include <trace/events/kvm.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}

	return injected;
}

static void update_handled_vectors(struct kvm_ioapic *ioapic)
{
	DECLARE_BITMAP(handled_vectors, 256);
	int i;

	memset(handled_vectors, 0, sizeof(handled_vectors));
	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
		__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	memcpy(ioapic->handled_vectors, handled_vectors,
	       sizeof(handled_vectors));
	smp_wmb();
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;
	union kvm_ioapic_redirect_entry *e;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		e = &ioapic->redirtbl[index];
		mask_before = e->fields.mask;
		if (ioapic->ioregsel & 1) {
			e->bits &= 0xffffffff;
			e->bits |= (u64) val << 32;
		} else {
			e->bits &= ~0xffffffffULL;
			e->bits |= (u32) val;
			e->fields.remote_irr = 0;
		}
		update_handled_vectors(ioapic);
		mask_after = e->fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest_id, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;

#ifdef CONFIG_X86
	/* Always delivery PIT interrupt to vcpu 0 */
	if (irq == 0) {
		irqe.dest_mode = 0; /* Physical mode. */
		/* need to read apic_id from apic regiest since
		 * it can be rewritten */
		irqe.dest_id = ioapic->kvm->bsp_vcpu_id;
	}
#endif
	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
		       int level)
{
	u32 old_irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret, irq_level;

	BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);

	spin_lock(&ioapic->lock);
	old_irr = ioapic->irr;
	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
					 irq_source_id, level);
	entry = ioapic->redirtbl[irq];
	irq_level ^= entry.fields.polarity;
	if (!irq_level) {
		ioapic->irr &= ~mask;
		ret = 1;
	} else {
		int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
		ioapic->irr |= mask;
		if ((edge && old_irr != ioapic->irr) ||
		    (!edge && !entry.fields.remote_irr))
			ret = ioapic_service(ioapic, irq);
		else
			ret = 0; /* report coalesced interrupt */
	}
	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	spin_unlock(&ioapic->lock);

	return ret;
}

void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
{
	int i;

	spin_lock(&ioapic->lock);
	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
		__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	spin_unlock(&ioapic->lock);
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
				     int trigger_mode)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];

		if (ent->fields.vector != vector)
			continue;

		/*
		 * We are dropping lock while calling ack notifiers because ack
		 * notifier callbacks for assigned devices call into IOAPIC
		 * recursively. Since remote_irr is cleared only after call
		 * to notifiers if the same vector will be delivered while lock
		 * is dropped it will be put into irr and will be delivered
		 * after ack notifier returns.
		 */
		spin_unlock(&ioapic->lock);
		kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
		spin_lock(&ioapic->lock);

		if (trigger_mode != IOAPIC_LEVEL_TRIG)
			continue;

		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << i)))
			ioapic_service(ioapic, i);
	}
}

bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	smp_rmb();
	return test_bit(vector, ioapic->handled_vectors);
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	spin_lock(&ioapic->lock);
	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
	spin_unlock(&ioapic->lock);
}

static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_ioapic, dev);
}

static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
{
	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			    void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 result;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	spin_unlock(&ioapic->lock);

	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
	return 0;
}

static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			     const void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 data;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */

	switch (len) {
	case 8:
	case 4:
		data = *(u32 *) val;
		break;
	case 2:
		data = *(u16 *) val;
		break;
	case 1:
		data = *(u8  *) val;
		break;
	default:
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return 0;
	}

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data & 0xFF; /* 8-bit register */
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
	spin_unlock(&ioapic->lock);
	return 0;
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
	update_handled_vectors(ioapic);
}

static const struct kvm_io_device_ops ioapic_mmio_ops = {
	.read     = ioapic_mmio_read,
	.write    = ioapic_mmio_write,
};

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;
	int ret;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	spin_lock_init(&ioapic->lock);
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
	ioapic->kvm = kvm;
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
				      IOAPIC_MEM_LENGTH, &ioapic->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kvm->arch.vioapic = NULL;
		kfree(ioapic);
	}

	return ret;
}

void kvm_ioapic_destroy(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	if (ioapic) {
		kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
		kvm->arch.vioapic = NULL;
		kfree(ioapic);
	}
}

int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
	spin_unlock(&ioapic->lock);
	return 0;
}

int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
	update_handled_vectors(ioapic);
	spin_unlock(&ioapic->lock);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
1fd4f2a5 ED	2	* Copyright (C) 2001 MandrakeSoft S.A.
221d059d	3	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
1fd4f2a5 ED	4	*
	5	* MandrakeSoft S.A.
	6	* 43, rue d'Aboukir
	7	* 75002 Paris - France
	8	* http://www.linux-mandrake.com/
	9	* http://www.mandrakesoft.com/
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
	22	* License along with this library; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*
	25	* Yunhong Jiang <yunhong.jiang@intel.com>
	26	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	27	* Based on Xen 3.1 code.
	28	*/
	29
edf88417	30	#include <linux/kvm_host.h>
1fd4f2a5 ED	31	#include <linux/kvm.h>
	32	#include <linux/mm.h>
	33	#include <linux/highmem.h>
	34	#include <linux/smp.h>
	35	#include <linux/hrtimer.h>
	36	#include <linux/io.h>
5a0e3ad6	37	#include <linux/slab.h>
1fd4f2a5	38	#include <asm/processor.h>
1fd4f2a5 ED	39	#include <asm/page.h>
1fd4f2a5 ED	40	#include <asm/current.h>
1000ff8d	41	#include <trace/events/kvm.h>
82470196 ZX	42
	43	#include "ioapic.h"
	44	#include "lapic.h"
f5244726	45	#include "irq.h"
82470196	46
e25e3ed5 LV	47	#if 0
	48	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	49	#else
1fd4f2a5	50	#define ioapic_debug(fmt, arg...)
e25e3ed5	51	#endif
ff4b9df8	52	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	53
	54	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	55	unsigned long addr,
	56	unsigned long length)
	57	{
	58	unsigned long result = 0;
	59
	60	switch (ioapic->ioregsel) {
	61	case IOAPIC_REG_VERSION:
	62	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	63	\| (IOAPIC_VERSION_ID & 0xff));
	64	break;
	65
	66	case IOAPIC_REG_APIC_ID:
	67	case IOAPIC_REG_ARB_ID:
	68	result = ((ioapic->id & 0xf) << 24);
	69	break;
	70
	71	default:
	72	{
	73	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	74	u64 redir_content;
	75
	76	ASSERT(redir_index < IOAPIC_NUM_PINS);
	77
	78	redir_content = ioapic->redirtbl[redir_index].bits;
	79	result = (ioapic->ioregsel & 0x1) ?
	80	(redir_content >> 32) & 0xffffffff :
	81	redir_content & 0xffffffff;
	82	break;
	83	}
	84	}
	85
	86	return result;
	87	}
	88
4925663a	89	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	90	{
cf9e4e15	91	union kvm_ioapic_redirect_entry *pent;
4925663a	92	int injected = -1;
1fd4f2a5 ED	93
	94	pent = &ioapic->redirtbl[idx];
	95
	96	if (!pent->fields.mask) {
4925663a	97	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	98	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	99	pent->fields.remote_irr = 1;
1fd4f2a5 ED	100	}
4925663a GN	101
4925663a GN	102	return injected;
1fd4f2a5 ED	103	}
1fd4f2a5 ED	104
46a929bc AK	105	static void update_handled_vectors(struct kvm_ioapic *ioapic)
	106	{
	107	DECLARE_BITMAP(handled_vectors, 256);
	108	int i;
	109
	110	memset(handled_vectors, 0, sizeof(handled_vectors));
	111	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
	112	__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	113	memcpy(ioapic->handled_vectors, handled_vectors,
	114	sizeof(handled_vectors));
	115	smp_wmb();
	116	}
	117
1fd4f2a5 ED	118	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	119	{
	120	unsigned index;
75858a84	121	bool mask_before, mask_after;
70f93dae	122	union kvm_ioapic_redirect_entry *e;
1fd4f2a5 ED	123
	124	switch (ioapic->ioregsel) {
	125	case IOAPIC_REG_VERSION:
	126	/* Writes are ignored. */
	127	break;
	128
	129	case IOAPIC_REG_APIC_ID:
	130	ioapic->id = (val >> 24) & 0xf;
	131	break;
	132
	133	case IOAPIC_REG_ARB_ID:
	134	break;
	135
	136	default:
	137	index = (ioapic->ioregsel - 0x10) >> 1;
	138
e25e3ed5	139	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	140	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	141	return;
70f93dae GN	142	e = &ioapic->redirtbl[index];
70f93dae GN	143	mask_before = e->fields.mask;
1fd4f2a5	144	if (ioapic->ioregsel & 1) {
70f93dae GN	145	e->bits &= 0xffffffff;
70f93dae GN	146	e->bits \|= (u64) val << 32;
1fd4f2a5	147	} else {
70f93dae GN	148	e->bits &= ~0xffffffffULL;
	149	e->bits \|= (u32) val;
	150	e->fields.remote_irr = 0;
1fd4f2a5	151	}
46a929bc	152	update_handled_vectors(ioapic);
70f93dae	153	mask_after = e->fields.mask;
75858a84	154	if (mask_before != mask_after)
4a994358	155	kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
70f93dae	156	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7	157	&& ioapic->irr & (1 << index))
1fd4f2a5 ED	158	ioapic_service(ioapic, index);
	159	break;
	160	}
	161	}
	162
a53c17d2 GN	163	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
a53c17d2 GN	164	{
58c2dde1 GN	165	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	166	struct kvm_lapic_irq irqe;
a53c17d2 GN	167
	168	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
	169	"vector=%x trig_mode=%x\n",
a38f84ca	170	entry->fields.dest_id, entry->fields.dest_mode,
58c2dde1 GN	171	entry->fields.delivery_mode, entry->fields.vector,
	172	entry->fields.trig_mode);
	173
	174	irqe.dest_id = entry->fields.dest_id;
	175	irqe.vector = entry->fields.vector;
	176	irqe.dest_mode = entry->fields.dest_mode;
	177	irqe.trig_mode = entry->fields.trig_mode;
	178	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	179	irqe.level = 1;
	180	irqe.shorthand = 0;
a53c17d2 GN	181
	182	#ifdef CONFIG_X86
	183	/* Always delivery PIT interrupt to vcpu 0 */
	184	if (irq == 0) {
58c2dde1	185	irqe.dest_mode = 0; /* Physical mode. */
c5af89b6 GN	186	/* need to read apic_id from apic regiest since
c5af89b6 GN	187	* it can be rewritten */
d546cb40	188	irqe.dest_id = ioapic->kvm->bsp_vcpu_id;
a53c17d2 GN	189	}
a53c17d2 GN	190	#endif
58c2dde1	191	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
a53c17d2 GN	192	}
a53c17d2 GN	193
1a577b72 MT	194	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
1a577b72 MT	195	int level)
1fd4f2a5	196	{
07dc7263	197	u32 old_irr;
1fd4f2a5	198	u32 mask = 1 << irq;
cf9e4e15	199	union kvm_ioapic_redirect_entry entry;
28a6fdab MT	200	int ret, irq_level;
	201
	202	BUG_ON(irq < 0 \|\| irq >= IOAPIC_NUM_PINS);
1fd4f2a5	203
46a47b1e	204	spin_lock(&ioapic->lock);
07dc7263	205	old_irr = ioapic->irr;
28a6fdab MT	206	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
	207	irq_source_id, level);
	208	entry = ioapic->redirtbl[irq];
	209	irq_level ^= entry.fields.polarity;
	210	if (!irq_level) {
	211	ioapic->irr &= ~mask;
	212	ret = 1;
	213	} else {
	214	int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
	215	ioapic->irr \|= mask;
	216	if ((edge && old_irr != ioapic->irr) \|\|
	217	(!edge && !entry.fields.remote_irr))
	218	ret = ioapic_service(ioapic, irq);
	219	else
	220	ret = 0; /* report coalesced interrupt */
1fd4f2a5	221	}
28a6fdab	222	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
46a47b1e	223	spin_unlock(&ioapic->lock);
eba0226b	224
4925663a	225	return ret;
1fd4f2a5 ED	226	}
1fd4f2a5 ED	227
1a577b72 MT	228	void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
	229	{
	230	int i;
	231
	232	spin_lock(&ioapic->lock);
	233	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
	234	__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	235	spin_unlock(&ioapic->lock);
	236	}
	237
eba0226b GN	238	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
eba0226b GN	239	int trigger_mode)
1fd4f2a5	240	{
eba0226b GN	241	int i;
	242
	243	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	244	union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
1fd4f2a5	245
eba0226b GN	246	if (ent->fields.vector != vector)
eba0226b GN	247	continue;
1fd4f2a5	248
eba0226b GN	249	/*
	250	* We are dropping lock while calling ack notifiers because ack
	251	* notifier callbacks for assigned devices call into IOAPIC
	252	* recursively. Since remote_irr is cleared only after call
	253	* to notifiers if the same vector will be delivered while lock
	254	* is dropped it will be put into irr and will be delivered
	255	* after ack notifier returns.
	256	*/
46a47b1e	257	spin_unlock(&ioapic->lock);
eba0226b	258	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
46a47b1e	259	spin_lock(&ioapic->lock);
eba0226b GN	260
	261	if (trigger_mode != IOAPIC_LEVEL_TRIG)
	262	continue;
f5244726	263
f5244726 MT	264	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
f5244726 MT	265	ent->fields.remote_irr = 0;
eba0226b GN	266	if (!ent->fields.mask && (ioapic->irr & (1 << i)))
eba0226b GN	267	ioapic_service(ioapic, i);
f5244726	268	}
1fd4f2a5 ED	269	}
1fd4f2a5 ED	270
a0c9a822 MT	271	bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
	272	{
	273	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	274	smp_rmb();
	275	return test_bit(vector, ioapic->handled_vectors);
	276	}
	277
f5244726	278	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	279	{
4fa6b9c5 AK	280	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
4fa6b9c5	281
46a47b1e	282	spin_lock(&ioapic->lock);
eba0226b	283	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
46a47b1e	284	spin_unlock(&ioapic->lock);
4fa6b9c5 AK	285	}
4fa6b9c5 AK	286
d76685c4 GH	287	static inline struct kvm_ioapic to_ioapic(struct kvm_io_device dev)
	288	{
	289	return container_of(dev, struct kvm_ioapic, dev);
	290	}
	291
bda9020e	292	static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
1fd4f2a5	293	{
1fd4f2a5 ED	294	return ((addr >= ioapic->base_address &&
	295	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	296	}
	297
bda9020e MT	298	static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	299	void *val)
1fd4f2a5	300	{
d76685c4	301	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	302	u32 result;
bda9020e MT	303	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	304	return -EOPNOTSUPP;
1fd4f2a5	305
e25e3ed5	306	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	307	ASSERT(!(addr & 0xf)); /* check alignment */
	308
	309	addr &= 0xff;
46a47b1e	310	spin_lock(&ioapic->lock);
1fd4f2a5 ED	311	switch (addr) {
	312	case IOAPIC_REG_SELECT:
	313	result = ioapic->ioregsel;
	314	break;
	315
	316	case IOAPIC_REG_WINDOW:
	317	result = ioapic_read_indirect(ioapic, addr, len);
	318	break;
	319
	320	default:
	321	result = 0;
	322	break;
	323	}
46a47b1e	324	spin_unlock(&ioapic->lock);
eba0226b	325
1fd4f2a5 ED	326	switch (len) {
	327	case 8:
	328	(u64 ) val = result;
	329	break;
	330	case 1:
	331	case 2:
	332	case 4:
	333	memcpy(val, (char *)&result, len);
	334	break;
	335	default:
	336	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	337	}
bda9020e	338	return 0;
1fd4f2a5 ED	339	}
1fd4f2a5 ED	340
bda9020e MT	341	static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	342	const void *val)
1fd4f2a5	343	{
d76685c4	344	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	345	u32 data;
bda9020e MT	346	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	347	return -EOPNOTSUPP;
1fd4f2a5	348
e25e3ed5 LV	349	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	350	(void*)addr, len, val);
1fd4f2a5	351	ASSERT(!(addr & 0xf)); /* check alignment */
60eead79	352
d77fe635 JS	353	switch (len) {
	354	case 8:
	355	case 4:
1fd4f2a5	356	data = (u32 ) val;
d77fe635 JS	357	break;
	358	case 2:
	359	data = (u16 ) val;
	360	break;
	361	case 1:
	362	data = (u8 ) val;
	363	break;
	364	default:
1fd4f2a5	365	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
eba0226b	366	return 0;
1fd4f2a5 ED	367	}
	368
	369	addr &= 0xff;
46a47b1e	370	spin_lock(&ioapic->lock);
1fd4f2a5 ED	371	switch (addr) {
1fd4f2a5 ED	372	case IOAPIC_REG_SELECT:
d77fe635	373	ioapic->ioregsel = data & 0xFF; /* 8-bit register */
1fd4f2a5 ED	374	break;
	375
	376	case IOAPIC_REG_WINDOW:
	377	ioapic_write_indirect(ioapic, data);
	378	break;
b1fd3d30 ZX	379	#ifdef CONFIG_IA64
b1fd3d30 ZX	380	case IOAPIC_REG_EOI:
eba0226b	381	__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	382	break;
b1fd3d30 ZX	383	#endif
1fd4f2a5 ED	384
	385	default:
	386	break;
	387	}
46a47b1e	388	spin_unlock(&ioapic->lock);
bda9020e	389	return 0;
1fd4f2a5 ED	390	}
1fd4f2a5 ED	391
8c392696 ED	392	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	393	{
	394	int i;
	395
	396	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	397	ioapic->redirtbl[i].fields.mask = 1;
	398	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	399	ioapic->ioregsel = 0;
	400	ioapic->irr = 0;
	401	ioapic->id = 0;
46a929bc	402	update_handled_vectors(ioapic);
8c392696 ED	403	}
8c392696 ED	404
d76685c4 GH	405	static const struct kvm_io_device_ops ioapic_mmio_ops = {
	406	.read = ioapic_mmio_read,
	407	.write = ioapic_mmio_write,
d76685c4 GH	408	};
d76685c4 GH	409
1fd4f2a5 ED	410	int kvm_ioapic_init(struct kvm *kvm)
	411	{
	412	struct kvm_ioapic *ioapic;
090b7aff	413	int ret;
1fd4f2a5 ED	414
	415	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	416	if (!ioapic)
	417	return -ENOMEM;
46a47b1e	418	spin_lock_init(&ioapic->lock);
d7deeeb0	419	kvm->arch.vioapic = ioapic;
8c392696	420	kvm_ioapic_reset(ioapic);
d76685c4	421	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
1fd4f2a5	422	ioapic->kvm = kvm;
79fac95e	423	mutex_lock(&kvm->slots_lock);
743eeb0b SL	424	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
743eeb0b SL	425	IOAPIC_MEM_LENGTH, &ioapic->dev);
79fac95e	426	mutex_unlock(&kvm->slots_lock);
1ae77bad WY	427	if (ret < 0) {
1ae77bad WY	428	kvm->arch.vioapic = NULL;
090b7aff	429	kfree(ioapic);
1ae77bad	430	}
090b7aff GH	431
090b7aff GH	432	return ret;
1fd4f2a5	433	}
75858a84	434
72bb2fcd WY	435	void kvm_ioapic_destroy(struct kvm *kvm)
	436	{
	437	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	438
	439	if (ioapic) {
	440	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
	441	kvm->arch.vioapic = NULL;
	442	kfree(ioapic);
	443	}
	444	}
	445
eba0226b GN	446	int kvm_get_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	447	{
	448	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	449	if (!ioapic)
	450	return -EINVAL;
	451
46a47b1e	452	spin_lock(&ioapic->lock);
eba0226b	453	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
46a47b1e	454	spin_unlock(&ioapic->lock);
eba0226b GN	455	return 0;
	456	}
	457
	458	int kvm_set_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	459	{
	460	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	461	if (!ioapic)
	462	return -EINVAL;
	463
46a47b1e	464	spin_lock(&ioapic->lock);
eba0226b	465	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
46a929bc	466	update_handled_vectors(ioapic);
46a47b1e	467	spin_unlock(&ioapic->lock);
eba0226b GN	468	return 0;
eba0226b GN	469	}