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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
edf88417 | 29 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
30 | #include <linux/kvm.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/smp.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/io.h> | |
36 | #include <asm/processor.h> | |
1fd4f2a5 ED |
37 | #include <asm/page.h> |
38 | #include <asm/current.h> | |
82470196 ZX |
39 | |
40 | #include "ioapic.h" | |
41 | #include "lapic.h" | |
f5244726 | 42 | #include "irq.h" |
82470196 | 43 | |
e25e3ed5 LV |
44 | #if 0 |
45 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
46 | #else | |
1fd4f2a5 | 47 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 48 | #endif |
ff4b9df8 | 49 | static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
1fd4f2a5 ED |
50 | |
51 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
52 | unsigned long addr, | |
53 | unsigned long length) | |
54 | { | |
55 | unsigned long result = 0; | |
56 | ||
57 | switch (ioapic->ioregsel) { | |
58 | case IOAPIC_REG_VERSION: | |
59 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
60 | | (IOAPIC_VERSION_ID & 0xff)); | |
61 | break; | |
62 | ||
63 | case IOAPIC_REG_APIC_ID: | |
64 | case IOAPIC_REG_ARB_ID: | |
65 | result = ((ioapic->id & 0xf) << 24); | |
66 | break; | |
67 | ||
68 | default: | |
69 | { | |
70 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
71 | u64 redir_content; | |
72 | ||
73 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
74 | ||
75 | redir_content = ioapic->redirtbl[redir_index].bits; | |
76 | result = (ioapic->ioregsel & 0x1) ? | |
77 | (redir_content >> 32) & 0xffffffff : | |
78 | redir_content & 0xffffffff; | |
79 | break; | |
80 | } | |
81 | } | |
82 | ||
83 | return result; | |
84 | } | |
85 | ||
86 | static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) | |
87 | { | |
88 | union ioapic_redir_entry *pent; | |
89 | ||
90 | pent = &ioapic->redirtbl[idx]; | |
91 | ||
92 | if (!pent->fields.mask) { | |
ff4b9df8 MT |
93 | int injected = ioapic_deliver(ioapic, idx); |
94 | if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
1fd4f2a5 ED |
95 | pent->fields.remote_irr = 1; |
96 | } | |
97 | if (!pent->fields.trig_mode) | |
98 | ioapic->irr &= ~(1 << idx); | |
99 | } | |
100 | ||
101 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) | |
102 | { | |
103 | unsigned index; | |
104 | ||
105 | switch (ioapic->ioregsel) { | |
106 | case IOAPIC_REG_VERSION: | |
107 | /* Writes are ignored. */ | |
108 | break; | |
109 | ||
110 | case IOAPIC_REG_APIC_ID: | |
111 | ioapic->id = (val >> 24) & 0xf; | |
112 | break; | |
113 | ||
114 | case IOAPIC_REG_ARB_ID: | |
115 | break; | |
116 | ||
117 | default: | |
118 | index = (ioapic->ioregsel - 0x10) >> 1; | |
119 | ||
e25e3ed5 | 120 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
121 | if (index >= IOAPIC_NUM_PINS) |
122 | return; | |
123 | if (ioapic->ioregsel & 1) { | |
124 | ioapic->redirtbl[index].bits &= 0xffffffff; | |
125 | ioapic->redirtbl[index].bits |= (u64) val << 32; | |
126 | } else { | |
127 | ioapic->redirtbl[index].bits &= ~0xffffffffULL; | |
128 | ioapic->redirtbl[index].bits |= (u32) val; | |
129 | ioapic->redirtbl[index].fields.remote_irr = 0; | |
130 | } | |
131 | if (ioapic->irr & (1 << index)) | |
132 | ioapic_service(ioapic, index); | |
133 | break; | |
134 | } | |
135 | } | |
136 | ||
ff4b9df8 | 137 | static int ioapic_inj_irq(struct kvm_ioapic *ioapic, |
8be5453f | 138 | struct kvm_vcpu *vcpu, |
1fd4f2a5 ED |
139 | u8 vector, u8 trig_mode, u8 delivery_mode) |
140 | { | |
e25e3ed5 | 141 | ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode, |
1fd4f2a5 ED |
142 | delivery_mode); |
143 | ||
0c7ac28d ZX |
144 | ASSERT((delivery_mode == IOAPIC_FIXED) || |
145 | (delivery_mode == IOAPIC_LOWEST_PRIORITY)); | |
1fd4f2a5 | 146 | |
ff4b9df8 | 147 | return kvm_apic_set_irq(vcpu, vector, trig_mode); |
1fd4f2a5 ED |
148 | } |
149 | ||
3419ffc8 SY |
150 | static void ioapic_inj_nmi(struct kvm_vcpu *vcpu) |
151 | { | |
152 | kvm_inject_nmi(vcpu); | |
26df99c6 | 153 | kvm_vcpu_kick(vcpu); |
3419ffc8 SY |
154 | } |
155 | ||
1fd4f2a5 ED |
156 | static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest, |
157 | u8 dest_mode) | |
158 | { | |
159 | u32 mask = 0; | |
160 | int i; | |
161 | struct kvm *kvm = ioapic->kvm; | |
162 | struct kvm_vcpu *vcpu; | |
163 | ||
e25e3ed5 | 164 | ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode); |
1fd4f2a5 ED |
165 | |
166 | if (dest_mode == 0) { /* Physical mode. */ | |
167 | if (dest == 0xFF) { /* Broadcast. */ | |
168 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
ad312c7c | 169 | if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic) |
1fd4f2a5 ED |
170 | mask |= 1 << i; |
171 | return mask; | |
172 | } | |
173 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
174 | vcpu = kvm->vcpus[i]; | |
175 | if (!vcpu) | |
176 | continue; | |
ad312c7c ZX |
177 | if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) { |
178 | if (vcpu->arch.apic) | |
1fd4f2a5 ED |
179 | mask = 1 << i; |
180 | break; | |
181 | } | |
182 | } | |
183 | } else if (dest != 0) /* Logical mode, MDA non-zero. */ | |
184 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
185 | vcpu = kvm->vcpus[i]; | |
186 | if (!vcpu) | |
187 | continue; | |
ad312c7c ZX |
188 | if (vcpu->arch.apic && |
189 | kvm_apic_match_logical_addr(vcpu->arch.apic, dest)) | |
1fd4f2a5 ED |
190 | mask |= 1 << vcpu->vcpu_id; |
191 | } | |
e25e3ed5 | 192 | ioapic_debug("mask %x\n", mask); |
1fd4f2a5 ED |
193 | return mask; |
194 | } | |
195 | ||
ff4b9df8 | 196 | static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq) |
1fd4f2a5 ED |
197 | { |
198 | u8 dest = ioapic->redirtbl[irq].fields.dest_id; | |
199 | u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode; | |
200 | u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode; | |
201 | u8 vector = ioapic->redirtbl[irq].fields.vector; | |
202 | u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode; | |
203 | u32 deliver_bitmask; | |
1fd4f2a5 | 204 | struct kvm_vcpu *vcpu; |
ff4b9df8 | 205 | int vcpu_id, r = 0; |
1fd4f2a5 ED |
206 | |
207 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
e25e3ed5 | 208 | "vector=%x trig_mode=%x\n", |
1fd4f2a5 ED |
209 | dest, dest_mode, delivery_mode, vector, trig_mode); |
210 | ||
211 | deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode); | |
212 | if (!deliver_bitmask) { | |
e25e3ed5 | 213 | ioapic_debug("no target on destination\n"); |
ff4b9df8 | 214 | return 0; |
1fd4f2a5 ED |
215 | } |
216 | ||
217 | switch (delivery_mode) { | |
0c7ac28d | 218 | case IOAPIC_LOWEST_PRIORITY: |
8be5453f ZX |
219 | vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector, |
220 | deliver_bitmask); | |
8c35f237 AK |
221 | #ifdef CONFIG_X86 |
222 | if (irq == 0) | |
223 | vcpu = ioapic->kvm->vcpus[0]; | |
224 | #endif | |
8be5453f | 225 | if (vcpu != NULL) |
ff4b9df8 | 226 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
227 | trig_mode, delivery_mode); |
228 | else | |
8be5453f | 229 | ioapic_debug("null lowest prio vcpu: " |
e25e3ed5 | 230 | "mask=%x vector=%x delivery_mode=%x\n", |
0c7ac28d | 231 | deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY); |
1fd4f2a5 | 232 | break; |
0c7ac28d | 233 | case IOAPIC_FIXED: |
8c35f237 AK |
234 | #ifdef CONFIG_X86 |
235 | if (irq == 0) | |
236 | deliver_bitmask = 1; | |
237 | #endif | |
1fd4f2a5 ED |
238 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { |
239 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
240 | continue; | |
241 | deliver_bitmask &= ~(1 << vcpu_id); | |
242 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
243 | if (vcpu) { | |
ff4b9df8 | 244 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
245 | trig_mode, delivery_mode); |
246 | } | |
247 | } | |
248 | break; | |
3419ffc8 SY |
249 | case IOAPIC_NMI: |
250 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { | |
251 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
252 | continue; | |
253 | deliver_bitmask &= ~(1 << vcpu_id); | |
254 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
255 | if (vcpu) | |
256 | ioapic_inj_nmi(vcpu); | |
257 | else | |
258 | ioapic_debug("NMI to vcpu %d failed\n", | |
259 | vcpu->vcpu_id); | |
260 | } | |
261 | break; | |
1fd4f2a5 ED |
262 | default: |
263 | printk(KERN_WARNING "Unsupported delivery mode %d\n", | |
264 | delivery_mode); | |
265 | break; | |
266 | } | |
ff4b9df8 | 267 | return r; |
1fd4f2a5 ED |
268 | } |
269 | ||
270 | void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) | |
271 | { | |
272 | u32 old_irr = ioapic->irr; | |
273 | u32 mask = 1 << irq; | |
274 | union ioapic_redir_entry entry; | |
275 | ||
276 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { | |
277 | entry = ioapic->redirtbl[irq]; | |
278 | level ^= entry.fields.polarity; | |
279 | if (!level) | |
280 | ioapic->irr &= ~mask; | |
281 | else { | |
282 | ioapic->irr |= mask; | |
283 | if ((!entry.fields.trig_mode && old_irr != ioapic->irr) | |
284 | || !entry.fields.remote_irr) | |
285 | ioapic_service(ioapic, irq); | |
286 | } | |
287 | } | |
288 | } | |
289 | ||
f5244726 MT |
290 | static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int gsi, |
291 | int trigger_mode) | |
1fd4f2a5 | 292 | { |
1fd4f2a5 | 293 | union ioapic_redir_entry *ent; |
1fd4f2a5 ED |
294 | |
295 | ent = &ioapic->redirtbl[gsi]; | |
1fd4f2a5 | 296 | |
f5244726 MT |
297 | kvm_notify_acked_irq(ioapic->kvm, gsi); |
298 | ||
299 | if (trigger_mode == IOAPIC_LEVEL_TRIG) { | |
300 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); | |
301 | ent->fields.remote_irr = 0; | |
302 | if (!ent->fields.mask && (ioapic->irr & (1 << gsi))) | |
303 | ioapic_service(ioapic, gsi); | |
304 | } | |
1fd4f2a5 ED |
305 | } |
306 | ||
f5244726 | 307 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode) |
4fa6b9c5 AK |
308 | { |
309 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
310 | int i; | |
311 | ||
312 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
313 | if (ioapic->redirtbl[i].fields.vector == vector) | |
f5244726 | 314 | __kvm_ioapic_update_eoi(ioapic, i, trigger_mode); |
4fa6b9c5 AK |
315 | } |
316 | ||
92760499 LV |
317 | static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr, |
318 | int len, int is_write) | |
1fd4f2a5 ED |
319 | { |
320 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
321 | ||
322 | return ((addr >= ioapic->base_address && | |
323 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
324 | } | |
325 | ||
326 | static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, | |
327 | void *val) | |
328 | { | |
329 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
330 | u32 result; | |
331 | ||
e25e3ed5 | 332 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
333 | ASSERT(!(addr & 0xf)); /* check alignment */ |
334 | ||
335 | addr &= 0xff; | |
336 | switch (addr) { | |
337 | case IOAPIC_REG_SELECT: | |
338 | result = ioapic->ioregsel; | |
339 | break; | |
340 | ||
341 | case IOAPIC_REG_WINDOW: | |
342 | result = ioapic_read_indirect(ioapic, addr, len); | |
343 | break; | |
344 | ||
345 | default: | |
346 | result = 0; | |
347 | break; | |
348 | } | |
349 | switch (len) { | |
350 | case 8: | |
351 | *(u64 *) val = result; | |
352 | break; | |
353 | case 1: | |
354 | case 2: | |
355 | case 4: | |
356 | memcpy(val, (char *)&result, len); | |
357 | break; | |
358 | default: | |
359 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
360 | } | |
361 | } | |
362 | ||
363 | static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, | |
364 | const void *val) | |
365 | { | |
366 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
367 | u32 data; | |
368 | ||
e25e3ed5 LV |
369 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
370 | (void*)addr, len, val); | |
1fd4f2a5 ED |
371 | ASSERT(!(addr & 0xf)); /* check alignment */ |
372 | if (len == 4 || len == 8) | |
373 | data = *(u32 *) val; | |
374 | else { | |
375 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
376 | return; | |
377 | } | |
378 | ||
379 | addr &= 0xff; | |
380 | switch (addr) { | |
381 | case IOAPIC_REG_SELECT: | |
382 | ioapic->ioregsel = data; | |
383 | break; | |
384 | ||
385 | case IOAPIC_REG_WINDOW: | |
386 | ioapic_write_indirect(ioapic, data); | |
387 | break; | |
b1fd3d30 ZX |
388 | #ifdef CONFIG_IA64 |
389 | case IOAPIC_REG_EOI: | |
26815a64 | 390 | kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG); |
b1fd3d30 ZX |
391 | break; |
392 | #endif | |
1fd4f2a5 ED |
393 | |
394 | default: | |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
8c392696 ED |
399 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
400 | { | |
401 | int i; | |
402 | ||
403 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
404 | ioapic->redirtbl[i].fields.mask = 1; | |
405 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
406 | ioapic->ioregsel = 0; | |
407 | ioapic->irr = 0; | |
408 | ioapic->id = 0; | |
409 | } | |
410 | ||
1fd4f2a5 ED |
411 | int kvm_ioapic_init(struct kvm *kvm) |
412 | { | |
413 | struct kvm_ioapic *ioapic; | |
1fd4f2a5 ED |
414 | |
415 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
416 | if (!ioapic) | |
417 | return -ENOMEM; | |
d7deeeb0 | 418 | kvm->arch.vioapic = ioapic; |
8c392696 | 419 | kvm_ioapic_reset(ioapic); |
1fd4f2a5 ED |
420 | ioapic->dev.read = ioapic_mmio_read; |
421 | ioapic->dev.write = ioapic_mmio_write; | |
422 | ioapic->dev.in_range = ioapic_in_range; | |
423 | ioapic->dev.private = ioapic; | |
424 | ioapic->kvm = kvm; | |
425 | kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev); | |
426 | return 0; | |
427 | } |