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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
edf88417 | 29 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
30 | #include <linux/kvm.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/smp.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/io.h> | |
36 | #include <asm/processor.h> | |
1fd4f2a5 ED |
37 | #include <asm/page.h> |
38 | #include <asm/current.h> | |
1000ff8d | 39 | #include <trace/events/kvm.h> |
82470196 ZX |
40 | |
41 | #include "ioapic.h" | |
42 | #include "lapic.h" | |
f5244726 | 43 | #include "irq.h" |
82470196 | 44 | |
e25e3ed5 LV |
45 | #if 0 |
46 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
47 | #else | |
1fd4f2a5 | 48 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 49 | #endif |
ff4b9df8 | 50 | static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
1fd4f2a5 ED |
51 | |
52 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
53 | unsigned long addr, | |
54 | unsigned long length) | |
55 | { | |
56 | unsigned long result = 0; | |
57 | ||
58 | switch (ioapic->ioregsel) { | |
59 | case IOAPIC_REG_VERSION: | |
60 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
61 | | (IOAPIC_VERSION_ID & 0xff)); | |
62 | break; | |
63 | ||
64 | case IOAPIC_REG_APIC_ID: | |
65 | case IOAPIC_REG_ARB_ID: | |
66 | result = ((ioapic->id & 0xf) << 24); | |
67 | break; | |
68 | ||
69 | default: | |
70 | { | |
71 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
72 | u64 redir_content; | |
73 | ||
74 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
75 | ||
76 | redir_content = ioapic->redirtbl[redir_index].bits; | |
77 | result = (ioapic->ioregsel & 0x1) ? | |
78 | (redir_content >> 32) & 0xffffffff : | |
79 | redir_content & 0xffffffff; | |
80 | break; | |
81 | } | |
82 | } | |
83 | ||
84 | return result; | |
85 | } | |
86 | ||
4925663a | 87 | static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) |
1fd4f2a5 | 88 | { |
cf9e4e15 | 89 | union kvm_ioapic_redirect_entry *pent; |
4925663a | 90 | int injected = -1; |
1fd4f2a5 ED |
91 | |
92 | pent = &ioapic->redirtbl[idx]; | |
93 | ||
94 | if (!pent->fields.mask) { | |
4925663a | 95 | injected = ioapic_deliver(ioapic, idx); |
ff4b9df8 | 96 | if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) |
1fd4f2a5 ED |
97 | pent->fields.remote_irr = 1; |
98 | } | |
4925663a GN |
99 | |
100 | return injected; | |
1fd4f2a5 ED |
101 | } |
102 | ||
46a929bc AK |
103 | static void update_handled_vectors(struct kvm_ioapic *ioapic) |
104 | { | |
105 | DECLARE_BITMAP(handled_vectors, 256); | |
106 | int i; | |
107 | ||
108 | memset(handled_vectors, 0, sizeof(handled_vectors)); | |
109 | for (i = 0; i < IOAPIC_NUM_PINS; ++i) | |
110 | __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors); | |
111 | memcpy(ioapic->handled_vectors, handled_vectors, | |
112 | sizeof(handled_vectors)); | |
113 | smp_wmb(); | |
114 | } | |
115 | ||
1fd4f2a5 ED |
116 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
117 | { | |
118 | unsigned index; | |
75858a84 | 119 | bool mask_before, mask_after; |
70f93dae | 120 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
121 | |
122 | switch (ioapic->ioregsel) { | |
123 | case IOAPIC_REG_VERSION: | |
124 | /* Writes are ignored. */ | |
125 | break; | |
126 | ||
127 | case IOAPIC_REG_APIC_ID: | |
128 | ioapic->id = (val >> 24) & 0xf; | |
129 | break; | |
130 | ||
131 | case IOAPIC_REG_ARB_ID: | |
132 | break; | |
133 | ||
134 | default: | |
135 | index = (ioapic->ioregsel - 0x10) >> 1; | |
136 | ||
e25e3ed5 | 137 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
138 | if (index >= IOAPIC_NUM_PINS) |
139 | return; | |
70f93dae GN |
140 | e = &ioapic->redirtbl[index]; |
141 | mask_before = e->fields.mask; | |
1fd4f2a5 | 142 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
143 | e->bits &= 0xffffffff; |
144 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 145 | } else { |
70f93dae GN |
146 | e->bits &= ~0xffffffffULL; |
147 | e->bits |= (u32) val; | |
148 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 149 | } |
46a929bc | 150 | update_handled_vectors(ioapic); |
70f93dae | 151 | mask_after = e->fields.mask; |
75858a84 AK |
152 | if (mask_before != mask_after) |
153 | kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after); | |
70f93dae | 154 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 155 | && ioapic->irr & (1 << index)) |
1fd4f2a5 ED |
156 | ioapic_service(ioapic, index); |
157 | break; | |
158 | } | |
159 | } | |
160 | ||
a53c17d2 GN |
161 | static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq) |
162 | { | |
58c2dde1 GN |
163 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
164 | struct kvm_lapic_irq irqe; | |
a53c17d2 GN |
165 | |
166 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
167 | "vector=%x trig_mode=%x\n", | |
58c2dde1 GN |
168 | entry->fields.dest, entry->fields.dest_mode, |
169 | entry->fields.delivery_mode, entry->fields.vector, | |
170 | entry->fields.trig_mode); | |
171 | ||
172 | irqe.dest_id = entry->fields.dest_id; | |
173 | irqe.vector = entry->fields.vector; | |
174 | irqe.dest_mode = entry->fields.dest_mode; | |
175 | irqe.trig_mode = entry->fields.trig_mode; | |
176 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
177 | irqe.level = 1; | |
178 | irqe.shorthand = 0; | |
a53c17d2 GN |
179 | |
180 | #ifdef CONFIG_X86 | |
181 | /* Always delivery PIT interrupt to vcpu 0 */ | |
182 | if (irq == 0) { | |
58c2dde1 | 183 | irqe.dest_mode = 0; /* Physical mode. */ |
c5af89b6 GN |
184 | /* need to read apic_id from apic regiest since |
185 | * it can be rewritten */ | |
186 | irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id; | |
a53c17d2 GN |
187 | } |
188 | #endif | |
58c2dde1 | 189 | return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe); |
a53c17d2 GN |
190 | } |
191 | ||
4925663a | 192 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) |
1fd4f2a5 ED |
193 | { |
194 | u32 old_irr = ioapic->irr; | |
195 | u32 mask = 1 << irq; | |
cf9e4e15 | 196 | union kvm_ioapic_redirect_entry entry; |
4925663a | 197 | int ret = 1; |
1fd4f2a5 | 198 | |
eba0226b | 199 | mutex_lock(&ioapic->lock); |
1fd4f2a5 ED |
200 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { |
201 | entry = ioapic->redirtbl[irq]; | |
202 | level ^= entry.fields.polarity; | |
203 | if (!level) | |
204 | ioapic->irr &= ~mask; | |
205 | else { | |
b4a2f5e7 | 206 | int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); |
1fd4f2a5 | 207 | ioapic->irr |= mask; |
b4a2f5e7 GN |
208 | if ((edge && old_irr != ioapic->irr) || |
209 | (!edge && !entry.fields.remote_irr)) | |
4925663a | 210 | ret = ioapic_service(ioapic, irq); |
65a82211 GN |
211 | else |
212 | ret = 0; /* report coalesced interrupt */ | |
1fd4f2a5 | 213 | } |
1000ff8d | 214 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); |
1fd4f2a5 | 215 | } |
eba0226b GN |
216 | mutex_unlock(&ioapic->lock); |
217 | ||
4925663a | 218 | return ret; |
1fd4f2a5 ED |
219 | } |
220 | ||
eba0226b GN |
221 | static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector, |
222 | int trigger_mode) | |
1fd4f2a5 | 223 | { |
eba0226b GN |
224 | int i; |
225 | ||
226 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
227 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 228 | |
eba0226b GN |
229 | if (ent->fields.vector != vector) |
230 | continue; | |
1fd4f2a5 | 231 | |
eba0226b GN |
232 | /* |
233 | * We are dropping lock while calling ack notifiers because ack | |
234 | * notifier callbacks for assigned devices call into IOAPIC | |
235 | * recursively. Since remote_irr is cleared only after call | |
236 | * to notifiers if the same vector will be delivered while lock | |
237 | * is dropped it will be put into irr and will be delivered | |
238 | * after ack notifier returns. | |
239 | */ | |
240 | mutex_unlock(&ioapic->lock); | |
241 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); | |
242 | mutex_lock(&ioapic->lock); | |
243 | ||
244 | if (trigger_mode != IOAPIC_LEVEL_TRIG) | |
245 | continue; | |
f5244726 | 246 | |
f5244726 MT |
247 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
248 | ent->fields.remote_irr = 0; | |
eba0226b GN |
249 | if (!ent->fields.mask && (ioapic->irr & (1 << i))) |
250 | ioapic_service(ioapic, i); | |
f5244726 | 251 | } |
1fd4f2a5 ED |
252 | } |
253 | ||
f5244726 | 254 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode) |
4fa6b9c5 AK |
255 | { |
256 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
4fa6b9c5 | 257 | |
46a929bc AK |
258 | smp_rmb(); |
259 | if (!test_bit(vector, ioapic->handled_vectors)) | |
260 | return; | |
eba0226b GN |
261 | mutex_lock(&ioapic->lock); |
262 | __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode); | |
263 | mutex_unlock(&ioapic->lock); | |
4fa6b9c5 AK |
264 | } |
265 | ||
d76685c4 GH |
266 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
267 | { | |
268 | return container_of(dev, struct kvm_ioapic, dev); | |
269 | } | |
270 | ||
bda9020e | 271 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 272 | { |
1fd4f2a5 ED |
273 | return ((addr >= ioapic->base_address && |
274 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
275 | } | |
276 | ||
bda9020e MT |
277 | static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, |
278 | void *val) | |
1fd4f2a5 | 279 | { |
d76685c4 | 280 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 281 | u32 result; |
bda9020e MT |
282 | if (!ioapic_in_range(ioapic, addr)) |
283 | return -EOPNOTSUPP; | |
1fd4f2a5 | 284 | |
e25e3ed5 | 285 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
286 | ASSERT(!(addr & 0xf)); /* check alignment */ |
287 | ||
288 | addr &= 0xff; | |
eba0226b | 289 | mutex_lock(&ioapic->lock); |
1fd4f2a5 ED |
290 | switch (addr) { |
291 | case IOAPIC_REG_SELECT: | |
292 | result = ioapic->ioregsel; | |
293 | break; | |
294 | ||
295 | case IOAPIC_REG_WINDOW: | |
296 | result = ioapic_read_indirect(ioapic, addr, len); | |
297 | break; | |
298 | ||
299 | default: | |
300 | result = 0; | |
301 | break; | |
302 | } | |
eba0226b GN |
303 | mutex_unlock(&ioapic->lock); |
304 | ||
1fd4f2a5 ED |
305 | switch (len) { |
306 | case 8: | |
307 | *(u64 *) val = result; | |
308 | break; | |
309 | case 1: | |
310 | case 2: | |
311 | case 4: | |
312 | memcpy(val, (char *)&result, len); | |
313 | break; | |
314 | default: | |
315 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
316 | } | |
bda9020e | 317 | return 0; |
1fd4f2a5 ED |
318 | } |
319 | ||
bda9020e MT |
320 | static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, |
321 | const void *val) | |
1fd4f2a5 | 322 | { |
d76685c4 | 323 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 324 | u32 data; |
bda9020e MT |
325 | if (!ioapic_in_range(ioapic, addr)) |
326 | return -EOPNOTSUPP; | |
1fd4f2a5 | 327 | |
e25e3ed5 LV |
328 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
329 | (void*)addr, len, val); | |
1fd4f2a5 | 330 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 331 | |
1fd4f2a5 ED |
332 | if (len == 4 || len == 8) |
333 | data = *(u32 *) val; | |
334 | else { | |
335 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
eba0226b | 336 | return 0; |
1fd4f2a5 ED |
337 | } |
338 | ||
339 | addr &= 0xff; | |
eba0226b | 340 | mutex_lock(&ioapic->lock); |
1fd4f2a5 ED |
341 | switch (addr) { |
342 | case IOAPIC_REG_SELECT: | |
343 | ioapic->ioregsel = data; | |
344 | break; | |
345 | ||
346 | case IOAPIC_REG_WINDOW: | |
347 | ioapic_write_indirect(ioapic, data); | |
348 | break; | |
b1fd3d30 ZX |
349 | #ifdef CONFIG_IA64 |
350 | case IOAPIC_REG_EOI: | |
eba0226b | 351 | __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG); |
b1fd3d30 ZX |
352 | break; |
353 | #endif | |
1fd4f2a5 ED |
354 | |
355 | default: | |
356 | break; | |
357 | } | |
eba0226b | 358 | mutex_unlock(&ioapic->lock); |
bda9020e | 359 | return 0; |
1fd4f2a5 ED |
360 | } |
361 | ||
8c392696 ED |
362 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
363 | { | |
364 | int i; | |
365 | ||
366 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
367 | ioapic->redirtbl[i].fields.mask = 1; | |
368 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
369 | ioapic->ioregsel = 0; | |
370 | ioapic->irr = 0; | |
371 | ioapic->id = 0; | |
46a929bc | 372 | update_handled_vectors(ioapic); |
8c392696 ED |
373 | } |
374 | ||
d76685c4 GH |
375 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
376 | .read = ioapic_mmio_read, | |
377 | .write = ioapic_mmio_write, | |
d76685c4 GH |
378 | }; |
379 | ||
1fd4f2a5 ED |
380 | int kvm_ioapic_init(struct kvm *kvm) |
381 | { | |
382 | struct kvm_ioapic *ioapic; | |
090b7aff | 383 | int ret; |
1fd4f2a5 ED |
384 | |
385 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
386 | if (!ioapic) | |
387 | return -ENOMEM; | |
eba0226b | 388 | mutex_init(&ioapic->lock); |
d7deeeb0 | 389 | kvm->arch.vioapic = ioapic; |
8c392696 | 390 | kvm_ioapic_reset(ioapic); |
d76685c4 | 391 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 392 | ioapic->kvm = kvm; |
79fac95e | 393 | mutex_lock(&kvm->slots_lock); |
e93f8a0f | 394 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); |
79fac95e | 395 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
396 | if (ret < 0) { |
397 | kvm->arch.vioapic = NULL; | |
090b7aff | 398 | kfree(ioapic); |
1ae77bad | 399 | } |
090b7aff GH |
400 | |
401 | return ret; | |
1fd4f2a5 | 402 | } |
75858a84 | 403 | |
eba0226b GN |
404 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
405 | { | |
406 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
407 | if (!ioapic) | |
408 | return -EINVAL; | |
409 | ||
410 | mutex_lock(&ioapic->lock); | |
411 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); | |
412 | mutex_unlock(&ioapic->lock); | |
413 | return 0; | |
414 | } | |
415 | ||
416 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
417 | { | |
418 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
419 | if (!ioapic) | |
420 | return -EINVAL; | |
421 | ||
422 | mutex_lock(&ioapic->lock); | |
423 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); | |
46a929bc | 424 | update_handled_vectors(ioapic); |
eba0226b GN |
425 | mutex_unlock(&ioapic->lock); |
426 | return 0; | |
427 | } |