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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
edf88417 | 29 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
30 | #include <linux/kvm.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/smp.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/io.h> | |
36 | #include <asm/processor.h> | |
1fd4f2a5 ED |
37 | #include <asm/page.h> |
38 | #include <asm/current.h> | |
82470196 ZX |
39 | |
40 | #include "ioapic.h" | |
41 | #include "lapic.h" | |
42 | ||
e25e3ed5 LV |
43 | #if 0 |
44 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
45 | #else | |
1fd4f2a5 | 46 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 47 | #endif |
ff4b9df8 | 48 | static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
1fd4f2a5 ED |
49 | |
50 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
51 | unsigned long addr, | |
52 | unsigned long length) | |
53 | { | |
54 | unsigned long result = 0; | |
55 | ||
56 | switch (ioapic->ioregsel) { | |
57 | case IOAPIC_REG_VERSION: | |
58 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
59 | | (IOAPIC_VERSION_ID & 0xff)); | |
60 | break; | |
61 | ||
62 | case IOAPIC_REG_APIC_ID: | |
63 | case IOAPIC_REG_ARB_ID: | |
64 | result = ((ioapic->id & 0xf) << 24); | |
65 | break; | |
66 | ||
67 | default: | |
68 | { | |
69 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
70 | u64 redir_content; | |
71 | ||
72 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
73 | ||
74 | redir_content = ioapic->redirtbl[redir_index].bits; | |
75 | result = (ioapic->ioregsel & 0x1) ? | |
76 | (redir_content >> 32) & 0xffffffff : | |
77 | redir_content & 0xffffffff; | |
78 | break; | |
79 | } | |
80 | } | |
81 | ||
82 | return result; | |
83 | } | |
84 | ||
85 | static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) | |
86 | { | |
87 | union ioapic_redir_entry *pent; | |
88 | ||
89 | pent = &ioapic->redirtbl[idx]; | |
90 | ||
91 | if (!pent->fields.mask) { | |
ff4b9df8 MT |
92 | int injected = ioapic_deliver(ioapic, idx); |
93 | if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
1fd4f2a5 ED |
94 | pent->fields.remote_irr = 1; |
95 | } | |
96 | if (!pent->fields.trig_mode) | |
97 | ioapic->irr &= ~(1 << idx); | |
98 | } | |
99 | ||
100 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) | |
101 | { | |
102 | unsigned index; | |
103 | ||
104 | switch (ioapic->ioregsel) { | |
105 | case IOAPIC_REG_VERSION: | |
106 | /* Writes are ignored. */ | |
107 | break; | |
108 | ||
109 | case IOAPIC_REG_APIC_ID: | |
110 | ioapic->id = (val >> 24) & 0xf; | |
111 | break; | |
112 | ||
113 | case IOAPIC_REG_ARB_ID: | |
114 | break; | |
115 | ||
116 | default: | |
117 | index = (ioapic->ioregsel - 0x10) >> 1; | |
118 | ||
e25e3ed5 | 119 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
120 | if (index >= IOAPIC_NUM_PINS) |
121 | return; | |
122 | if (ioapic->ioregsel & 1) { | |
123 | ioapic->redirtbl[index].bits &= 0xffffffff; | |
124 | ioapic->redirtbl[index].bits |= (u64) val << 32; | |
125 | } else { | |
126 | ioapic->redirtbl[index].bits &= ~0xffffffffULL; | |
127 | ioapic->redirtbl[index].bits |= (u32) val; | |
128 | ioapic->redirtbl[index].fields.remote_irr = 0; | |
129 | } | |
130 | if (ioapic->irr & (1 << index)) | |
131 | ioapic_service(ioapic, index); | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
ff4b9df8 | 136 | static int ioapic_inj_irq(struct kvm_ioapic *ioapic, |
8be5453f | 137 | struct kvm_vcpu *vcpu, |
1fd4f2a5 ED |
138 | u8 vector, u8 trig_mode, u8 delivery_mode) |
139 | { | |
e25e3ed5 | 140 | ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode, |
1fd4f2a5 ED |
141 | delivery_mode); |
142 | ||
0c7ac28d ZX |
143 | ASSERT((delivery_mode == IOAPIC_FIXED) || |
144 | (delivery_mode == IOAPIC_LOWEST_PRIORITY)); | |
1fd4f2a5 | 145 | |
ff4b9df8 | 146 | return kvm_apic_set_irq(vcpu, vector, trig_mode); |
1fd4f2a5 ED |
147 | } |
148 | ||
149 | static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest, | |
150 | u8 dest_mode) | |
151 | { | |
152 | u32 mask = 0; | |
153 | int i; | |
154 | struct kvm *kvm = ioapic->kvm; | |
155 | struct kvm_vcpu *vcpu; | |
156 | ||
e25e3ed5 | 157 | ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode); |
1fd4f2a5 ED |
158 | |
159 | if (dest_mode == 0) { /* Physical mode. */ | |
160 | if (dest == 0xFF) { /* Broadcast. */ | |
161 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
ad312c7c | 162 | if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic) |
1fd4f2a5 ED |
163 | mask |= 1 << i; |
164 | return mask; | |
165 | } | |
166 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
167 | vcpu = kvm->vcpus[i]; | |
168 | if (!vcpu) | |
169 | continue; | |
ad312c7c ZX |
170 | if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) { |
171 | if (vcpu->arch.apic) | |
1fd4f2a5 ED |
172 | mask = 1 << i; |
173 | break; | |
174 | } | |
175 | } | |
176 | } else if (dest != 0) /* Logical mode, MDA non-zero. */ | |
177 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
178 | vcpu = kvm->vcpus[i]; | |
179 | if (!vcpu) | |
180 | continue; | |
ad312c7c ZX |
181 | if (vcpu->arch.apic && |
182 | kvm_apic_match_logical_addr(vcpu->arch.apic, dest)) | |
1fd4f2a5 ED |
183 | mask |= 1 << vcpu->vcpu_id; |
184 | } | |
e25e3ed5 | 185 | ioapic_debug("mask %x\n", mask); |
1fd4f2a5 ED |
186 | return mask; |
187 | } | |
188 | ||
ff4b9df8 | 189 | static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq) |
1fd4f2a5 ED |
190 | { |
191 | u8 dest = ioapic->redirtbl[irq].fields.dest_id; | |
192 | u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode; | |
193 | u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode; | |
194 | u8 vector = ioapic->redirtbl[irq].fields.vector; | |
195 | u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode; | |
196 | u32 deliver_bitmask; | |
1fd4f2a5 | 197 | struct kvm_vcpu *vcpu; |
ff4b9df8 | 198 | int vcpu_id, r = 0; |
1fd4f2a5 ED |
199 | |
200 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
e25e3ed5 | 201 | "vector=%x trig_mode=%x\n", |
1fd4f2a5 ED |
202 | dest, dest_mode, delivery_mode, vector, trig_mode); |
203 | ||
204 | deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode); | |
205 | if (!deliver_bitmask) { | |
e25e3ed5 | 206 | ioapic_debug("no target on destination\n"); |
ff4b9df8 | 207 | return 0; |
1fd4f2a5 ED |
208 | } |
209 | ||
210 | switch (delivery_mode) { | |
0c7ac28d | 211 | case IOAPIC_LOWEST_PRIORITY: |
8be5453f ZX |
212 | vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector, |
213 | deliver_bitmask); | |
8c35f237 AK |
214 | #ifdef CONFIG_X86 |
215 | if (irq == 0) | |
216 | vcpu = ioapic->kvm->vcpus[0]; | |
217 | #endif | |
8be5453f | 218 | if (vcpu != NULL) |
ff4b9df8 | 219 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
220 | trig_mode, delivery_mode); |
221 | else | |
8be5453f | 222 | ioapic_debug("null lowest prio vcpu: " |
e25e3ed5 | 223 | "mask=%x vector=%x delivery_mode=%x\n", |
0c7ac28d | 224 | deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY); |
1fd4f2a5 | 225 | break; |
0c7ac28d | 226 | case IOAPIC_FIXED: |
8c35f237 AK |
227 | #ifdef CONFIG_X86 |
228 | if (irq == 0) | |
229 | deliver_bitmask = 1; | |
230 | #endif | |
1fd4f2a5 ED |
231 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { |
232 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
233 | continue; | |
234 | deliver_bitmask &= ~(1 << vcpu_id); | |
235 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
236 | if (vcpu) { | |
ff4b9df8 | 237 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
238 | trig_mode, delivery_mode); |
239 | } | |
240 | } | |
241 | break; | |
242 | ||
243 | /* TODO: NMI */ | |
244 | default: | |
245 | printk(KERN_WARNING "Unsupported delivery mode %d\n", | |
246 | delivery_mode); | |
247 | break; | |
248 | } | |
ff4b9df8 | 249 | return r; |
1fd4f2a5 ED |
250 | } |
251 | ||
252 | void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) | |
253 | { | |
254 | u32 old_irr = ioapic->irr; | |
255 | u32 mask = 1 << irq; | |
256 | union ioapic_redir_entry entry; | |
257 | ||
258 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { | |
259 | entry = ioapic->redirtbl[irq]; | |
260 | level ^= entry.fields.polarity; | |
261 | if (!level) | |
262 | ioapic->irr &= ~mask; | |
263 | else { | |
264 | ioapic->irr |= mask; | |
265 | if ((!entry.fields.trig_mode && old_irr != ioapic->irr) | |
266 | || !entry.fields.remote_irr) | |
267 | ioapic_service(ioapic, irq); | |
268 | } | |
269 | } | |
270 | } | |
271 | ||
4fa6b9c5 | 272 | static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int gsi) |
1fd4f2a5 | 273 | { |
1fd4f2a5 | 274 | union ioapic_redir_entry *ent; |
1fd4f2a5 ED |
275 | |
276 | ent = &ioapic->redirtbl[gsi]; | |
277 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); | |
278 | ||
279 | ent->fields.remote_irr = 0; | |
280 | if (!ent->fields.mask && (ioapic->irr & (1 << gsi))) | |
35baff25 | 281 | ioapic_service(ioapic, gsi); |
1fd4f2a5 ED |
282 | } |
283 | ||
4fa6b9c5 AK |
284 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector) |
285 | { | |
286 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
287 | int i; | |
288 | ||
289 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
290 | if (ioapic->redirtbl[i].fields.vector == vector) | |
291 | __kvm_ioapic_update_eoi(ioapic, i); | |
292 | } | |
293 | ||
1fd4f2a5 ED |
294 | static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr) |
295 | { | |
296 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
297 | ||
298 | return ((addr >= ioapic->base_address && | |
299 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
300 | } | |
301 | ||
302 | static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, | |
303 | void *val) | |
304 | { | |
305 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
306 | u32 result; | |
307 | ||
e25e3ed5 | 308 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
309 | ASSERT(!(addr & 0xf)); /* check alignment */ |
310 | ||
311 | addr &= 0xff; | |
312 | switch (addr) { | |
313 | case IOAPIC_REG_SELECT: | |
314 | result = ioapic->ioregsel; | |
315 | break; | |
316 | ||
317 | case IOAPIC_REG_WINDOW: | |
318 | result = ioapic_read_indirect(ioapic, addr, len); | |
319 | break; | |
320 | ||
321 | default: | |
322 | result = 0; | |
323 | break; | |
324 | } | |
325 | switch (len) { | |
326 | case 8: | |
327 | *(u64 *) val = result; | |
328 | break; | |
329 | case 1: | |
330 | case 2: | |
331 | case 4: | |
332 | memcpy(val, (char *)&result, len); | |
333 | break; | |
334 | default: | |
335 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
336 | } | |
337 | } | |
338 | ||
339 | static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, | |
340 | const void *val) | |
341 | { | |
342 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
343 | u32 data; | |
344 | ||
e25e3ed5 LV |
345 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
346 | (void*)addr, len, val); | |
1fd4f2a5 ED |
347 | ASSERT(!(addr & 0xf)); /* check alignment */ |
348 | if (len == 4 || len == 8) | |
349 | data = *(u32 *) val; | |
350 | else { | |
351 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
352 | return; | |
353 | } | |
354 | ||
355 | addr &= 0xff; | |
356 | switch (addr) { | |
357 | case IOAPIC_REG_SELECT: | |
358 | ioapic->ioregsel = data; | |
359 | break; | |
360 | ||
361 | case IOAPIC_REG_WINDOW: | |
362 | ioapic_write_indirect(ioapic, data); | |
363 | break; | |
b1fd3d30 ZX |
364 | #ifdef CONFIG_IA64 |
365 | case IOAPIC_REG_EOI: | |
0eb8f498 | 366 | kvm_ioapic_update_eoi(ioapic->kvm, data); |
b1fd3d30 ZX |
367 | break; |
368 | #endif | |
1fd4f2a5 ED |
369 | |
370 | default: | |
371 | break; | |
372 | } | |
373 | } | |
374 | ||
8c392696 ED |
375 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
376 | { | |
377 | int i; | |
378 | ||
379 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
380 | ioapic->redirtbl[i].fields.mask = 1; | |
381 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
382 | ioapic->ioregsel = 0; | |
383 | ioapic->irr = 0; | |
384 | ioapic->id = 0; | |
385 | } | |
386 | ||
1fd4f2a5 ED |
387 | int kvm_ioapic_init(struct kvm *kvm) |
388 | { | |
389 | struct kvm_ioapic *ioapic; | |
1fd4f2a5 ED |
390 | |
391 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
392 | if (!ioapic) | |
393 | return -ENOMEM; | |
d7deeeb0 | 394 | kvm->arch.vioapic = ioapic; |
8c392696 | 395 | kvm_ioapic_reset(ioapic); |
1fd4f2a5 ED |
396 | ioapic->dev.read = ioapic_mmio_read; |
397 | ioapic->dev.write = ioapic_mmio_write; | |
398 | ioapic->dev.in_range = ioapic_in_range; | |
399 | ioapic->dev.private = ioapic; | |
400 | ioapic->kvm = kvm; | |
401 | kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev); | |
402 | return 0; | |
403 | } |