[mirror_ubuntu-bionic-kernel.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>
#include <trace/events/kvm.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}

	return injected;
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;
	union kvm_ioapic_redirect_entry *e;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		e = &ioapic->redirtbl[index];
		mask_before = e->fields.mask;
		if (ioapic->ioregsel & 1) {
			e->bits &= 0xffffffff;
			e->bits |= (u64) val << 32;
		} else {
			e->bits &= ~0xffffffffULL;
			e->bits |= (u32) val;
			e->fields.remote_irr = 0;
		}
		mask_after = e->fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;

#ifdef CONFIG_X86
	/* Always delivery PIT interrupt to vcpu 0 */
	if (irq == 0) {
		irqe.dest_mode = 0; /* Physical mode. */
		/* need to read apic_id from apic regiest since
		 * it can be rewritten */
		irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
	}
#endif
	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
{
	u32 old_irr = ioapic->irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret = 1;

	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
		entry = ioapic->redirtbl[irq];
		level ^= entry.fields.polarity;
		if (!level)
			ioapic->irr &= ~mask;
		else {
			int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
			ioapic->irr |= mask;
			if ((edge && old_irr != ioapic->irr) ||
			    (!edge && !entry.fields.remote_irr))
				ret = ioapic_service(ioapic, irq);
			else
				ret = 0; /* report coalesced interrupt */
		}
		trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	}
	return ret;
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
				    int trigger_mode)
{
	union kvm_ioapic_redirect_entry *ent;

	ent = &ioapic->redirtbl[pin];

	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);

	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
			ioapic_service(ioapic, pin);
	}
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		if (ioapic->redirtbl[i].fields.vector == vector)
			__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
}

static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_ioapic, dev);
}

static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
{
	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			    void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 result;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	mutex_lock(&ioapic->kvm->irq_lock);
	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
	mutex_unlock(&ioapic->kvm->irq_lock);
	return 0;
}

static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			     const void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 data;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */

	mutex_lock(&ioapic->kvm->irq_lock);
	if (len == 4 || len == 8)
		data = *(u32 *) val;
	else {
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		goto unlock;
	}

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data;
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
unlock:
	mutex_unlock(&ioapic->kvm->irq_lock);
	return 0;
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
}

static const struct kvm_io_device_ops ioapic_mmio_ops = {
	.read     = ioapic_mmio_read,
	.write    = ioapic_mmio_write,
};

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;
	int ret;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
	ioapic->kvm = kvm;
	ret = kvm_io_bus_register_dev(kvm, &kvm->mmio_bus, &ioapic->dev);
	if (ret < 0)
		kfree(ioapic);

	return ret;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
	2	* Copyright (C) 2001 MandrakeSoft S.A.
	3	*
	4	* MandrakeSoft S.A.
	5	* 43, rue d'Aboukir
	6	* 75002 Paris - France
	7	* http://www.linux-mandrake.com/
	8	* http://www.mandrakesoft.com/
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Yunhong Jiang <yunhong.jiang@intel.com>
	25	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	26	* Based on Xen 3.1 code.
	27	*/
	28
edf88417	29	#include <linux/kvm_host.h>
1fd4f2a5 ED	30	#include <linux/kvm.h>
	31	#include <linux/mm.h>
	32	#include <linux/highmem.h>
	33	#include <linux/smp.h>
	34	#include <linux/hrtimer.h>
	35	#include <linux/io.h>
	36	#include <asm/processor.h>
1fd4f2a5 ED	37	#include <asm/page.h>
1fd4f2a5 ED	38	#include <asm/current.h>
1000ff8d	39	#include <trace/events/kvm.h>
82470196 ZX	40
	41	#include "ioapic.h"
	42	#include "lapic.h"
f5244726	43	#include "irq.h"
82470196	44
e25e3ed5 LV	45	#if 0
	46	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	47	#else
1fd4f2a5	48	#define ioapic_debug(fmt, arg...)
e25e3ed5	49	#endif
ff4b9df8	50	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	51
	52	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	53	unsigned long addr,
	54	unsigned long length)
	55	{
	56	unsigned long result = 0;
	57
	58	switch (ioapic->ioregsel) {
	59	case IOAPIC_REG_VERSION:
	60	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	61	\| (IOAPIC_VERSION_ID & 0xff));
	62	break;
	63
	64	case IOAPIC_REG_APIC_ID:
	65	case IOAPIC_REG_ARB_ID:
	66	result = ((ioapic->id & 0xf) << 24);
	67	break;
	68
	69	default:
	70	{
	71	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	72	u64 redir_content;
	73
	74	ASSERT(redir_index < IOAPIC_NUM_PINS);
	75
	76	redir_content = ioapic->redirtbl[redir_index].bits;
	77	result = (ioapic->ioregsel & 0x1) ?
	78	(redir_content >> 32) & 0xffffffff :
	79	redir_content & 0xffffffff;
	80	break;
	81	}
	82	}
	83
	84	return result;
	85	}
	86
4925663a	87	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	88	{
cf9e4e15	89	union kvm_ioapic_redirect_entry *pent;
4925663a	90	int injected = -1;
1fd4f2a5 ED	91
	92	pent = &ioapic->redirtbl[idx];
	93
	94	if (!pent->fields.mask) {
4925663a	95	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	96	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	97	pent->fields.remote_irr = 1;
1fd4f2a5 ED	98	}
4925663a GN	99
4925663a GN	100	return injected;
1fd4f2a5 ED	101	}
	102
	103	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	104	{
	105	unsigned index;
75858a84	106	bool mask_before, mask_after;
70f93dae	107	union kvm_ioapic_redirect_entry *e;
1fd4f2a5 ED	108
	109	switch (ioapic->ioregsel) {
	110	case IOAPIC_REG_VERSION:
	111	/* Writes are ignored. */
	112	break;
	113
	114	case IOAPIC_REG_APIC_ID:
	115	ioapic->id = (val >> 24) & 0xf;
	116	break;
	117
	118	case IOAPIC_REG_ARB_ID:
	119	break;
	120
	121	default:
	122	index = (ioapic->ioregsel - 0x10) >> 1;
	123
e25e3ed5	124	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	125	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	126	return;
70f93dae GN	127	e = &ioapic->redirtbl[index];
70f93dae GN	128	mask_before = e->fields.mask;
1fd4f2a5	129	if (ioapic->ioregsel & 1) {
70f93dae GN	130	e->bits &= 0xffffffff;
70f93dae GN	131	e->bits \|= (u64) val << 32;
1fd4f2a5	132	} else {
70f93dae GN	133	e->bits &= ~0xffffffffULL;
	134	e->bits \|= (u32) val;
	135	e->fields.remote_irr = 0;
1fd4f2a5	136	}
70f93dae	137	mask_after = e->fields.mask;
75858a84 AK	138	if (mask_before != mask_after)
75858a84 AK	139	kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
70f93dae	140	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7	141	&& ioapic->irr & (1 << index))
1fd4f2a5 ED	142	ioapic_service(ioapic, index);
	143	break;
	144	}
	145	}
	146
a53c17d2 GN	147	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
a53c17d2 GN	148	{
58c2dde1 GN	149	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	150	struct kvm_lapic_irq irqe;
a53c17d2 GN	151
	152	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
	153	"vector=%x trig_mode=%x\n",
58c2dde1 GN	154	entry->fields.dest, entry->fields.dest_mode,
	155	entry->fields.delivery_mode, entry->fields.vector,
	156	entry->fields.trig_mode);
	157
	158	irqe.dest_id = entry->fields.dest_id;
	159	irqe.vector = entry->fields.vector;
	160	irqe.dest_mode = entry->fields.dest_mode;
	161	irqe.trig_mode = entry->fields.trig_mode;
	162	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	163	irqe.level = 1;
	164	irqe.shorthand = 0;
a53c17d2 GN	165
	166	#ifdef CONFIG_X86
	167	/* Always delivery PIT interrupt to vcpu 0 */
	168	if (irq == 0) {
58c2dde1	169	irqe.dest_mode = 0; /* Physical mode. */
c5af89b6 GN	170	/* need to read apic_id from apic regiest since
	171	* it can be rewritten */
	172	irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
a53c17d2 GN	173	}
a53c17d2 GN	174	#endif
58c2dde1	175	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
a53c17d2 GN	176	}
a53c17d2 GN	177
4925663a	178	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
1fd4f2a5 ED	179	{
	180	u32 old_irr = ioapic->irr;
	181	u32 mask = 1 << irq;
cf9e4e15	182	union kvm_ioapic_redirect_entry entry;
4925663a	183	int ret = 1;
1fd4f2a5 ED	184
	185	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
	186	entry = ioapic->redirtbl[irq];
	187	level ^= entry.fields.polarity;
	188	if (!level)
	189	ioapic->irr &= ~mask;
	190	else {
b4a2f5e7	191	int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
1fd4f2a5	192	ioapic->irr \|= mask;
b4a2f5e7 GN	193	if ((edge && old_irr != ioapic->irr) \|\|
b4a2f5e7 GN	194	(!edge && !entry.fields.remote_irr))
4925663a	195	ret = ioapic_service(ioapic, irq);
65a82211 GN	196	else
65a82211 GN	197	ret = 0; /* report coalesced interrupt */
1fd4f2a5	198	}
1000ff8d	199	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
1fd4f2a5	200	}
4925663a	201	return ret;
1fd4f2a5 ED	202	}
1fd4f2a5 ED	203
44882eed	204	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
f5244726	205	int trigger_mode)
1fd4f2a5	206	{
cf9e4e15	207	union kvm_ioapic_redirect_entry *ent;
1fd4f2a5	208
44882eed	209	ent = &ioapic->redirtbl[pin];
1fd4f2a5	210
44882eed	211	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
f5244726 MT	212
	213	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
	214	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
	215	ent->fields.remote_irr = 0;
44882eed MT	216	if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
44882eed MT	217	ioapic_service(ioapic, pin);
f5244726	218	}
1fd4f2a5 ED	219	}
1fd4f2a5 ED	220
f5244726	221	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	222	{
	223	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	224	int i;
	225
	226	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	227	if (ioapic->redirtbl[i].fields.vector == vector)
f5244726	228	__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
4fa6b9c5 AK	229	}
4fa6b9c5 AK	230
d76685c4 GH	231	static inline struct kvm_ioapic to_ioapic(struct kvm_io_device dev)
	232	{
	233	return container_of(dev, struct kvm_ioapic, dev);
	234	}
	235
bda9020e	236	static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
1fd4f2a5	237	{
1fd4f2a5 ED	238	return ((addr >= ioapic->base_address &&
	239	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	240	}
	241
bda9020e MT	242	static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	243	void *val)
1fd4f2a5	244	{
d76685c4	245	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	246	u32 result;
bda9020e MT	247	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	248	return -EOPNOTSUPP;
1fd4f2a5	249
e25e3ed5	250	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	251	ASSERT(!(addr & 0xf)); /* check alignment */
1fd4f2a5 ED	252
60eead79	253	mutex_lock(&ioapic->kvm->irq_lock);
1fd4f2a5 ED	254	addr &= 0xff;
	255	switch (addr) {
	256	case IOAPIC_REG_SELECT:
	257	result = ioapic->ioregsel;
	258	break;
	259
	260	case IOAPIC_REG_WINDOW:
	261	result = ioapic_read_indirect(ioapic, addr, len);
	262	break;
	263
	264	default:
	265	result = 0;
	266	break;
	267	}
	268	switch (len) {
	269	case 8:
	270	(u64 ) val = result;
	271	break;
	272	case 1:
	273	case 2:
	274	case 4:
	275	memcpy(val, (char *)&result, len);
	276	break;
	277	default:
	278	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	279	}
60eead79	280	mutex_unlock(&ioapic->kvm->irq_lock);
bda9020e	281	return 0;
1fd4f2a5 ED	282	}
1fd4f2a5 ED	283
bda9020e MT	284	static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	285	const void *val)
1fd4f2a5	286	{
d76685c4	287	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	288	u32 data;
bda9020e MT	289	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	290	return -EOPNOTSUPP;
1fd4f2a5	291
e25e3ed5 LV	292	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	293	(void*)addr, len, val);
1fd4f2a5	294	ASSERT(!(addr & 0xf)); /* check alignment */
60eead79 MT	295
60eead79 MT	296	mutex_lock(&ioapic->kvm->irq_lock);
1fd4f2a5 ED	297	if (len == 4 \|\| len == 8)
	298	data = (u32 ) val;
	299	else {
	300	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
27c4ba60	301	goto unlock;
1fd4f2a5 ED	302	}
	303
	304	addr &= 0xff;
	305	switch (addr) {
	306	case IOAPIC_REG_SELECT:
	307	ioapic->ioregsel = data;
	308	break;
	309
	310	case IOAPIC_REG_WINDOW:
	311	ioapic_write_indirect(ioapic, data);
	312	break;
b1fd3d30 ZX	313	#ifdef CONFIG_IA64
b1fd3d30 ZX	314	case IOAPIC_REG_EOI:
26815a64	315	kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	316	break;
b1fd3d30 ZX	317	#endif
1fd4f2a5 ED	318
	319	default:
	320	break;
	321	}
27c4ba60	322	unlock:
60eead79	323	mutex_unlock(&ioapic->kvm->irq_lock);
bda9020e	324	return 0;
1fd4f2a5 ED	325	}
1fd4f2a5 ED	326
8c392696 ED	327	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	328	{
	329	int i;
	330
	331	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	332	ioapic->redirtbl[i].fields.mask = 1;
	333	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	334	ioapic->ioregsel = 0;
	335	ioapic->irr = 0;
	336	ioapic->id = 0;
	337	}
	338
d76685c4 GH	339	static const struct kvm_io_device_ops ioapic_mmio_ops = {
	340	.read = ioapic_mmio_read,
	341	.write = ioapic_mmio_write,
d76685c4 GH	342	};
d76685c4 GH	343
1fd4f2a5 ED	344	int kvm_ioapic_init(struct kvm *kvm)
	345	{
	346	struct kvm_ioapic *ioapic;
090b7aff	347	int ret;
1fd4f2a5 ED	348
	349	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	350	if (!ioapic)
	351	return -ENOMEM;
d7deeeb0	352	kvm->arch.vioapic = ioapic;
8c392696	353	kvm_ioapic_reset(ioapic);
d76685c4	354	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
1fd4f2a5	355	ioapic->kvm = kvm;
090b7aff GH	356	ret = kvm_io_bus_register_dev(kvm, &kvm->mmio_bus, &ioapic->dev);
	357	if (ret < 0)
	358	kfree(ioapic);
	359
	360	return ret;
1fd4f2a5	361	}
75858a84	362