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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
edf88417 | 29 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
30 | #include <linux/kvm.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/smp.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/io.h> | |
36 | #include <asm/processor.h> | |
1fd4f2a5 ED |
37 | #include <asm/page.h> |
38 | #include <asm/current.h> | |
82470196 ZX |
39 | |
40 | #include "ioapic.h" | |
41 | #include "lapic.h" | |
42 | ||
e25e3ed5 LV |
43 | #if 0 |
44 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
45 | #else | |
1fd4f2a5 | 46 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 47 | #endif |
ff4b9df8 | 48 | static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
1fd4f2a5 ED |
49 | |
50 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
51 | unsigned long addr, | |
52 | unsigned long length) | |
53 | { | |
54 | unsigned long result = 0; | |
55 | ||
56 | switch (ioapic->ioregsel) { | |
57 | case IOAPIC_REG_VERSION: | |
58 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
59 | | (IOAPIC_VERSION_ID & 0xff)); | |
60 | break; | |
61 | ||
62 | case IOAPIC_REG_APIC_ID: | |
63 | case IOAPIC_REG_ARB_ID: | |
64 | result = ((ioapic->id & 0xf) << 24); | |
65 | break; | |
66 | ||
67 | default: | |
68 | { | |
69 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
70 | u64 redir_content; | |
71 | ||
72 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
73 | ||
74 | redir_content = ioapic->redirtbl[redir_index].bits; | |
75 | result = (ioapic->ioregsel & 0x1) ? | |
76 | (redir_content >> 32) & 0xffffffff : | |
77 | redir_content & 0xffffffff; | |
78 | break; | |
79 | } | |
80 | } | |
81 | ||
82 | return result; | |
83 | } | |
84 | ||
85 | static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) | |
86 | { | |
87 | union ioapic_redir_entry *pent; | |
88 | ||
89 | pent = &ioapic->redirtbl[idx]; | |
90 | ||
91 | if (!pent->fields.mask) { | |
ff4b9df8 MT |
92 | int injected = ioapic_deliver(ioapic, idx); |
93 | if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
1fd4f2a5 ED |
94 | pent->fields.remote_irr = 1; |
95 | } | |
96 | if (!pent->fields.trig_mode) | |
97 | ioapic->irr &= ~(1 << idx); | |
98 | } | |
99 | ||
100 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) | |
101 | { | |
102 | unsigned index; | |
103 | ||
104 | switch (ioapic->ioregsel) { | |
105 | case IOAPIC_REG_VERSION: | |
106 | /* Writes are ignored. */ | |
107 | break; | |
108 | ||
109 | case IOAPIC_REG_APIC_ID: | |
110 | ioapic->id = (val >> 24) & 0xf; | |
111 | break; | |
112 | ||
113 | case IOAPIC_REG_ARB_ID: | |
114 | break; | |
115 | ||
116 | default: | |
117 | index = (ioapic->ioregsel - 0x10) >> 1; | |
118 | ||
e25e3ed5 | 119 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
120 | if (index >= IOAPIC_NUM_PINS) |
121 | return; | |
122 | if (ioapic->ioregsel & 1) { | |
123 | ioapic->redirtbl[index].bits &= 0xffffffff; | |
124 | ioapic->redirtbl[index].bits |= (u64) val << 32; | |
125 | } else { | |
126 | ioapic->redirtbl[index].bits &= ~0xffffffffULL; | |
127 | ioapic->redirtbl[index].bits |= (u32) val; | |
128 | ioapic->redirtbl[index].fields.remote_irr = 0; | |
129 | } | |
130 | if (ioapic->irr & (1 << index)) | |
131 | ioapic_service(ioapic, index); | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
ff4b9df8 | 136 | static int ioapic_inj_irq(struct kvm_ioapic *ioapic, |
8be5453f | 137 | struct kvm_vcpu *vcpu, |
1fd4f2a5 ED |
138 | u8 vector, u8 trig_mode, u8 delivery_mode) |
139 | { | |
e25e3ed5 | 140 | ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode, |
1fd4f2a5 ED |
141 | delivery_mode); |
142 | ||
0c7ac28d ZX |
143 | ASSERT((delivery_mode == IOAPIC_FIXED) || |
144 | (delivery_mode == IOAPIC_LOWEST_PRIORITY)); | |
1fd4f2a5 | 145 | |
ff4b9df8 | 146 | return kvm_apic_set_irq(vcpu, vector, trig_mode); |
1fd4f2a5 ED |
147 | } |
148 | ||
3419ffc8 SY |
149 | static void ioapic_inj_nmi(struct kvm_vcpu *vcpu) |
150 | { | |
151 | kvm_inject_nmi(vcpu); | |
152 | } | |
153 | ||
1fd4f2a5 ED |
154 | static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest, |
155 | u8 dest_mode) | |
156 | { | |
157 | u32 mask = 0; | |
158 | int i; | |
159 | struct kvm *kvm = ioapic->kvm; | |
160 | struct kvm_vcpu *vcpu; | |
161 | ||
e25e3ed5 | 162 | ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode); |
1fd4f2a5 ED |
163 | |
164 | if (dest_mode == 0) { /* Physical mode. */ | |
165 | if (dest == 0xFF) { /* Broadcast. */ | |
166 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
ad312c7c | 167 | if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic) |
1fd4f2a5 ED |
168 | mask |= 1 << i; |
169 | return mask; | |
170 | } | |
171 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
172 | vcpu = kvm->vcpus[i]; | |
173 | if (!vcpu) | |
174 | continue; | |
ad312c7c ZX |
175 | if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) { |
176 | if (vcpu->arch.apic) | |
1fd4f2a5 ED |
177 | mask = 1 << i; |
178 | break; | |
179 | } | |
180 | } | |
181 | } else if (dest != 0) /* Logical mode, MDA non-zero. */ | |
182 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
183 | vcpu = kvm->vcpus[i]; | |
184 | if (!vcpu) | |
185 | continue; | |
ad312c7c ZX |
186 | if (vcpu->arch.apic && |
187 | kvm_apic_match_logical_addr(vcpu->arch.apic, dest)) | |
1fd4f2a5 ED |
188 | mask |= 1 << vcpu->vcpu_id; |
189 | } | |
e25e3ed5 | 190 | ioapic_debug("mask %x\n", mask); |
1fd4f2a5 ED |
191 | return mask; |
192 | } | |
193 | ||
ff4b9df8 | 194 | static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq) |
1fd4f2a5 ED |
195 | { |
196 | u8 dest = ioapic->redirtbl[irq].fields.dest_id; | |
197 | u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode; | |
198 | u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode; | |
199 | u8 vector = ioapic->redirtbl[irq].fields.vector; | |
200 | u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode; | |
201 | u32 deliver_bitmask; | |
1fd4f2a5 | 202 | struct kvm_vcpu *vcpu; |
ff4b9df8 | 203 | int vcpu_id, r = 0; |
1fd4f2a5 ED |
204 | |
205 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
e25e3ed5 | 206 | "vector=%x trig_mode=%x\n", |
1fd4f2a5 ED |
207 | dest, dest_mode, delivery_mode, vector, trig_mode); |
208 | ||
209 | deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode); | |
210 | if (!deliver_bitmask) { | |
e25e3ed5 | 211 | ioapic_debug("no target on destination\n"); |
ff4b9df8 | 212 | return 0; |
1fd4f2a5 ED |
213 | } |
214 | ||
215 | switch (delivery_mode) { | |
0c7ac28d | 216 | case IOAPIC_LOWEST_PRIORITY: |
8be5453f ZX |
217 | vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector, |
218 | deliver_bitmask); | |
8c35f237 AK |
219 | #ifdef CONFIG_X86 |
220 | if (irq == 0) | |
221 | vcpu = ioapic->kvm->vcpus[0]; | |
222 | #endif | |
8be5453f | 223 | if (vcpu != NULL) |
ff4b9df8 | 224 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
225 | trig_mode, delivery_mode); |
226 | else | |
8be5453f | 227 | ioapic_debug("null lowest prio vcpu: " |
e25e3ed5 | 228 | "mask=%x vector=%x delivery_mode=%x\n", |
0c7ac28d | 229 | deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY); |
1fd4f2a5 | 230 | break; |
0c7ac28d | 231 | case IOAPIC_FIXED: |
8c35f237 AK |
232 | #ifdef CONFIG_X86 |
233 | if (irq == 0) | |
234 | deliver_bitmask = 1; | |
235 | #endif | |
1fd4f2a5 ED |
236 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { |
237 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
238 | continue; | |
239 | deliver_bitmask &= ~(1 << vcpu_id); | |
240 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
241 | if (vcpu) { | |
ff4b9df8 | 242 | r = ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
243 | trig_mode, delivery_mode); |
244 | } | |
245 | } | |
246 | break; | |
3419ffc8 SY |
247 | case IOAPIC_NMI: |
248 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { | |
249 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
250 | continue; | |
251 | deliver_bitmask &= ~(1 << vcpu_id); | |
252 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
253 | if (vcpu) | |
254 | ioapic_inj_nmi(vcpu); | |
255 | else | |
256 | ioapic_debug("NMI to vcpu %d failed\n", | |
257 | vcpu->vcpu_id); | |
258 | } | |
259 | break; | |
1fd4f2a5 ED |
260 | default: |
261 | printk(KERN_WARNING "Unsupported delivery mode %d\n", | |
262 | delivery_mode); | |
263 | break; | |
264 | } | |
ff4b9df8 | 265 | return r; |
1fd4f2a5 ED |
266 | } |
267 | ||
268 | void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) | |
269 | { | |
270 | u32 old_irr = ioapic->irr; | |
271 | u32 mask = 1 << irq; | |
272 | union ioapic_redir_entry entry; | |
273 | ||
274 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { | |
275 | entry = ioapic->redirtbl[irq]; | |
276 | level ^= entry.fields.polarity; | |
277 | if (!level) | |
278 | ioapic->irr &= ~mask; | |
279 | else { | |
280 | ioapic->irr |= mask; | |
281 | if ((!entry.fields.trig_mode && old_irr != ioapic->irr) | |
282 | || !entry.fields.remote_irr) | |
283 | ioapic_service(ioapic, irq); | |
284 | } | |
285 | } | |
286 | } | |
287 | ||
4fa6b9c5 | 288 | static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int gsi) |
1fd4f2a5 | 289 | { |
1fd4f2a5 | 290 | union ioapic_redir_entry *ent; |
1fd4f2a5 ED |
291 | |
292 | ent = &ioapic->redirtbl[gsi]; | |
293 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); | |
294 | ||
295 | ent->fields.remote_irr = 0; | |
296 | if (!ent->fields.mask && (ioapic->irr & (1 << gsi))) | |
35baff25 | 297 | ioapic_service(ioapic, gsi); |
1fd4f2a5 ED |
298 | } |
299 | ||
4fa6b9c5 AK |
300 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector) |
301 | { | |
302 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
303 | int i; | |
304 | ||
305 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
306 | if (ioapic->redirtbl[i].fields.vector == vector) | |
307 | __kvm_ioapic_update_eoi(ioapic, i); | |
308 | } | |
309 | ||
92760499 LV |
310 | static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr, |
311 | int len, int is_write) | |
1fd4f2a5 ED |
312 | { |
313 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
314 | ||
315 | return ((addr >= ioapic->base_address && | |
316 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
317 | } | |
318 | ||
319 | static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, | |
320 | void *val) | |
321 | { | |
322 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
323 | u32 result; | |
324 | ||
e25e3ed5 | 325 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
326 | ASSERT(!(addr & 0xf)); /* check alignment */ |
327 | ||
328 | addr &= 0xff; | |
329 | switch (addr) { | |
330 | case IOAPIC_REG_SELECT: | |
331 | result = ioapic->ioregsel; | |
332 | break; | |
333 | ||
334 | case IOAPIC_REG_WINDOW: | |
335 | result = ioapic_read_indirect(ioapic, addr, len); | |
336 | break; | |
337 | ||
338 | default: | |
339 | result = 0; | |
340 | break; | |
341 | } | |
342 | switch (len) { | |
343 | case 8: | |
344 | *(u64 *) val = result; | |
345 | break; | |
346 | case 1: | |
347 | case 2: | |
348 | case 4: | |
349 | memcpy(val, (char *)&result, len); | |
350 | break; | |
351 | default: | |
352 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
353 | } | |
354 | } | |
355 | ||
356 | static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, | |
357 | const void *val) | |
358 | { | |
359 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
360 | u32 data; | |
361 | ||
e25e3ed5 LV |
362 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
363 | (void*)addr, len, val); | |
1fd4f2a5 ED |
364 | ASSERT(!(addr & 0xf)); /* check alignment */ |
365 | if (len == 4 || len == 8) | |
366 | data = *(u32 *) val; | |
367 | else { | |
368 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
369 | return; | |
370 | } | |
371 | ||
372 | addr &= 0xff; | |
373 | switch (addr) { | |
374 | case IOAPIC_REG_SELECT: | |
375 | ioapic->ioregsel = data; | |
376 | break; | |
377 | ||
378 | case IOAPIC_REG_WINDOW: | |
379 | ioapic_write_indirect(ioapic, data); | |
380 | break; | |
b1fd3d30 ZX |
381 | #ifdef CONFIG_IA64 |
382 | case IOAPIC_REG_EOI: | |
0eb8f498 | 383 | kvm_ioapic_update_eoi(ioapic->kvm, data); |
b1fd3d30 ZX |
384 | break; |
385 | #endif | |
1fd4f2a5 ED |
386 | |
387 | default: | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
8c392696 ED |
392 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
393 | { | |
394 | int i; | |
395 | ||
396 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
397 | ioapic->redirtbl[i].fields.mask = 1; | |
398 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
399 | ioapic->ioregsel = 0; | |
400 | ioapic->irr = 0; | |
401 | ioapic->id = 0; | |
402 | } | |
403 | ||
1fd4f2a5 ED |
404 | int kvm_ioapic_init(struct kvm *kvm) |
405 | { | |
406 | struct kvm_ioapic *ioapic; | |
1fd4f2a5 ED |
407 | |
408 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
409 | if (!ioapic) | |
410 | return -ENOMEM; | |
d7deeeb0 | 411 | kvm->arch.vioapic = ioapic; |
8c392696 | 412 | kvm_ioapic_reset(ioapic); |
1fd4f2a5 ED |
413 | ioapic->dev.read = ioapic_mmio_read; |
414 | ioapic->dev.write = ioapic_mmio_write; | |
415 | ioapic->dev.in_range = ioapic_in_range; | |
416 | ioapic->dev.private = ioapic; | |
417 | ioapic->kvm = kvm; | |
418 | kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev); | |
419 | return 0; | |
420 | } |