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3de42dc0 XZ |
1 | /* |
2 | * irq_comm.c: Common API for in kernel interrupt controller | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
9611c187 | 20 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
3de42dc0 XZ |
21 | */ |
22 | ||
23 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
229456fc | 25 | #include <trace/events/kvm.h> |
79950e10 | 26 | |
79950e10 | 27 | #include <asm/msidef.h> |
58c2dde1 GN |
28 | #ifdef CONFIG_IA64 |
29 | #include <asm/iosapic.h> | |
30 | #endif | |
79950e10 | 31 | |
3de42dc0 XZ |
32 | #include "irq.h" |
33 | ||
34 | #include "ioapic.h" | |
35 | ||
1a6e4a8c GN |
36 | static inline int kvm_irq_line_state(unsigned long *irq_state, |
37 | int irq_source_id, int level) | |
38 | { | |
39 | /* Logical OR for level trig interrupt */ | |
40 | if (level) | |
41 | set_bit(irq_source_id, irq_state); | |
42 | else | |
43 | clear_bit(irq_source_id, irq_state); | |
44 | ||
45 | return !!(*irq_state); | |
46 | } | |
47 | ||
4925663a | 48 | static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e, |
1a6e4a8c | 49 | struct kvm *kvm, int irq_source_id, int level) |
399ec807 AK |
50 | { |
51 | #ifdef CONFIG_X86 | |
1a6e4a8c GN |
52 | struct kvm_pic *pic = pic_irqchip(kvm); |
53 | level = kvm_irq_line_state(&pic->irq_states[e->irqchip.pin], | |
54 | irq_source_id, level); | |
55 | return kvm_pic_set_irq(pic, e->irqchip.pin, level); | |
4925663a GN |
56 | #else |
57 | return -1; | |
399ec807 AK |
58 | #endif |
59 | } | |
60 | ||
4925663a | 61 | static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e, |
1a6e4a8c | 62 | struct kvm *kvm, int irq_source_id, int level) |
399ec807 | 63 | { |
1a6e4a8c GN |
64 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
65 | level = kvm_irq_line_state(&ioapic->irq_states[e->irqchip.pin], | |
66 | irq_source_id, level); | |
67 | ||
68 | return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, level); | |
399ec807 AK |
69 | } |
70 | ||
58c2dde1 | 71 | inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq) |
116191b6 | 72 | { |
58c2dde1 GN |
73 | #ifdef CONFIG_IA64 |
74 | return irq->delivery_mode == | |
75 | (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
76 | #else | |
77 | return irq->delivery_mode == APIC_DM_LOWEST; | |
78 | #endif | |
79 | } | |
116191b6 | 80 | |
58c2dde1 GN |
81 | int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src, |
82 | struct kvm_lapic_irq *irq) | |
83 | { | |
84 | int i, r = -1; | |
85 | struct kvm_vcpu *vcpu, *lowest = NULL; | |
86 | ||
87 | if (irq->dest_mode == 0 && irq->dest_id == 0xff && | |
88 | kvm_is_dm_lowest_prio(irq)) | |
343f94fe GN |
89 | printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n"); |
90 | ||
988a2cae GN |
91 | kvm_for_each_vcpu(i, vcpu, kvm) { |
92 | if (!kvm_apic_present(vcpu)) | |
343f94fe GN |
93 | continue; |
94 | ||
58c2dde1 GN |
95 | if (!kvm_apic_match_dest(vcpu, src, irq->shorthand, |
96 | irq->dest_id, irq->dest_mode)) | |
343f94fe GN |
97 | continue; |
98 | ||
58c2dde1 GN |
99 | if (!kvm_is_dm_lowest_prio(irq)) { |
100 | if (r < 0) | |
101 | r = 0; | |
102 | r += kvm_apic_set_irq(vcpu, irq); | |
aefd18f0 | 103 | } else if (kvm_lapic_enabled(vcpu)) { |
58c2dde1 GN |
104 | if (!lowest) |
105 | lowest = vcpu; | |
106 | else if (kvm_apic_compare_prio(vcpu, lowest) < 0) | |
107 | lowest = vcpu; | |
e1035715 | 108 | } |
343f94fe GN |
109 | } |
110 | ||
58c2dde1 GN |
111 | if (lowest) |
112 | r = kvm_apic_set_irq(lowest, irq); | |
113 | ||
114 | return r; | |
116191b6 SY |
115 | } |
116 | ||
bd2b53b2 MT |
117 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, |
118 | struct kvm *kvm, int irq_source_id, int level) | |
79950e10 | 119 | { |
58c2dde1 | 120 | struct kvm_lapic_irq irq; |
79950e10 | 121 | |
1a6e4a8c GN |
122 | if (!level) |
123 | return -1; | |
124 | ||
1000ff8d GN |
125 | trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data); |
126 | ||
58c2dde1 | 127 | irq.dest_id = (e->msi.address_lo & |
116191b6 | 128 | MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
58c2dde1 | 129 | irq.vector = (e->msi.data & |
116191b6 | 130 | MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
58c2dde1 GN |
131 | irq.dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo; |
132 | irq.trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data; | |
133 | irq.delivery_mode = e->msi.data & 0x700; | |
134 | irq.level = 1; | |
135 | irq.shorthand = 0; | |
116191b6 SY |
136 | |
137 | /* TODO Deal with RH bit of MSI message address */ | |
58c2dde1 | 138 | return kvm_irq_delivery_to_apic(kvm, NULL, &irq); |
79950e10 SY |
139 | } |
140 | ||
680b3648 | 141 | /* |
4925663a GN |
142 | * Return value: |
143 | * < 0 Interrupt was ignored (masked or not delivered for other reasons) | |
144 | * = 0 Interrupt was coalesced (previous irq is still pending) | |
145 | * > 0 Number of CPUs interrupt was delivered to | |
146 | */ | |
46e624b9 | 147 | int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level) |
3de42dc0 | 148 | { |
eba0226b GN |
149 | struct kvm_kernel_irq_routing_entry *e, irq_set[KVM_NR_IRQCHIPS]; |
150 | int ret = -1, i = 0; | |
46e624b9 GN |
151 | struct kvm_irq_routing_table *irq_rt; |
152 | struct hlist_node *n; | |
79950e10 | 153 | |
ae8c1c40 | 154 | trace_kvm_set_irq(irq, level, irq_source_id); |
229456fc | 155 | |
3de42dc0 XZ |
156 | /* Not possible to detect if the guest uses the PIC or the |
157 | * IOAPIC. So set the bit in both. The guest will ignore | |
158 | * writes to the unused one. | |
159 | */ | |
e42bba90 GN |
160 | rcu_read_lock(); |
161 | irq_rt = rcu_dereference(kvm->irq_routing); | |
46e624b9 | 162 | if (irq < irq_rt->nr_rt_entries) |
eba0226b GN |
163 | hlist_for_each_entry(e, n, &irq_rt->map[irq], link) |
164 | irq_set[i++] = *e; | |
e42bba90 | 165 | rcu_read_unlock(); |
eba0226b GN |
166 | |
167 | while(i--) { | |
168 | int r; | |
169 | r = irq_set[i].set(&irq_set[i], kvm, irq_source_id, level); | |
170 | if (r < 0) | |
171 | continue; | |
172 | ||
173 | ret = r + ((ret < 0) ? 0 : ret); | |
174 | } | |
175 | ||
4925663a | 176 | return ret; |
3de42dc0 XZ |
177 | } |
178 | ||
44882eed | 179 | void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin) |
3de42dc0 XZ |
180 | { |
181 | struct kvm_irq_ack_notifier *kian; | |
182 | struct hlist_node *n; | |
3e71f88b | 183 | int gsi; |
44882eed | 184 | |
229456fc MT |
185 | trace_kvm_ack_irq(irqchip, pin); |
186 | ||
e42bba90 GN |
187 | rcu_read_lock(); |
188 | gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin]; | |
3e71f88b | 189 | if (gsi != -1) |
280aa177 GN |
190 | hlist_for_each_entry_rcu(kian, n, &kvm->irq_ack_notifier_list, |
191 | link) | |
3e71f88b GN |
192 | if (kian->gsi == gsi) |
193 | kian->irq_acked(kian); | |
280aa177 | 194 | rcu_read_unlock(); |
3de42dc0 XZ |
195 | } |
196 | ||
197 | void kvm_register_irq_ack_notifier(struct kvm *kvm, | |
198 | struct kvm_irq_ack_notifier *kian) | |
199 | { | |
fa40a821 | 200 | mutex_lock(&kvm->irq_lock); |
280aa177 | 201 | hlist_add_head_rcu(&kian->link, &kvm->irq_ack_notifier_list); |
fa40a821 | 202 | mutex_unlock(&kvm->irq_lock); |
3de42dc0 XZ |
203 | } |
204 | ||
fa40a821 MT |
205 | void kvm_unregister_irq_ack_notifier(struct kvm *kvm, |
206 | struct kvm_irq_ack_notifier *kian) | |
3de42dc0 | 207 | { |
fa40a821 | 208 | mutex_lock(&kvm->irq_lock); |
280aa177 | 209 | hlist_del_init_rcu(&kian->link); |
fa40a821 | 210 | mutex_unlock(&kvm->irq_lock); |
280aa177 | 211 | synchronize_rcu(); |
3de42dc0 | 212 | } |
5550af4d | 213 | |
5550af4d SY |
214 | int kvm_request_irq_source_id(struct kvm *kvm) |
215 | { | |
216 | unsigned long *bitmap = &kvm->arch.irq_sources_bitmap; | |
fa40a821 MT |
217 | int irq_source_id; |
218 | ||
219 | mutex_lock(&kvm->irq_lock); | |
cd5a2685 | 220 | irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG); |
61552367 | 221 | |
cd5a2685 | 222 | if (irq_source_id >= BITS_PER_LONG) { |
5550af4d | 223 | printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n"); |
0c6ddceb JS |
224 | irq_source_id = -EFAULT; |
225 | goto unlock; | |
61552367 MM |
226 | } |
227 | ||
228 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); | |
229 | set_bit(irq_source_id, bitmap); | |
0c6ddceb | 230 | unlock: |
fa40a821 | 231 | mutex_unlock(&kvm->irq_lock); |
61552367 | 232 | |
5550af4d SY |
233 | return irq_source_id; |
234 | } | |
235 | ||
236 | void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id) | |
237 | { | |
238 | int i; | |
239 | ||
61552367 MM |
240 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); |
241 | ||
fa40a821 | 242 | mutex_lock(&kvm->irq_lock); |
61552367 | 243 | if (irq_source_id < 0 || |
cd5a2685 | 244 | irq_source_id >= BITS_PER_LONG) { |
5550af4d | 245 | printk(KERN_ERR "kvm: IRQ source ID out of range!\n"); |
0c6ddceb | 246 | goto unlock; |
5550af4d | 247 | } |
e50212bb MT |
248 | clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap); |
249 | if (!irqchip_in_kernel(kvm)) | |
250 | goto unlock; | |
251 | ||
1a6e4a8c GN |
252 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) { |
253 | clear_bit(irq_source_id, &kvm->arch.vioapic->irq_states[i]); | |
254 | if (i >= 16) | |
255 | continue; | |
256 | #ifdef CONFIG_X86 | |
257 | clear_bit(irq_source_id, &pic_irqchip(kvm)->irq_states[i]); | |
258 | #endif | |
259 | } | |
0c6ddceb | 260 | unlock: |
fa40a821 | 261 | mutex_unlock(&kvm->irq_lock); |
5550af4d | 262 | } |
75858a84 AK |
263 | |
264 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
265 | struct kvm_irq_mask_notifier *kimn) | |
266 | { | |
fa40a821 | 267 | mutex_lock(&kvm->irq_lock); |
75858a84 | 268 | kimn->irq = irq; |
280aa177 | 269 | hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list); |
fa40a821 | 270 | mutex_unlock(&kvm->irq_lock); |
75858a84 AK |
271 | } |
272 | ||
273 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
274 | struct kvm_irq_mask_notifier *kimn) | |
275 | { | |
fa40a821 | 276 | mutex_lock(&kvm->irq_lock); |
280aa177 | 277 | hlist_del_rcu(&kimn->link); |
fa40a821 | 278 | mutex_unlock(&kvm->irq_lock); |
280aa177 | 279 | synchronize_rcu(); |
75858a84 AK |
280 | } |
281 | ||
4a994358 GN |
282 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, |
283 | bool mask) | |
75858a84 AK |
284 | { |
285 | struct kvm_irq_mask_notifier *kimn; | |
286 | struct hlist_node *n; | |
4a994358 | 287 | int gsi; |
75858a84 | 288 | |
280aa177 | 289 | rcu_read_lock(); |
4a994358 GN |
290 | gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin]; |
291 | if (gsi != -1) | |
292 | hlist_for_each_entry_rcu(kimn, n, &kvm->mask_notifier_list, link) | |
293 | if (kimn->irq == gsi) | |
294 | kimn->func(kimn, mask); | |
280aa177 | 295 | rcu_read_unlock(); |
75858a84 AK |
296 | } |
297 | ||
399ec807 AK |
298 | void kvm_free_irq_routing(struct kvm *kvm) |
299 | { | |
e42bba90 GN |
300 | /* Called only during vm destruction. Nobody can use the pointer |
301 | at this stage */ | |
46e624b9 | 302 | kfree(kvm->irq_routing); |
399ec807 AK |
303 | } |
304 | ||
46e624b9 GN |
305 | static int setup_routing_entry(struct kvm_irq_routing_table *rt, |
306 | struct kvm_kernel_irq_routing_entry *e, | |
cded19f3 | 307 | const struct kvm_irq_routing_entry *ue) |
399ec807 AK |
308 | { |
309 | int r = -EINVAL; | |
310 | int delta; | |
d72118ce | 311 | unsigned max_pin; |
46e624b9 GN |
312 | struct kvm_kernel_irq_routing_entry *ei; |
313 | struct hlist_node *n; | |
314 | ||
315 | /* | |
316 | * Do not allow GSI to be mapped to the same irqchip more than once. | |
317 | * Allow only one to one mapping between GSI and MSI. | |
318 | */ | |
319 | hlist_for_each_entry(ei, n, &rt->map[ue->gsi], link) | |
320 | if (ei->type == KVM_IRQ_ROUTING_MSI || | |
321 | ue->u.irqchip.irqchip == ei->irqchip.irqchip) | |
322 | return r; | |
399ec807 AK |
323 | |
324 | e->gsi = ue->gsi; | |
5116d8f6 | 325 | e->type = ue->type; |
399ec807 AK |
326 | switch (ue->type) { |
327 | case KVM_IRQ_ROUTING_IRQCHIP: | |
328 | delta = 0; | |
329 | switch (ue->u.irqchip.irqchip) { | |
330 | case KVM_IRQCHIP_PIC_MASTER: | |
331 | e->set = kvm_set_pic_irq; | |
d72118ce | 332 | max_pin = 16; |
399ec807 AK |
333 | break; |
334 | case KVM_IRQCHIP_PIC_SLAVE: | |
4925663a | 335 | e->set = kvm_set_pic_irq; |
d72118ce | 336 | max_pin = 16; |
399ec807 AK |
337 | delta = 8; |
338 | break; | |
339 | case KVM_IRQCHIP_IOAPIC: | |
d72118ce | 340 | max_pin = KVM_IOAPIC_NUM_PINS; |
efbc100c | 341 | e->set = kvm_set_ioapic_irq; |
399ec807 AK |
342 | break; |
343 | default: | |
344 | goto out; | |
345 | } | |
346 | e->irqchip.irqchip = ue->u.irqchip.irqchip; | |
347 | e->irqchip.pin = ue->u.irqchip.pin + delta; | |
d72118ce | 348 | if (e->irqchip.pin >= max_pin) |
3e71f88b GN |
349 | goto out; |
350 | rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi; | |
399ec807 | 351 | break; |
79950e10 SY |
352 | case KVM_IRQ_ROUTING_MSI: |
353 | e->set = kvm_set_msi; | |
354 | e->msi.address_lo = ue->u.msi.address_lo; | |
355 | e->msi.address_hi = ue->u.msi.address_hi; | |
356 | e->msi.data = ue->u.msi.data; | |
357 | break; | |
399ec807 AK |
358 | default: |
359 | goto out; | |
360 | } | |
46e624b9 GN |
361 | |
362 | hlist_add_head(&e->link, &rt->map[e->gsi]); | |
399ec807 AK |
363 | r = 0; |
364 | out: | |
365 | return r; | |
366 | } | |
367 | ||
368 | ||
369 | int kvm_set_irq_routing(struct kvm *kvm, | |
370 | const struct kvm_irq_routing_entry *ue, | |
371 | unsigned nr, | |
372 | unsigned flags) | |
373 | { | |
46e624b9 | 374 | struct kvm_irq_routing_table *new, *old; |
3e71f88b | 375 | u32 i, j, nr_rt_entries = 0; |
399ec807 AK |
376 | int r; |
377 | ||
46e624b9 GN |
378 | for (i = 0; i < nr; ++i) { |
379 | if (ue[i].gsi >= KVM_MAX_IRQ_ROUTES) | |
380 | return -EINVAL; | |
381 | nr_rt_entries = max(nr_rt_entries, ue[i].gsi); | |
382 | } | |
383 | ||
384 | nr_rt_entries += 1; | |
385 | ||
386 | new = kzalloc(sizeof(*new) + (nr_rt_entries * sizeof(struct hlist_head)) | |
387 | + (nr * sizeof(struct kvm_kernel_irq_routing_entry)), | |
388 | GFP_KERNEL); | |
389 | ||
390 | if (!new) | |
391 | return -ENOMEM; | |
392 | ||
393 | new->rt_entries = (void *)&new->map[nr_rt_entries]; | |
394 | ||
395 | new->nr_rt_entries = nr_rt_entries; | |
3e71f88b GN |
396 | for (i = 0; i < 3; i++) |
397 | for (j = 0; j < KVM_IOAPIC_NUM_PINS; j++) | |
398 | new->chip[i][j] = -1; | |
46e624b9 | 399 | |
399ec807 AK |
400 | for (i = 0; i < nr; ++i) { |
401 | r = -EINVAL; | |
399ec807 AK |
402 | if (ue->flags) |
403 | goto out; | |
46e624b9 | 404 | r = setup_routing_entry(new, &new->rt_entries[i], ue); |
399ec807 AK |
405 | if (r) |
406 | goto out; | |
407 | ++ue; | |
399ec807 AK |
408 | } |
409 | ||
fa40a821 | 410 | mutex_lock(&kvm->irq_lock); |
46e624b9 | 411 | old = kvm->irq_routing; |
bd2b53b2 | 412 | kvm_irq_routing_update(kvm, new); |
fa40a821 | 413 | mutex_unlock(&kvm->irq_lock); |
bd2b53b2 | 414 | |
e42bba90 | 415 | synchronize_rcu(); |
399ec807 | 416 | |
46e624b9 | 417 | new = old; |
399ec807 AK |
418 | r = 0; |
419 | ||
420 | out: | |
46e624b9 | 421 | kfree(new); |
399ec807 AK |
422 | return r; |
423 | } | |
424 | ||
425 | #define IOAPIC_ROUTING_ENTRY(irq) \ | |
426 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ | |
427 | .u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) } | |
428 | #define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq) | |
429 | ||
430 | #ifdef CONFIG_X86 | |
399ec807 AK |
431 | # define PIC_ROUTING_ENTRY(irq) \ |
432 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ | |
433 | .u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 } | |
434 | # define ROUTING_ENTRY2(irq) \ | |
435 | IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq) | |
436 | #else | |
437 | # define ROUTING_ENTRY2(irq) \ | |
438 | IOAPIC_ROUTING_ENTRY(irq) | |
439 | #endif | |
440 | ||
441 | static const struct kvm_irq_routing_entry default_routing[] = { | |
442 | ROUTING_ENTRY2(0), ROUTING_ENTRY2(1), | |
443 | ROUTING_ENTRY2(2), ROUTING_ENTRY2(3), | |
444 | ROUTING_ENTRY2(4), ROUTING_ENTRY2(5), | |
445 | ROUTING_ENTRY2(6), ROUTING_ENTRY2(7), | |
446 | ROUTING_ENTRY2(8), ROUTING_ENTRY2(9), | |
447 | ROUTING_ENTRY2(10), ROUTING_ENTRY2(11), | |
448 | ROUTING_ENTRY2(12), ROUTING_ENTRY2(13), | |
449 | ROUTING_ENTRY2(14), ROUTING_ENTRY2(15), | |
450 | ROUTING_ENTRY1(16), ROUTING_ENTRY1(17), | |
451 | ROUTING_ENTRY1(18), ROUTING_ENTRY1(19), | |
452 | ROUTING_ENTRY1(20), ROUTING_ENTRY1(21), | |
453 | ROUTING_ENTRY1(22), ROUTING_ENTRY1(23), | |
454 | #ifdef CONFIG_IA64 | |
455 | ROUTING_ENTRY1(24), ROUTING_ENTRY1(25), | |
456 | ROUTING_ENTRY1(26), ROUTING_ENTRY1(27), | |
457 | ROUTING_ENTRY1(28), ROUTING_ENTRY1(29), | |
458 | ROUTING_ENTRY1(30), ROUTING_ENTRY1(31), | |
459 | ROUTING_ENTRY1(32), ROUTING_ENTRY1(33), | |
460 | ROUTING_ENTRY1(34), ROUTING_ENTRY1(35), | |
461 | ROUTING_ENTRY1(36), ROUTING_ENTRY1(37), | |
462 | ROUTING_ENTRY1(38), ROUTING_ENTRY1(39), | |
463 | ROUTING_ENTRY1(40), ROUTING_ENTRY1(41), | |
464 | ROUTING_ENTRY1(42), ROUTING_ENTRY1(43), | |
465 | ROUTING_ENTRY1(44), ROUTING_ENTRY1(45), | |
466 | ROUTING_ENTRY1(46), ROUTING_ENTRY1(47), | |
467 | #endif | |
468 | }; | |
469 | ||
470 | int kvm_setup_default_irq_routing(struct kvm *kvm) | |
471 | { | |
472 | return kvm_set_irq_routing(kvm, default_routing, | |
473 | ARRAY_SIZE(default_routing), 0); | |
474 | } |