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Commit | Line | Data |
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fc01f7e7 FB |
1 | /* |
2 | * QEMU System Emulator header | |
5fafdf24 | 3 | * |
fc01f7e7 | 4 | * Copyright (c) 2003 Fabrice Bellard |
5fafdf24 | 5 | * |
fc01f7e7 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #ifndef VL_H | |
25 | #define VL_H | |
26 | ||
67b915a5 FB |
27 | /* we put basic includes here to avoid repeating them in device drivers */ |
28 | #include <stdlib.h> | |
29 | #include <stdio.h> | |
30 | #include <stdarg.h> | |
31 | #include <string.h> | |
32 | #include <inttypes.h> | |
85571bc7 | 33 | #include <limits.h> |
8a7ddc38 | 34 | #include <time.h> |
67b915a5 FB |
35 | #include <ctype.h> |
36 | #include <errno.h> | |
37 | #include <unistd.h> | |
38 | #include <fcntl.h> | |
7d3505c5 | 39 | #include <sys/stat.h> |
67b915a5 FB |
40 | |
41 | #ifndef O_LARGEFILE | |
42 | #define O_LARGEFILE 0 | |
43 | #endif | |
40c3bac3 FB |
44 | #ifndef O_BINARY |
45 | #define O_BINARY 0 | |
46 | #endif | |
67b915a5 | 47 | |
71c2fd5c TS |
48 | #ifndef ENOMEDIUM |
49 | #define ENOMEDIUM ENODEV | |
50 | #endif | |
2e9671da | 51 | |
67b915a5 | 52 | #ifdef _WIN32 |
a18e524a | 53 | #include <windows.h> |
ac62f715 | 54 | #define fsync _commit |
57d1a2b6 FB |
55 | #define lseek _lseeki64 |
56 | #define ENOTSUP 4096 | |
beac80cd FB |
57 | extern int qemu_ftruncate64(int, int64_t); |
58 | #define ftruncate qemu_ftruncate64 | |
59 | ||
57d1a2b6 FB |
60 | |
61 | static inline char *realpath(const char *path, char *resolved_path) | |
62 | { | |
63 | _fullpath(resolved_path, path, _MAX_PATH); | |
64 | return resolved_path; | |
65 | } | |
ec3757de FB |
66 | |
67 | #define PRId64 "I64d" | |
26a76461 FB |
68 | #define PRIx64 "I64x" |
69 | #define PRIu64 "I64u" | |
70 | #define PRIo64 "I64o" | |
67b915a5 | 71 | #endif |
8a7ddc38 | 72 | |
ea2384d3 FB |
73 | #ifdef QEMU_TOOL |
74 | ||
75 | /* we use QEMU_TOOL in the command line tools which do not depend on | |
76 | the target CPU type */ | |
77 | #include "config-host.h" | |
78 | #include <setjmp.h> | |
79 | #include "osdep.h" | |
80 | #include "bswap.h" | |
81 | ||
82 | #else | |
83 | ||
4f209290 | 84 | #include "audio/audio.h" |
16f62432 FB |
85 | #include "cpu.h" |
86 | ||
ea2384d3 FB |
87 | #endif /* !defined(QEMU_TOOL) */ |
88 | ||
67b915a5 FB |
89 | #ifndef glue |
90 | #define xglue(x, y) x ## y | |
91 | #define glue(x, y) xglue(x, y) | |
92 | #define stringify(s) tostring(s) | |
93 | #define tostring(s) #s | |
94 | #endif | |
95 | ||
2e03286b AZ |
96 | #ifndef likely |
97 | #if __GNUC__ < 3 | |
98 | #define __builtin_expect(x, n) (x) | |
99 | #endif | |
100 | ||
101 | #define likely(x) __builtin_expect(!!(x), 1) | |
102 | #define unlikely(x) __builtin_expect(!!(x), 0) | |
103 | #endif | |
104 | ||
24236869 FB |
105 | #ifndef MIN |
106 | #define MIN(a, b) (((a) < (b)) ? (a) : (b)) | |
107 | #endif | |
108 | #ifndef MAX | |
109 | #define MAX(a, b) (((a) > (b)) ? (a) : (b)) | |
110 | #endif | |
111 | ||
18607dcb FB |
112 | /* cutils.c */ |
113 | void pstrcpy(char *buf, int buf_size, const char *str); | |
114 | char *pstrcat(char *buf, int buf_size, const char *s); | |
115 | int strstart(const char *str, const char *val, const char **ptr); | |
116 | int stristart(const char *str, const char *val, const char **ptr); | |
117 | ||
33e3963e | 118 | /* vl.c */ |
80cabfad | 119 | uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
313aa567 | 120 | |
80cabfad FB |
121 | void hw_error(const char *fmt, ...); |
122 | ||
80cabfad FB |
123 | extern const char *bios_dir; |
124 | ||
8a7ddc38 | 125 | extern int vm_running; |
c35734b2 | 126 | extern const char *qemu_name; |
8a7ddc38 | 127 | |
0bd48850 FB |
128 | typedef struct vm_change_state_entry VMChangeStateEntry; |
129 | typedef void VMChangeStateHandler(void *opaque, int running); | |
8a7ddc38 FB |
130 | typedef void VMStopHandler(void *opaque, int reason); |
131 | ||
0bd48850 FB |
132 | VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
133 | void *opaque); | |
134 | void qemu_del_vm_change_state_handler(VMChangeStateEntry *e); | |
135 | ||
8a7ddc38 FB |
136 | int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
137 | void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); | |
138 | ||
139 | void vm_start(void); | |
140 | void vm_stop(int reason); | |
141 | ||
bb0c6722 FB |
142 | typedef void QEMUResetHandler(void *opaque); |
143 | ||
144 | void qemu_register_reset(QEMUResetHandler *func, void *opaque); | |
145 | void qemu_system_reset_request(void); | |
146 | void qemu_system_shutdown_request(void); | |
3475187d FB |
147 | void qemu_system_powerdown_request(void); |
148 | #if !defined(TARGET_SPARC) | |
149 | // Please implement a power failure function to signal the OS | |
150 | #define qemu_system_powerdown() do{}while(0) | |
151 | #else | |
152 | void qemu_system_powerdown(void); | |
153 | #endif | |
bb0c6722 | 154 | |
ea2384d3 FB |
155 | void main_loop_wait(int timeout); |
156 | ||
0ced6589 FB |
157 | extern int ram_size; |
158 | extern int bios_size; | |
ee22c2f7 | 159 | extern int rtc_utc; |
1f04275e | 160 | extern int cirrus_vga_enabled; |
d34cab9f | 161 | extern int vmsvga_enabled; |
28b9b5af FB |
162 | extern int graphic_width; |
163 | extern int graphic_height; | |
164 | extern int graphic_depth; | |
3d11d0eb | 165 | extern const char *keyboard_layout; |
d993e026 | 166 | extern int kqemu_allowed; |
a09db21f | 167 | extern int win2k_install_hack; |
3780e197 | 168 | extern int alt_grab; |
bb36d470 | 169 | extern int usb_enabled; |
6a00d601 | 170 | extern int smp_cpus; |
9467cd46 | 171 | extern int cursor_hide; |
a171fe39 | 172 | extern int graphic_rotate; |
667accab | 173 | extern int no_quit; |
8e71621f | 174 | extern int semihosting_enabled; |
3c07f8e8 | 175 | extern int autostart; |
2b8f2d41 | 176 | extern int old_param; |
47d5d01a | 177 | extern const char *bootp_filename; |
0ced6589 | 178 | |
9ae02555 TS |
179 | #define MAX_OPTION_ROMS 16 |
180 | extern const char *option_rom[MAX_OPTION_ROMS]; | |
181 | extern int nb_option_roms; | |
182 | ||
66508601 BS |
183 | #ifdef TARGET_SPARC |
184 | #define MAX_PROM_ENVS 128 | |
185 | extern const char *prom_envs[MAX_PROM_ENVS]; | |
186 | extern unsigned int nb_prom_envs; | |
187 | #endif | |
188 | ||
0ced6589 | 189 | /* XXX: make it dynamic */ |
970ac5a3 | 190 | #define MAX_BIOS_SIZE (4 * 1024 * 1024) |
75956cf0 | 191 | #if defined (TARGET_PPC) || defined (TARGET_SPARC64) |
d5295253 | 192 | #define BIOS_SIZE ((512 + 32) * 1024) |
6af0bf9c | 193 | #elif defined(TARGET_MIPS) |
567daa49 | 194 | #define BIOS_SIZE (4 * 1024 * 1024) |
0ced6589 | 195 | #endif |
aaaa7df6 | 196 | |
63066f4f FB |
197 | /* keyboard/mouse support */ |
198 | ||
199 | #define MOUSE_EVENT_LBUTTON 0x01 | |
200 | #define MOUSE_EVENT_RBUTTON 0x02 | |
201 | #define MOUSE_EVENT_MBUTTON 0x04 | |
202 | ||
203 | typedef void QEMUPutKBDEvent(void *opaque, int keycode); | |
204 | typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); | |
205 | ||
455204eb TS |
206 | typedef struct QEMUPutMouseEntry { |
207 | QEMUPutMouseEvent *qemu_put_mouse_event; | |
208 | void *qemu_put_mouse_event_opaque; | |
209 | int qemu_put_mouse_event_absolute; | |
210 | char *qemu_put_mouse_event_name; | |
211 | ||
212 | /* used internally by qemu for handling mice */ | |
213 | struct QEMUPutMouseEntry *next; | |
214 | } QEMUPutMouseEntry; | |
215 | ||
63066f4f | 216 | void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
455204eb TS |
217 | QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
218 | void *opaque, int absolute, | |
219 | const char *name); | |
220 | void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry); | |
63066f4f FB |
221 | |
222 | void kbd_put_keycode(int keycode); | |
223 | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); | |
09b26c5e | 224 | int kbd_mouse_is_absolute(void); |
63066f4f | 225 | |
455204eb TS |
226 | void do_info_mice(void); |
227 | void do_mouse_set(int index); | |
228 | ||
82c643ff FB |
229 | /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx |
230 | constants) */ | |
231 | #define QEMU_KEY_ESC1(c) ((c) | 0xe100) | |
232 | #define QEMU_KEY_BACKSPACE 0x007f | |
233 | #define QEMU_KEY_UP QEMU_KEY_ESC1('A') | |
234 | #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') | |
235 | #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') | |
236 | #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') | |
237 | #define QEMU_KEY_HOME QEMU_KEY_ESC1(1) | |
238 | #define QEMU_KEY_END QEMU_KEY_ESC1(4) | |
239 | #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) | |
240 | #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) | |
241 | #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) | |
242 | ||
243 | #define QEMU_KEY_CTRL_UP 0xe400 | |
244 | #define QEMU_KEY_CTRL_DOWN 0xe401 | |
245 | #define QEMU_KEY_CTRL_LEFT 0xe402 | |
246 | #define QEMU_KEY_CTRL_RIGHT 0xe403 | |
247 | #define QEMU_KEY_CTRL_HOME 0xe404 | |
248 | #define QEMU_KEY_CTRL_END 0xe405 | |
249 | #define QEMU_KEY_CTRL_PAGEUP 0xe406 | |
250 | #define QEMU_KEY_CTRL_PAGEDOWN 0xe407 | |
251 | ||
252 | void kbd_put_keysym(int keysym); | |
253 | ||
c20709aa FB |
254 | /* async I/O support */ |
255 | ||
256 | typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); | |
257 | typedef int IOCanRWHandler(void *opaque); | |
7c9d8e07 | 258 | typedef void IOHandler(void *opaque); |
c20709aa | 259 | |
5fafdf24 TS |
260 | int qemu_set_fd_handler2(int fd, |
261 | IOCanRWHandler *fd_read_poll, | |
262 | IOHandler *fd_read, | |
263 | IOHandler *fd_write, | |
7c9d8e07 FB |
264 | void *opaque); |
265 | int qemu_set_fd_handler(int fd, | |
5fafdf24 | 266 | IOHandler *fd_read, |
7c9d8e07 FB |
267 | IOHandler *fd_write, |
268 | void *opaque); | |
c20709aa | 269 | |
f331110f FB |
270 | /* Polling handling */ |
271 | ||
272 | /* return TRUE if no sleep should be done afterwards */ | |
273 | typedef int PollingFunc(void *opaque); | |
274 | ||
275 | int qemu_add_polling_cb(PollingFunc *func, void *opaque); | |
276 | void qemu_del_polling_cb(PollingFunc *func, void *opaque); | |
277 | ||
a18e524a FB |
278 | #ifdef _WIN32 |
279 | /* Wait objects handling */ | |
280 | typedef void WaitObjectFunc(void *opaque); | |
281 | ||
282 | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); | |
283 | void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); | |
284 | #endif | |
285 | ||
86e94dea TS |
286 | typedef struct QEMUBH QEMUBH; |
287 | ||
82c643ff FB |
288 | /* character device */ |
289 | ||
290 | #define CHR_EVENT_BREAK 0 /* serial break char */ | |
ea2384d3 | 291 | #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
86e94dea | 292 | #define CHR_EVENT_RESET 2 /* new connection established */ |
2122c51a FB |
293 | |
294 | ||
295 | #define CHR_IOCTL_SERIAL_SET_PARAMS 1 | |
296 | typedef struct { | |
297 | int speed; | |
298 | int parity; | |
299 | int data_bits; | |
300 | int stop_bits; | |
301 | } QEMUSerialSetParams; | |
302 | ||
303 | #define CHR_IOCTL_SERIAL_SET_BREAK 2 | |
304 | ||
305 | #define CHR_IOCTL_PP_READ_DATA 3 | |
306 | #define CHR_IOCTL_PP_WRITE_DATA 4 | |
307 | #define CHR_IOCTL_PP_READ_CONTROL 5 | |
308 | #define CHR_IOCTL_PP_WRITE_CONTROL 6 | |
309 | #define CHR_IOCTL_PP_READ_STATUS 7 | |
5867c88a TS |
310 | #define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
311 | #define CHR_IOCTL_PP_EPP_READ 9 | |
312 | #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 | |
313 | #define CHR_IOCTL_PP_EPP_WRITE 11 | |
2122c51a | 314 | |
82c643ff FB |
315 | typedef void IOEventHandler(void *opaque, int event); |
316 | ||
317 | typedef struct CharDriverState { | |
318 | int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); | |
e5b0bc44 | 319 | void (*chr_update_read_handler)(struct CharDriverState *s); |
2122c51a | 320 | int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
82c643ff | 321 | IOEventHandler *chr_event; |
e5b0bc44 PB |
322 | IOCanRWHandler *chr_can_read; |
323 | IOReadHandler *chr_read; | |
324 | void *handler_opaque; | |
eb45f5fe | 325 | void (*chr_send_event)(struct CharDriverState *chr, int event); |
f331110f | 326 | void (*chr_close)(struct CharDriverState *chr); |
82c643ff | 327 | void *opaque; |
20d8a3ed | 328 | int focus; |
86e94dea | 329 | QEMUBH *bh; |
82c643ff FB |
330 | } CharDriverState; |
331 | ||
5856de80 | 332 | CharDriverState *qemu_chr_open(const char *filename); |
82c643ff FB |
333 | void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
334 | int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); | |
ea2384d3 | 335 | void qemu_chr_send_event(CharDriverState *s, int event); |
5fafdf24 TS |
336 | void qemu_chr_add_handlers(CharDriverState *s, |
337 | IOCanRWHandler *fd_can_read, | |
e5b0bc44 PB |
338 | IOReadHandler *fd_read, |
339 | IOEventHandler *fd_event, | |
340 | void *opaque); | |
2122c51a | 341 | int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
86e94dea | 342 | void qemu_chr_reset(CharDriverState *s); |
e5b0bc44 PB |
343 | int qemu_chr_can_read(CharDriverState *s); |
344 | void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); | |
f8d179e3 | 345 | |
82c643ff FB |
346 | /* consoles */ |
347 | ||
348 | typedef struct DisplayState DisplayState; | |
349 | typedef struct TextConsole TextConsole; | |
350 | ||
95219897 PB |
351 | typedef void (*vga_hw_update_ptr)(void *); |
352 | typedef void (*vga_hw_invalidate_ptr)(void *); | |
353 | typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); | |
354 | ||
355 | TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, | |
356 | vga_hw_invalidate_ptr invalidate, | |
357 | vga_hw_screen_dump_ptr screen_dump, | |
358 | void *opaque); | |
359 | void vga_hw_update(void); | |
360 | void vga_hw_invalidate(void); | |
361 | void vga_hw_screen_dump(const char *filename); | |
362 | ||
363 | int is_graphic_console(void); | |
af3a9031 | 364 | CharDriverState *text_console_init(DisplayState *ds, const char *p); |
82c643ff FB |
365 | void console_select(unsigned int index); |
366 | ||
8d11df9e FB |
367 | /* serial ports */ |
368 | ||
369 | #define MAX_SERIAL_PORTS 4 | |
370 | ||
371 | extern CharDriverState *serial_hds[MAX_SERIAL_PORTS]; | |
372 | ||
6508fe59 FB |
373 | /* parallel ports */ |
374 | ||
375 | #define MAX_PARALLEL_PORTS 3 | |
376 | ||
377 | extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS]; | |
378 | ||
5867c88a TS |
379 | struct ParallelIOArg { |
380 | void *buffer; | |
381 | int count; | |
382 | }; | |
383 | ||
7c9d8e07 FB |
384 | /* VLANs support */ |
385 | ||
386 | typedef struct VLANClientState VLANClientState; | |
387 | ||
388 | struct VLANClientState { | |
389 | IOReadHandler *fd_read; | |
d861b05e PB |
390 | /* Packets may still be sent if this returns zero. It's used to |
391 | rate-limit the slirp code. */ | |
392 | IOCanRWHandler *fd_can_read; | |
7c9d8e07 FB |
393 | void *opaque; |
394 | struct VLANClientState *next; | |
395 | struct VLANState *vlan; | |
396 | char info_str[256]; | |
397 | }; | |
398 | ||
399 | typedef struct VLANState { | |
400 | int id; | |
401 | VLANClientState *first_client; | |
402 | struct VLANState *next; | |
833c7174 | 403 | unsigned int nb_guest_devs, nb_host_devs; |
7c9d8e07 FB |
404 | } VLANState; |
405 | ||
406 | VLANState *qemu_find_vlan(int id); | |
407 | VLANClientState *qemu_new_vlan_client(VLANState *vlan, | |
d861b05e PB |
408 | IOReadHandler *fd_read, |
409 | IOCanRWHandler *fd_can_read, | |
410 | void *opaque); | |
411 | int qemu_can_send_packet(VLANClientState *vc); | |
7c9d8e07 | 412 | void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
d861b05e | 413 | void qemu_handler_true(void *opaque); |
7c9d8e07 FB |
414 | |
415 | void do_info_network(void); | |
416 | ||
7fb843f8 FB |
417 | /* TAP win32 */ |
418 | int tap_win32_init(VLANState *vlan, const char *ifname); | |
7fb843f8 | 419 | |
7c9d8e07 | 420 | /* NIC info */ |
c4b1fcc0 FB |
421 | |
422 | #define MAX_NICS 8 | |
423 | ||
7c9d8e07 | 424 | typedef struct NICInfo { |
c4b1fcc0 | 425 | uint8_t macaddr[6]; |
a41b2ff2 | 426 | const char *model; |
7c9d8e07 FB |
427 | VLANState *vlan; |
428 | } NICInfo; | |
c4b1fcc0 FB |
429 | |
430 | extern int nb_nics; | |
7c9d8e07 | 431 | extern NICInfo nd_table[MAX_NICS]; |
8a7ddc38 FB |
432 | |
433 | /* timers */ | |
434 | ||
435 | typedef struct QEMUClock QEMUClock; | |
436 | typedef struct QEMUTimer QEMUTimer; | |
437 | typedef void QEMUTimerCB(void *opaque); | |
438 | ||
439 | /* The real time clock should be used only for stuff which does not | |
440 | change the virtual machine state, as it is run even if the virtual | |
69b91039 | 441 | machine is stopped. The real time clock has a frequency of 1000 |
8a7ddc38 FB |
442 | Hz. */ |
443 | extern QEMUClock *rt_clock; | |
444 | ||
e80cfcfc | 445 | /* The virtual clock is only run during the emulation. It is stopped |
8a7ddc38 FB |
446 | when the virtual machine is stopped. Virtual timers use a high |
447 | precision clock, usually cpu cycles (use ticks_per_sec). */ | |
448 | extern QEMUClock *vm_clock; | |
449 | ||
450 | int64_t qemu_get_clock(QEMUClock *clock); | |
451 | ||
452 | QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque); | |
453 | void qemu_free_timer(QEMUTimer *ts); | |
454 | void qemu_del_timer(QEMUTimer *ts); | |
455 | void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time); | |
456 | int qemu_timer_pending(QEMUTimer *ts); | |
457 | ||
458 | extern int64_t ticks_per_sec; | |
8a7ddc38 | 459 | |
1dce7c3c | 460 | int64_t cpu_get_ticks(void); |
8a7ddc38 FB |
461 | void cpu_enable_ticks(void); |
462 | void cpu_disable_ticks(void); | |
463 | ||
464 | /* VM Load/Save */ | |
465 | ||
faea38e7 | 466 | typedef struct QEMUFile QEMUFile; |
8a7ddc38 | 467 | |
faea38e7 FB |
468 | QEMUFile *qemu_fopen(const char *filename, const char *mode); |
469 | void qemu_fflush(QEMUFile *f); | |
470 | void qemu_fclose(QEMUFile *f); | |
8a7ddc38 FB |
471 | void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
472 | void qemu_put_byte(QEMUFile *f, int v); | |
473 | void qemu_put_be16(QEMUFile *f, unsigned int v); | |
474 | void qemu_put_be32(QEMUFile *f, unsigned int v); | |
475 | void qemu_put_be64(QEMUFile *f, uint64_t v); | |
476 | int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); | |
477 | int qemu_get_byte(QEMUFile *f); | |
478 | unsigned int qemu_get_be16(QEMUFile *f); | |
479 | unsigned int qemu_get_be32(QEMUFile *f); | |
480 | uint64_t qemu_get_be64(QEMUFile *f); | |
481 | ||
482 | static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) | |
483 | { | |
484 | qemu_put_be64(f, *pv); | |
485 | } | |
486 | ||
487 | static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) | |
488 | { | |
489 | qemu_put_be32(f, *pv); | |
490 | } | |
491 | ||
492 | static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) | |
493 | { | |
494 | qemu_put_be16(f, *pv); | |
495 | } | |
496 | ||
497 | static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) | |
498 | { | |
499 | qemu_put_byte(f, *pv); | |
500 | } | |
501 | ||
502 | static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) | |
503 | { | |
504 | *pv = qemu_get_be64(f); | |
505 | } | |
506 | ||
507 | static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) | |
508 | { | |
509 | *pv = qemu_get_be32(f); | |
510 | } | |
511 | ||
512 | static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) | |
513 | { | |
514 | *pv = qemu_get_be16(f); | |
515 | } | |
516 | ||
517 | static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) | |
518 | { | |
519 | *pv = qemu_get_byte(f); | |
520 | } | |
521 | ||
c27004ec FB |
522 | #if TARGET_LONG_BITS == 64 |
523 | #define qemu_put_betl qemu_put_be64 | |
524 | #define qemu_get_betl qemu_get_be64 | |
525 | #define qemu_put_betls qemu_put_be64s | |
526 | #define qemu_get_betls qemu_get_be64s | |
527 | #else | |
528 | #define qemu_put_betl qemu_put_be32 | |
529 | #define qemu_get_betl qemu_get_be32 | |
530 | #define qemu_put_betls qemu_put_be32s | |
531 | #define qemu_get_betls qemu_get_be32s | |
532 | #endif | |
533 | ||
8a7ddc38 FB |
534 | int64_t qemu_ftell(QEMUFile *f); |
535 | int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence); | |
536 | ||
537 | typedef void SaveStateHandler(QEMUFile *f, void *opaque); | |
538 | typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); | |
539 | ||
5fafdf24 TS |
540 | int register_savevm(const char *idstr, |
541 | int instance_id, | |
8a7ddc38 FB |
542 | int version_id, |
543 | SaveStateHandler *save_state, | |
544 | LoadStateHandler *load_state, | |
545 | void *opaque); | |
546 | void qemu_get_timer(QEMUFile *f, QEMUTimer *ts); | |
547 | void qemu_put_timer(QEMUFile *f, QEMUTimer *ts); | |
c4b1fcc0 | 548 | |
6a00d601 FB |
549 | void cpu_save(QEMUFile *f, void *opaque); |
550 | int cpu_load(QEMUFile *f, void *opaque, int version_id); | |
551 | ||
faea38e7 FB |
552 | void do_savevm(const char *name); |
553 | void do_loadvm(const char *name); | |
554 | void do_delvm(const char *name); | |
555 | void do_info_snapshots(void); | |
556 | ||
83f64091 | 557 | /* bottom halves */ |
83f64091 FB |
558 | typedef void QEMUBHFunc(void *opaque); |
559 | ||
560 | QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque); | |
561 | void qemu_bh_schedule(QEMUBH *bh); | |
562 | void qemu_bh_cancel(QEMUBH *bh); | |
563 | void qemu_bh_delete(QEMUBH *bh); | |
6eb5733a | 564 | int qemu_bh_poll(void); |
83f64091 | 565 | |
fc01f7e7 FB |
566 | /* block.c */ |
567 | typedef struct BlockDriverState BlockDriverState; | |
ea2384d3 FB |
568 | typedef struct BlockDriver BlockDriver; |
569 | ||
570 | extern BlockDriver bdrv_raw; | |
19cb3738 | 571 | extern BlockDriver bdrv_host_device; |
ea2384d3 FB |
572 | extern BlockDriver bdrv_cow; |
573 | extern BlockDriver bdrv_qcow; | |
574 | extern BlockDriver bdrv_vmdk; | |
3c56521b | 575 | extern BlockDriver bdrv_cloop; |
585d0ed9 | 576 | extern BlockDriver bdrv_dmg; |
a8753c34 | 577 | extern BlockDriver bdrv_bochs; |
6a0f9e82 | 578 | extern BlockDriver bdrv_vpc; |
de167e41 | 579 | extern BlockDriver bdrv_vvfat; |
faea38e7 | 580 | extern BlockDriver bdrv_qcow2; |
6ada7453 | 581 | extern BlockDriver bdrv_parallels; |
faea38e7 FB |
582 | |
583 | typedef struct BlockDriverInfo { | |
584 | /* in bytes, 0 if irrelevant */ | |
5fafdf24 | 585 | int cluster_size; |
faea38e7 | 586 | /* offset at which the VM state can be saved (0 if not possible) */ |
5fafdf24 | 587 | int64_t vm_state_offset; |
faea38e7 FB |
588 | } BlockDriverInfo; |
589 | ||
590 | typedef struct QEMUSnapshotInfo { | |
591 | char id_str[128]; /* unique snapshot id */ | |
592 | /* the following fields are informative. They are not needed for | |
593 | the consistency of the snapshot */ | |
594 | char name[256]; /* user choosen name */ | |
595 | uint32_t vm_state_size; /* VM state info size */ | |
596 | uint32_t date_sec; /* UTC date of the snapshot */ | |
597 | uint32_t date_nsec; | |
598 | uint64_t vm_clock_nsec; /* VM clock relative to boot */ | |
599 | } QEMUSnapshotInfo; | |
ea2384d3 | 600 | |
83f64091 FB |
601 | #define BDRV_O_RDONLY 0x0000 |
602 | #define BDRV_O_RDWR 0x0002 | |
603 | #define BDRV_O_ACCESS 0x0003 | |
604 | #define BDRV_O_CREAT 0x0004 /* create an empty file */ | |
605 | #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */ | |
606 | #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to | |
607 | use a disk image format on top of | |
608 | it (default for | |
609 | bdrv_file_open()) */ | |
610 | ||
ea2384d3 FB |
611 | void bdrv_init(void); |
612 | BlockDriver *bdrv_find_format(const char *format_name); | |
5fafdf24 | 613 | int bdrv_create(BlockDriver *drv, |
ea2384d3 FB |
614 | const char *filename, int64_t size_in_sectors, |
615 | const char *backing_file, int flags); | |
c4b1fcc0 FB |
616 | BlockDriverState *bdrv_new(const char *device_name); |
617 | void bdrv_delete(BlockDriverState *bs); | |
83f64091 FB |
618 | int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags); |
619 | int bdrv_open(BlockDriverState *bs, const char *filename, int flags); | |
620 | int bdrv_open2(BlockDriverState *bs, const char *filename, int flags, | |
ea2384d3 | 621 | BlockDriver *drv); |
fc01f7e7 | 622 | void bdrv_close(BlockDriverState *bs); |
5fafdf24 | 623 | int bdrv_read(BlockDriverState *bs, int64_t sector_num, |
fc01f7e7 | 624 | uint8_t *buf, int nb_sectors); |
5fafdf24 | 625 | int bdrv_write(BlockDriverState *bs, int64_t sector_num, |
fc01f7e7 | 626 | const uint8_t *buf, int nb_sectors); |
5fafdf24 | 627 | int bdrv_pread(BlockDriverState *bs, int64_t offset, |
83f64091 | 628 | void *buf, int count); |
5fafdf24 | 629 | int bdrv_pwrite(BlockDriverState *bs, int64_t offset, |
83f64091 FB |
630 | const void *buf, int count); |
631 | int bdrv_truncate(BlockDriverState *bs, int64_t offset); | |
632 | int64_t bdrv_getlength(BlockDriverState *bs); | |
fc01f7e7 | 633 | void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr); |
33e3963e | 634 | int bdrv_commit(BlockDriverState *bs); |
77fef8c1 | 635 | void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size); |
83f64091 FB |
636 | /* async block I/O */ |
637 | typedef struct BlockDriverAIOCB BlockDriverAIOCB; | |
638 | typedef void BlockDriverCompletionFunc(void *opaque, int ret); | |
639 | ||
ce1a14dc PB |
640 | BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num, |
641 | uint8_t *buf, int nb_sectors, | |
642 | BlockDriverCompletionFunc *cb, void *opaque); | |
643 | BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num, | |
644 | const uint8_t *buf, int nb_sectors, | |
645 | BlockDriverCompletionFunc *cb, void *opaque); | |
83f64091 | 646 | void bdrv_aio_cancel(BlockDriverAIOCB *acb); |
83f64091 FB |
647 | |
648 | void qemu_aio_init(void); | |
649 | void qemu_aio_poll(void); | |
6192bc37 | 650 | void qemu_aio_flush(void); |
83f64091 FB |
651 | void qemu_aio_wait_start(void); |
652 | void qemu_aio_wait(void); | |
653 | void qemu_aio_wait_end(void); | |
654 | ||
2bac6019 AZ |
655 | int qemu_key_check(BlockDriverState *bs, const char *name); |
656 | ||
7a6cba61 PB |
657 | /* Ensure contents are flushed to disk. */ |
658 | void bdrv_flush(BlockDriverState *bs); | |
33e3963e | 659 | |
c4b1fcc0 FB |
660 | #define BDRV_TYPE_HD 0 |
661 | #define BDRV_TYPE_CDROM 1 | |
662 | #define BDRV_TYPE_FLOPPY 2 | |
4dbb0f50 TS |
663 | #define BIOS_ATA_TRANSLATION_AUTO 0 |
664 | #define BIOS_ATA_TRANSLATION_NONE 1 | |
665 | #define BIOS_ATA_TRANSLATION_LBA 2 | |
666 | #define BIOS_ATA_TRANSLATION_LARGE 3 | |
667 | #define BIOS_ATA_TRANSLATION_RECHS 4 | |
c4b1fcc0 | 668 | |
5fafdf24 | 669 | void bdrv_set_geometry_hint(BlockDriverState *bs, |
c4b1fcc0 FB |
670 | int cyls, int heads, int secs); |
671 | void bdrv_set_type_hint(BlockDriverState *bs, int type); | |
46d4767d | 672 | void bdrv_set_translation_hint(BlockDriverState *bs, int translation); |
5fafdf24 | 673 | void bdrv_get_geometry_hint(BlockDriverState *bs, |
c4b1fcc0 FB |
674 | int *pcyls, int *pheads, int *psecs); |
675 | int bdrv_get_type_hint(BlockDriverState *bs); | |
46d4767d | 676 | int bdrv_get_translation_hint(BlockDriverState *bs); |
c4b1fcc0 FB |
677 | int bdrv_is_removable(BlockDriverState *bs); |
678 | int bdrv_is_read_only(BlockDriverState *bs); | |
679 | int bdrv_is_inserted(BlockDriverState *bs); | |
19cb3738 | 680 | int bdrv_media_changed(BlockDriverState *bs); |
c4b1fcc0 FB |
681 | int bdrv_is_locked(BlockDriverState *bs); |
682 | void bdrv_set_locked(BlockDriverState *bs, int locked); | |
19cb3738 | 683 | void bdrv_eject(BlockDriverState *bs, int eject_flag); |
5fafdf24 | 684 | void bdrv_set_change_cb(BlockDriverState *bs, |
c4b1fcc0 | 685 | void (*change_cb)(void *opaque), void *opaque); |
ea2384d3 | 686 | void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size); |
c4b1fcc0 FB |
687 | void bdrv_info(void); |
688 | BlockDriverState *bdrv_find(const char *name); | |
82c643ff | 689 | void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque); |
ea2384d3 FB |
690 | int bdrv_is_encrypted(BlockDriverState *bs); |
691 | int bdrv_set_key(BlockDriverState *bs, const char *key); | |
5fafdf24 | 692 | void bdrv_iterate_format(void (*it)(void *opaque, const char *name), |
ea2384d3 FB |
693 | void *opaque); |
694 | const char *bdrv_get_device_name(BlockDriverState *bs); | |
5fafdf24 | 695 | int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, |
faea38e7 FB |
696 | const uint8_t *buf, int nb_sectors); |
697 | int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi); | |
c4b1fcc0 | 698 | |
5fafdf24 | 699 | void bdrv_get_backing_filename(BlockDriverState *bs, |
83f64091 | 700 | char *filename, int filename_size); |
5fafdf24 | 701 | int bdrv_snapshot_create(BlockDriverState *bs, |
faea38e7 | 702 | QEMUSnapshotInfo *sn_info); |
5fafdf24 | 703 | int bdrv_snapshot_goto(BlockDriverState *bs, |
faea38e7 FB |
704 | const char *snapshot_id); |
705 | int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id); | |
5fafdf24 | 706 | int bdrv_snapshot_list(BlockDriverState *bs, |
faea38e7 FB |
707 | QEMUSnapshotInfo **psn_info); |
708 | char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn); | |
709 | ||
710 | char *get_human_readable_size(char *buf, int buf_size, int64_t size); | |
83f64091 FB |
711 | int path_is_absolute(const char *path); |
712 | void path_combine(char *dest, int dest_size, | |
713 | const char *base_path, | |
714 | const char *filename); | |
ea2384d3 FB |
715 | |
716 | #ifndef QEMU_TOOL | |
54fa5af5 | 717 | |
5fafdf24 | 718 | typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
54fa5af5 FB |
719 | int boot_device, |
720 | DisplayState *ds, const char **fd_filename, int snapshot, | |
721 | const char *kernel_filename, const char *kernel_cmdline, | |
94fc95cd | 722 | const char *initrd_filename, const char *cpu_model); |
54fa5af5 FB |
723 | |
724 | typedef struct QEMUMachine { | |
725 | const char *name; | |
726 | const char *desc; | |
727 | QEMUMachineInitFunc *init; | |
728 | struct QEMUMachine *next; | |
729 | } QEMUMachine; | |
730 | ||
731 | int qemu_register_machine(QEMUMachine *m); | |
732 | ||
733 | typedef void SetIRQFunc(void *opaque, int irq_num, int level); | |
734 | ||
94fc95cd JM |
735 | #if defined(TARGET_PPC) |
736 | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
737 | #endif | |
738 | ||
33d68b5f TS |
739 | #if defined(TARGET_MIPS) |
740 | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
741 | #endif | |
742 | ||
d537cf6c PB |
743 | #include "hw/irq.h" |
744 | ||
26aa7d72 FB |
745 | /* ISA bus */ |
746 | ||
747 | extern target_phys_addr_t isa_mem_base; | |
748 | ||
749 | typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); | |
750 | typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); | |
751 | ||
5fafdf24 | 752 | int register_ioport_read(int start, int length, int size, |
26aa7d72 | 753 | IOPortReadFunc *func, void *opaque); |
5fafdf24 | 754 | int register_ioport_write(int start, int length, int size, |
26aa7d72 | 755 | IOPortWriteFunc *func, void *opaque); |
69b91039 FB |
756 | void isa_unassign_ioport(int start, int length); |
757 | ||
aef445bd PB |
758 | void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); |
759 | ||
69b91039 FB |
760 | /* PCI bus */ |
761 | ||
69b91039 FB |
762 | extern target_phys_addr_t pci_mem_base; |
763 | ||
46e50e9d | 764 | typedef struct PCIBus PCIBus; |
69b91039 FB |
765 | typedef struct PCIDevice PCIDevice; |
766 | ||
5fafdf24 | 767 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
69b91039 | 768 | uint32_t address, uint32_t data, int len); |
5fafdf24 | 769 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, |
69b91039 | 770 | uint32_t address, int len); |
5fafdf24 | 771 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
69b91039 FB |
772 | uint32_t addr, uint32_t size, int type); |
773 | ||
774 | #define PCI_ADDRESS_SPACE_MEM 0x00 | |
775 | #define PCI_ADDRESS_SPACE_IO 0x01 | |
776 | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 | |
777 | ||
778 | typedef struct PCIIORegion { | |
5768f5ac | 779 | uint32_t addr; /* current PCI mapping address. -1 means not mapped */ |
69b91039 FB |
780 | uint32_t size; |
781 | uint8_t type; | |
782 | PCIMapIORegionFunc *map_func; | |
783 | } PCIIORegion; | |
784 | ||
8a8696a3 FB |
785 | #define PCI_ROM_SLOT 6 |
786 | #define PCI_NUM_REGIONS 7 | |
502a5395 PB |
787 | |
788 | #define PCI_DEVICES_MAX 64 | |
789 | ||
790 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ | |
791 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
792 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
793 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
794 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
795 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ | |
796 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ | |
797 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
798 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
799 | #define PCI_MAX_LAT 0x3f /* 8 bits */ | |
800 | ||
69b91039 FB |
801 | struct PCIDevice { |
802 | /* PCI config space */ | |
803 | uint8_t config[256]; | |
804 | ||
805 | /* the following fields are read only */ | |
46e50e9d | 806 | PCIBus *bus; |
69b91039 FB |
807 | int devfn; |
808 | char name[64]; | |
8a8696a3 | 809 | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
3b46e624 | 810 | |
69b91039 FB |
811 | /* do not access the following fields */ |
812 | PCIConfigReadFunc *config_read; | |
813 | PCIConfigWriteFunc *config_write; | |
502a5395 | 814 | /* ??? This is a PC-specific hack, and should be removed. */ |
5768f5ac | 815 | int irq_index; |
d2b59317 | 816 | |
d537cf6c PB |
817 | /* IRQ objects for the INTA-INTD pins. */ |
818 | qemu_irq *irq; | |
819 | ||
d2b59317 PB |
820 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
821 | int irq_state[4]; | |
69b91039 FB |
822 | }; |
823 | ||
46e50e9d FB |
824 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
825 | int instance_size, int devfn, | |
5fafdf24 | 826 | PCIConfigReadFunc *config_read, |
69b91039 FB |
827 | PCIConfigWriteFunc *config_write); |
828 | ||
5fafdf24 TS |
829 | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
830 | uint32_t size, int type, | |
69b91039 FB |
831 | PCIMapIORegionFunc *map_func); |
832 | ||
5fafdf24 | 833 | uint32_t pci_default_read_config(PCIDevice *d, |
5768f5ac | 834 | uint32_t address, int len); |
5fafdf24 | 835 | void pci_default_write_config(PCIDevice *d, |
5768f5ac | 836 | uint32_t address, uint32_t val, int len); |
89b6b508 FB |
837 | void pci_device_save(PCIDevice *s, QEMUFile *f); |
838 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
5768f5ac | 839 | |
d537cf6c | 840 | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
d2b59317 PB |
841 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
842 | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
d537cf6c | 843 | qemu_irq *pic, int devfn_min, int nirq); |
502a5395 | 844 | |
abcebc7e | 845 | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
502a5395 PB |
846 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
847 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); | |
848 | int pci_bus_num(PCIBus *s); | |
80b3ada7 | 849 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
9995c51f | 850 | |
5768f5ac | 851 | void pci_info(void); |
80b3ada7 PB |
852 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id, |
853 | pci_map_irq_fn map_irq, const char *name); | |
26aa7d72 | 854 | |
502a5395 | 855 | /* prep_pci.c */ |
d537cf6c | 856 | PCIBus *pci_prep_init(qemu_irq *pic); |
77d4bc34 | 857 | |
502a5395 | 858 | /* grackle_pci.c */ |
d537cf6c | 859 | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); |
502a5395 PB |
860 | |
861 | /* unin_pci.c */ | |
d537cf6c | 862 | PCIBus *pci_pmac_init(qemu_irq *pic); |
502a5395 PB |
863 | |
864 | /* apb_pci.c */ | |
5b9693dc | 865 | PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
d537cf6c | 866 | qemu_irq *pic); |
502a5395 | 867 | |
d537cf6c | 868 | PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview); |
502a5395 PB |
869 | |
870 | /* piix_pci.c */ | |
d537cf6c | 871 | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); |
f00fc47c | 872 | void i440fx_set_smm(PCIDevice *d, int val); |
8f1c91d8 | 873 | int piix3_init(PCIBus *bus, int devfn); |
f00fc47c | 874 | void i440fx_init_memory_mappings(PCIDevice *d); |
a41b2ff2 | 875 | |
5856de80 TS |
876 | int piix4_init(PCIBus *bus, int devfn); |
877 | ||
28b9b5af | 878 | /* openpic.c */ |
e9df014c | 879 | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ |
47103572 | 880 | enum { |
e9df014c JM |
881 | OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
882 | OPENPIC_OUTPUT_CINT, /* critical IRQ */ | |
883 | OPENPIC_OUTPUT_MCK, /* Machine check event */ | |
884 | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ | |
885 | OPENPIC_OUTPUT_RESET, /* Core reset event */ | |
886 | OPENPIC_OUTPUT_NB, | |
47103572 | 887 | }; |
e9df014c JM |
888 | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
889 | qemu_irq **irqs, qemu_irq irq_out); | |
28b9b5af | 890 | |
54fa5af5 | 891 | /* heathrow_pic.c */ |
d537cf6c | 892 | qemu_irq *heathrow_pic_init(int *pmem_index); |
54fa5af5 | 893 | |
fde7d5bd | 894 | /* gt64xxx.c */ |
d537cf6c | 895 | PCIBus *pci_gt64120_init(qemu_irq *pic); |
fde7d5bd | 896 | |
6a36d84e FB |
897 | #ifdef HAS_AUDIO |
898 | struct soundhw { | |
899 | const char *name; | |
900 | const char *descr; | |
901 | int enabled; | |
902 | int isa; | |
903 | union { | |
d537cf6c | 904 | int (*init_isa) (AudioState *s, qemu_irq *pic); |
6a36d84e FB |
905 | int (*init_pci) (PCIBus *bus, AudioState *s); |
906 | } init; | |
907 | }; | |
908 | ||
909 | extern struct soundhw soundhw[]; | |
910 | #endif | |
911 | ||
313aa567 FB |
912 | /* vga.c */ |
913 | ||
eee0b836 | 914 | #ifndef TARGET_SPARC |
74a14f22 | 915 | #define VGA_RAM_SIZE (8192 * 1024) |
eee0b836 BS |
916 | #else |
917 | #define VGA_RAM_SIZE (9 * 1024 * 1024) | |
918 | #endif | |
313aa567 | 919 | |
82c643ff | 920 | struct DisplayState { |
313aa567 FB |
921 | uint8_t *data; |
922 | int linesize; | |
923 | int depth; | |
d3079cd2 | 924 | int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
82c643ff FB |
925 | int width; |
926 | int height; | |
24236869 | 927 | void *opaque; |
740733bb | 928 | QEMUTimer *gui_timer; |
24236869 | 929 | |
313aa567 FB |
930 | void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
931 | void (*dpy_resize)(struct DisplayState *s, int w, int h); | |
932 | void (*dpy_refresh)(struct DisplayState *s); | |
d34cab9f TS |
933 | void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
934 | int dst_x, int dst_y, int w, int h); | |
935 | void (*dpy_fill)(struct DisplayState *s, int x, int y, | |
936 | int w, int h, uint32_t c); | |
937 | void (*mouse_set)(int x, int y, int on); | |
938 | void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, | |
939 | uint8_t *image, uint8_t *mask); | |
82c643ff | 940 | }; |
313aa567 FB |
941 | |
942 | static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) | |
943 | { | |
944 | s->dpy_update(s, x, y, w, h); | |
945 | } | |
946 | ||
947 | static inline void dpy_resize(DisplayState *s, int w, int h) | |
948 | { | |
949 | s->dpy_resize(s, w, h); | |
950 | } | |
951 | ||
5fafdf24 | 952 | int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, |
89b6b508 | 953 | unsigned long vga_ram_offset, int vga_ram_size); |
5fafdf24 | 954 | int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, |
89b6b508 FB |
955 | unsigned long vga_ram_offset, int vga_ram_size, |
956 | unsigned long vga_bios_offset, int vga_bios_size); | |
2abec30b TS |
957 | int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base, |
958 | unsigned long vga_ram_offset, int vga_ram_size, | |
959 | target_phys_addr_t vram_base, target_phys_addr_t ctrl_base, | |
960 | int it_shift); | |
313aa567 | 961 | |
d6bfa22f | 962 | /* cirrus_vga.c */ |
5fafdf24 | 963 | void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, |
d6bfa22f | 964 | unsigned long vga_ram_offset, int vga_ram_size); |
5fafdf24 | 965 | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, |
d6bfa22f FB |
966 | unsigned long vga_ram_offset, int vga_ram_size); |
967 | ||
d34cab9f TS |
968 | /* vmware_vga.c */ |
969 | void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, | |
970 | unsigned long vga_ram_offset, int vga_ram_size); | |
971 | ||
313aa567 | 972 | /* sdl.c */ |
43523e93 | 973 | void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
313aa567 | 974 | |
da4dbf74 FB |
975 | /* cocoa.m */ |
976 | void cocoa_display_init(DisplayState *ds, int full_screen); | |
977 | ||
24236869 | 978 | /* vnc.c */ |
71cab5ca TS |
979 | void vnc_display_init(DisplayState *ds); |
980 | void vnc_display_close(DisplayState *ds); | |
981 | int vnc_display_open(DisplayState *ds, const char *display); | |
70848515 | 982 | int vnc_display_password(DisplayState *ds, const char *password); |
a9ce8590 | 983 | void do_info_vnc(void); |
24236869 | 984 | |
6070dd07 TS |
985 | /* x_keymap.c */ |
986 | extern uint8_t _translate_keycode(const int key); | |
987 | ||
5391d806 FB |
988 | /* ide.c */ |
989 | #define MAX_DISKS 4 | |
990 | ||
faea38e7 | 991 | extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
a1bb27b1 | 992 | extern BlockDriverState *sd_bdrv; |
3e3d5815 | 993 | extern BlockDriverState *mtd_bdrv; |
5391d806 | 994 | |
d537cf6c | 995 | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
69b91039 | 996 | BlockDriverState *hd0, BlockDriverState *hd1); |
54fa5af5 FB |
997 | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, |
998 | int secondary_ide_enabled); | |
d537cf6c PB |
999 | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
1000 | qemu_irq *pic); | |
afcc3cdf TS |
1001 | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
1002 | qemu_irq *pic); | |
d537cf6c | 1003 | int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq); |
5391d806 | 1004 | |
2e5d83bb PB |
1005 | /* cdrom.c */ |
1006 | int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); | |
1007 | int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); | |
1008 | ||
9542611a TS |
1009 | /* ds1225y.c */ |
1010 | typedef struct ds1225y_t ds1225y_t; | |
71db710f | 1011 | ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); |
9542611a | 1012 | |
1d14ffa9 | 1013 | /* es1370.c */ |
c0fe3827 | 1014 | int es1370_init (PCIBus *bus, AudioState *s); |
1d14ffa9 | 1015 | |
fb065187 | 1016 | /* sb16.c */ |
d537cf6c | 1017 | int SB16_init (AudioState *s, qemu_irq *pic); |
fb065187 FB |
1018 | |
1019 | /* adlib.c */ | |
d537cf6c | 1020 | int Adlib_init (AudioState *s, qemu_irq *pic); |
fb065187 FB |
1021 | |
1022 | /* gus.c */ | |
d537cf6c | 1023 | int GUS_init (AudioState *s, qemu_irq *pic); |
27503323 FB |
1024 | |
1025 | /* dma.c */ | |
85571bc7 | 1026 | typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
27503323 | 1027 | int DMA_get_channel_mode (int nchan); |
85571bc7 FB |
1028 | int DMA_read_memory (int nchan, void *buf, int pos, int size); |
1029 | int DMA_write_memory (int nchan, void *buf, int pos, int size); | |
27503323 FB |
1030 | void DMA_hold_DREQ (int nchan); |
1031 | void DMA_release_DREQ (int nchan); | |
16f62432 | 1032 | void DMA_schedule(int nchan); |
27503323 | 1033 | void DMA_run (void); |
28b9b5af | 1034 | void DMA_init (int high_page_enable); |
27503323 | 1035 | void DMA_register_channel (int nchan, |
85571bc7 FB |
1036 | DMA_transfer_handler transfer_handler, |
1037 | void *opaque); | |
7138fcfb FB |
1038 | /* fdc.c */ |
1039 | #define MAX_FD 2 | |
1040 | extern BlockDriverState *fd_table[MAX_FD]; | |
1041 | ||
baca51fa FB |
1042 | typedef struct fdctrl_t fdctrl_t; |
1043 | ||
5fafdf24 | 1044 | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
5dcb6b91 | 1045 | target_phys_addr_t io_base, |
baca51fa FB |
1046 | BlockDriverState **fds); |
1047 | int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); | |
7138fcfb | 1048 | |
663e8e51 TS |
1049 | /* eepro100.c */ |
1050 | ||
1051 | void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); | |
1052 | void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); | |
1053 | void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); | |
1054 | ||
80cabfad FB |
1055 | /* ne2000.c */ |
1056 | ||
d537cf6c | 1057 | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); |
abcebc7e | 1058 | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
80cabfad | 1059 | |
a41b2ff2 PB |
1060 | /* rtl8139.c */ |
1061 | ||
abcebc7e | 1062 | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
a41b2ff2 | 1063 | |
e3c2613f FB |
1064 | /* pcnet.c */ |
1065 | ||
abcebc7e | 1066 | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
70c0de96 | 1067 | void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
2d069bab | 1068 | qemu_irq irq, qemu_irq *reset); |
67e999be | 1069 | |
548df2ac TS |
1070 | /* vmmouse.c */ |
1071 | void *vmmouse_init(void *m); | |
e3c2613f | 1072 | |
591a6d62 TS |
1073 | /* vmport.c */ |
1074 | #ifdef TARGET_I386 | |
1075 | void vmport_init(CPUState *env); | |
1076 | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); | |
1077 | #endif | |
1078 | ||
80cabfad FB |
1079 | /* pckbd.c */ |
1080 | ||
b92bb99b | 1081 | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); |
71db710f BS |
1082 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, |
1083 | target_phys_addr_t base, int it_shift); | |
80cabfad FB |
1084 | |
1085 | /* mc146818rtc.c */ | |
1086 | ||
8a7ddc38 | 1087 | typedef struct RTCState RTCState; |
80cabfad | 1088 | |
d537cf6c | 1089 | RTCState *rtc_init(int base, qemu_irq irq); |
18c6e2ff | 1090 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq); |
8a7ddc38 FB |
1091 | void rtc_set_memory(RTCState *s, int addr, int val); |
1092 | void rtc_set_date(RTCState *s, const struct tm *tm); | |
80cabfad FB |
1093 | |
1094 | /* serial.c */ | |
1095 | ||
c4b1fcc0 | 1096 | typedef struct SerialState SerialState; |
d537cf6c | 1097 | SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr); |
71db710f | 1098 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, |
d537cf6c | 1099 | qemu_irq irq, CharDriverState *chr, |
a4bc3afc TS |
1100 | int ioregister); |
1101 | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr); | |
1102 | void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); | |
1103 | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr); | |
1104 | void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); | |
1105 | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr); | |
1106 | void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); | |
80cabfad | 1107 | |
6508fe59 FB |
1108 | /* parallel.c */ |
1109 | ||
1110 | typedef struct ParallelState ParallelState; | |
d537cf6c | 1111 | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr); |
d60532ca | 1112 | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr); |
6508fe59 | 1113 | |
80cabfad FB |
1114 | /* i8259.c */ |
1115 | ||
3de388f6 FB |
1116 | typedef struct PicState2 PicState2; |
1117 | extern PicState2 *isa_pic; | |
80cabfad | 1118 | void pic_set_irq(int irq, int level); |
54fa5af5 | 1119 | void pic_set_irq_new(void *opaque, int irq, int level); |
d537cf6c | 1120 | qemu_irq *i8259_init(qemu_irq parent_irq); |
d592d303 FB |
1121 | void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, |
1122 | void *alt_irq_opaque); | |
3de388f6 FB |
1123 | int pic_read_irq(PicState2 *s); |
1124 | void pic_update_irq(PicState2 *s); | |
1125 | uint32_t pic_intack_read(PicState2 *s); | |
c20709aa | 1126 | void pic_info(void); |
4a0fb71e | 1127 | void irq_info(void); |
80cabfad | 1128 | |
c27004ec | 1129 | /* APIC */ |
d592d303 FB |
1130 | typedef struct IOAPICState IOAPICState; |
1131 | ||
c27004ec FB |
1132 | int apic_init(CPUState *env); |
1133 | int apic_get_interrupt(CPUState *env); | |
d592d303 FB |
1134 | IOAPICState *ioapic_init(void); |
1135 | void ioapic_set_irq(void *opaque, int vector, int level); | |
c27004ec | 1136 | |
80cabfad FB |
1137 | /* i8254.c */ |
1138 | ||
1139 | #define PIT_FREQ 1193182 | |
1140 | ||
ec844b96 FB |
1141 | typedef struct PITState PITState; |
1142 | ||
d537cf6c | 1143 | PITState *pit_init(int base, qemu_irq irq); |
ec844b96 FB |
1144 | void pit_set_gate(PITState *pit, int channel, int val); |
1145 | int pit_get_gate(PITState *pit, int channel); | |
fd06c375 FB |
1146 | int pit_get_initial_count(PITState *pit, int channel); |
1147 | int pit_get_mode(PITState *pit, int channel); | |
ec844b96 | 1148 | int pit_get_out(PITState *pit, int channel, int64_t current_time); |
80cabfad | 1149 | |
31211df1 TS |
1150 | /* jazz_led.c */ |
1151 | extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base); | |
1152 | ||
fd06c375 FB |
1153 | /* pcspk.c */ |
1154 | void pcspk_init(PITState *); | |
d537cf6c | 1155 | int pcspk_audio_init(AudioState *, qemu_irq *pic); |
fd06c375 | 1156 | |
0ff596d0 PB |
1157 | #include "hw/i2c.h" |
1158 | ||
3fffc223 TS |
1159 | #include "hw/smbus.h" |
1160 | ||
6515b203 FB |
1161 | /* acpi.c */ |
1162 | extern int acpi_enabled; | |
7b717336 | 1163 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base); |
3fffc223 | 1164 | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); |
6515b203 FB |
1165 | void acpi_bios_init(void); |
1166 | ||
80cabfad | 1167 | /* pc.c */ |
54fa5af5 | 1168 | extern QEMUMachine pc_machine; |
3dbbdc25 | 1169 | extern QEMUMachine isapc_machine; |
52ca8d6a | 1170 | extern int fd_bootchk; |
80cabfad | 1171 | |
6a00d601 FB |
1172 | void ioport_set_a20(int enable); |
1173 | int ioport_get_a20(void); | |
1174 | ||
26aa7d72 | 1175 | /* ppc.c */ |
54fa5af5 FB |
1176 | extern QEMUMachine prep_machine; |
1177 | extern QEMUMachine core99_machine; | |
1178 | extern QEMUMachine heathrow_machine; | |
1a6c0886 JM |
1179 | extern QEMUMachine ref405ep_machine; |
1180 | extern QEMUMachine taihu_machine; | |
54fa5af5 | 1181 | |
6af0bf9c FB |
1182 | /* mips_r4k.c */ |
1183 | extern QEMUMachine mips_machine; | |
1184 | ||
5856de80 TS |
1185 | /* mips_malta.c */ |
1186 | extern QEMUMachine mips_malta_machine; | |
1187 | ||
ad6fe1d2 | 1188 | /* mips_int.c */ |
d537cf6c | 1189 | extern void cpu_mips_irq_init_cpu(CPUState *env); |
4de9b249 | 1190 | |
ad6fe1d2 TS |
1191 | /* mips_pica61.c */ |
1192 | extern QEMUMachine mips_pica61_machine; | |
1193 | ||
e16fe40c TS |
1194 | /* mips_timer.c */ |
1195 | extern void cpu_mips_clock_init(CPUState *); | |
1196 | extern void cpu_mips_irqctrl_init (void); | |
1197 | ||
27c7ca7e FB |
1198 | /* shix.c */ |
1199 | extern QEMUMachine shix_machine; | |
1200 | ||
8cc43fef | 1201 | #ifdef TARGET_PPC |
47103572 | 1202 | /* PowerPC hardware exceptions management helpers */ |
8ecc7913 JM |
1203 | typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
1204 | typedef struct clk_setup_t clk_setup_t; | |
1205 | struct clk_setup_t { | |
1206 | clk_setup_cb cb; | |
1207 | void *opaque; | |
1208 | }; | |
1209 | static inline void clk_setup (clk_setup_t *clk, uint32_t freq) | |
1210 | { | |
1211 | if (clk->cb != NULL) | |
1212 | (*clk->cb)(clk->opaque, freq); | |
1213 | } | |
1214 | ||
1215 | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); | |
2e719ba3 JM |
1216 | /* Embedded PowerPC DCR management */ |
1217 | typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); | |
1218 | typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); | |
1219 | int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), | |
1220 | int (*dcr_write_error)(int dcrn)); | |
1221 | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, | |
1222 | dcr_read_cb drc_read, dcr_write_cb dcr_write); | |
8ecc7913 | 1223 | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
4a057712 JM |
1224 | /* Embedded PowerPC reset */ |
1225 | void ppc40x_core_reset (CPUState *env); | |
1226 | void ppc40x_chip_reset (CPUState *env); | |
1227 | void ppc40x_system_reset (CPUState *env); | |
8cc43fef | 1228 | #endif |
64201201 | 1229 | void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
77d4bc34 FB |
1230 | |
1231 | extern CPUWriteMemoryFunc *PPC_io_write[]; | |
1232 | extern CPUReadMemoryFunc *PPC_io_read[]; | |
54fa5af5 | 1233 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
26aa7d72 | 1234 | |
e95c8d51 | 1235 | /* sun4m.c */ |
e0353fe2 | 1236 | extern QEMUMachine ss5_machine, ss10_machine; |
e95c8d51 FB |
1237 | |
1238 | /* iommu.c */ | |
5dcb6b91 | 1239 | void *iommu_init(target_phys_addr_t addr); |
67e999be | 1240 | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
a917d384 | 1241 | uint8_t *buf, int len, int is_write); |
67e999be FB |
1242 | static inline void sparc_iommu_memory_read(void *opaque, |
1243 | target_phys_addr_t addr, | |
1244 | uint8_t *buf, int len) | |
1245 | { | |
1246 | sparc_iommu_memory_rw(opaque, addr, buf, len, 0); | |
1247 | } | |
e95c8d51 | 1248 | |
67e999be FB |
1249 | static inline void sparc_iommu_memory_write(void *opaque, |
1250 | target_phys_addr_t addr, | |
1251 | uint8_t *buf, int len) | |
1252 | { | |
1253 | sparc_iommu_memory_rw(opaque, addr, buf, len, 1); | |
1254 | } | |
e95c8d51 FB |
1255 | |
1256 | /* tcx.c */ | |
5dcb6b91 BS |
1257 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, |
1258 | unsigned long vram_offset, int vram_size, int width, int height, | |
eee0b836 | 1259 | int depth); |
e80cfcfc FB |
1260 | |
1261 | /* slavio_intctl.c */ | |
5dcb6b91 | 1262 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, |
d537cf6c | 1263 | const uint32_t *intbit_to_level, |
d7edfd27 | 1264 | qemu_irq **irq, qemu_irq **cpu_irq, |
b3a23197 | 1265 | qemu_irq **parent_irq, unsigned int cputimer); |
e80cfcfc FB |
1266 | void slavio_pic_info(void *opaque); |
1267 | void slavio_irq_info(void *opaque); | |
e95c8d51 | 1268 | |
5fe141fd FB |
1269 | /* loader.c */ |
1270 | int get_image_size(const char *filename); | |
1271 | int load_image(const char *filename, uint8_t *addr); | |
74287114 TS |
1272 | int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1273 | uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); | |
e80cfcfc | 1274 | int load_aout(const char *filename, uint8_t *addr); |
1c7b3754 | 1275 | int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
e80cfcfc FB |
1276 | |
1277 | /* slavio_timer.c */ | |
d7edfd27 | 1278 | void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode); |
8d5f07fa | 1279 | |
e80cfcfc | 1280 | /* slavio_serial.c */ |
5dcb6b91 BS |
1281 | SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
1282 | CharDriverState *chr1, CharDriverState *chr2); | |
1283 | void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq); | |
e95c8d51 | 1284 | |
3475187d | 1285 | /* slavio_misc.c */ |
5dcb6b91 BS |
1286 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, |
1287 | qemu_irq irq); | |
3475187d FB |
1288 | void slavio_set_power_fail(void *opaque, int power_failing); |
1289 | ||
6f7e9aec | 1290 | /* esp.c */ |
fa1fb14c | 1291 | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
5dcb6b91 | 1292 | void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, |
2d069bab | 1293 | void *dma_opaque, qemu_irq irq, qemu_irq *reset); |
67e999be FB |
1294 | |
1295 | /* sparc32_dma.c */ | |
70c0de96 | 1296 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
2d069bab | 1297 | void *iommu, qemu_irq **dev_irq, qemu_irq **reset); |
5fafdf24 | 1298 | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
9b94dc32 | 1299 | uint8_t *buf, int len, int do_bswap); |
5fafdf24 | 1300 | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
9b94dc32 | 1301 | uint8_t *buf, int len, int do_bswap); |
67e999be FB |
1302 | void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1303 | void espdma_memory_write(void *opaque, uint8_t *buf, int len); | |
6f7e9aec | 1304 | |
b8174937 FB |
1305 | /* cs4231.c */ |
1306 | void cs_init(target_phys_addr_t base, int irq, void *intctl); | |
1307 | ||
3475187d FB |
1308 | /* sun4u.c */ |
1309 | extern QEMUMachine sun4u_machine; | |
1310 | ||
64201201 FB |
1311 | /* NVRAM helpers */ |
1312 | #include "hw/m48t59.h" | |
1313 | ||
1314 | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value); | |
1315 | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr); | |
1316 | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value); | |
1317 | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr); | |
1318 | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value); | |
1319 | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr); | |
1320 | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr, | |
1321 | const unsigned char *str, uint32_t max); | |
1322 | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max); | |
1323 | void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr, | |
1324 | uint32_t start, uint32_t count); | |
1325 | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, | |
1326 | const unsigned char *arch, | |
1327 | uint32_t RAM_size, int boot_device, | |
1328 | uint32_t kernel_image, uint32_t kernel_size, | |
28b9b5af | 1329 | const char *cmdline, |
64201201 | 1330 | uint32_t initrd_image, uint32_t initrd_size, |
28b9b5af FB |
1331 | uint32_t NVRAM_image, |
1332 | int width, int height, int depth); | |
64201201 | 1333 | |
63066f4f FB |
1334 | /* adb.c */ |
1335 | ||
1336 | #define MAX_ADB_DEVICES 16 | |
1337 | ||
e2733d20 | 1338 | #define ADB_MAX_OUT_LEN 16 |
63066f4f | 1339 | |
e2733d20 | 1340 | typedef struct ADBDevice ADBDevice; |
63066f4f | 1341 | |
e2733d20 FB |
1342 | /* buf = NULL means polling */ |
1343 | typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, | |
1344 | const uint8_t *buf, int len); | |
12c28fed FB |
1345 | typedef int ADBDeviceReset(ADBDevice *d); |
1346 | ||
63066f4f FB |
1347 | struct ADBDevice { |
1348 | struct ADBBusState *bus; | |
1349 | int devaddr; | |
1350 | int handler; | |
e2733d20 | 1351 | ADBDeviceRequest *devreq; |
12c28fed | 1352 | ADBDeviceReset *devreset; |
63066f4f FB |
1353 | void *opaque; |
1354 | }; | |
1355 | ||
1356 | typedef struct ADBBusState { | |
1357 | ADBDevice devices[MAX_ADB_DEVICES]; | |
1358 | int nb_devices; | |
e2733d20 | 1359 | int poll_index; |
63066f4f FB |
1360 | } ADBBusState; |
1361 | ||
e2733d20 FB |
1362 | int adb_request(ADBBusState *s, uint8_t *buf_out, |
1363 | const uint8_t *buf, int len); | |
1364 | int adb_poll(ADBBusState *s, uint8_t *buf_out); | |
63066f4f | 1365 | |
5fafdf24 TS |
1366 | ADBDevice *adb_register_device(ADBBusState *s, int devaddr, |
1367 | ADBDeviceRequest *devreq, | |
1368 | ADBDeviceReset *devreset, | |
63066f4f FB |
1369 | void *opaque); |
1370 | void adb_kbd_init(ADBBusState *bus); | |
1371 | void adb_mouse_init(ADBBusState *bus); | |
1372 | ||
1373 | /* cuda.c */ | |
1374 | ||
1375 | extern ADBBusState adb_bus; | |
d537cf6c | 1376 | int cuda_init(qemu_irq irq); |
63066f4f | 1377 | |
bb36d470 FB |
1378 | #include "hw/usb.h" |
1379 | ||
a594cfbf FB |
1380 | /* usb ports of the VM */ |
1381 | ||
0d92ed30 PB |
1382 | void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1383 | usb_attachfn attach); | |
a594cfbf | 1384 | |
0d92ed30 | 1385 | #define VM_USB_HUB_SIZE 8 |
a594cfbf FB |
1386 | |
1387 | void do_usb_add(const char *devname); | |
1388 | void do_usb_del(const char *devname); | |
1389 | void usb_info(void); | |
1390 | ||
2e5d83bb | 1391 | /* scsi-disk.c */ |
4d611c9a PB |
1392 | enum scsi_reason { |
1393 | SCSI_REASON_DONE, /* Command complete. */ | |
1394 | SCSI_REASON_DATA /* Transfer complete, more data required. */ | |
1395 | }; | |
1396 | ||
2e5d83bb | 1397 | typedef struct SCSIDevice SCSIDevice; |
a917d384 PB |
1398 | typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1399 | uint32_t arg); | |
2e5d83bb PB |
1400 | |
1401 | SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, | |
a917d384 | 1402 | int tcq, |
2e5d83bb PB |
1403 | scsi_completionfn completion, |
1404 | void *opaque); | |
1405 | void scsi_disk_destroy(SCSIDevice *s); | |
1406 | ||
0fc5c15a | 1407 | int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun); |
4d611c9a PB |
1408 | /* SCSI data transfers are asynchrnonous. However, unlike the block IO |
1409 | layer the completion routine may be called directly by | |
1410 | scsi_{read,write}_data. */ | |
a917d384 PB |
1411 | void scsi_read_data(SCSIDevice *s, uint32_t tag); |
1412 | int scsi_write_data(SCSIDevice *s, uint32_t tag); | |
1413 | void scsi_cancel_io(SCSIDevice *s, uint32_t tag); | |
1414 | uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); | |
2e5d83bb | 1415 | |
7d8406be PB |
1416 | /* lsi53c895a.c */ |
1417 | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); | |
1418 | void *lsi_scsi_init(PCIBus *bus, int devfn); | |
1419 | ||
b5ff1b31 | 1420 | /* integratorcp.c */ |
3371d272 | 1421 | extern QEMUMachine integratorcp_machine; |
b5ff1b31 | 1422 | |
cdbdb648 PB |
1423 | /* versatilepb.c */ |
1424 | extern QEMUMachine versatilepb_machine; | |
16406950 | 1425 | extern QEMUMachine versatileab_machine; |
cdbdb648 | 1426 | |
e69954b9 PB |
1427 | /* realview.c */ |
1428 | extern QEMUMachine realview_machine; | |
1429 | ||
b00052e4 AZ |
1430 | /* spitz.c */ |
1431 | extern QEMUMachine akitapda_machine; | |
1432 | extern QEMUMachine spitzpda_machine; | |
1433 | extern QEMUMachine borzoipda_machine; | |
1434 | extern QEMUMachine terrierpda_machine; | |
1435 | ||
c3d2689d AZ |
1436 | /* palm.c */ |
1437 | extern QEMUMachine palmte_machine; | |
1438 | ||
daa57963 FB |
1439 | /* ps2.c */ |
1440 | void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); | |
1441 | void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); | |
1442 | void ps2_write_mouse(void *, int val); | |
1443 | void ps2_write_keyboard(void *, int val); | |
1444 | uint32_t ps2_read_data(void *); | |
1445 | void ps2_queue(void *, int b); | |
f94f5d71 | 1446 | void ps2_keyboard_set_translation(void *opaque, int mode); |
548df2ac | 1447 | void ps2_mouse_fake_event(void *opaque); |
daa57963 | 1448 | |
80337b66 | 1449 | /* smc91c111.c */ |
d537cf6c | 1450 | void smc91c111_init(NICInfo *, uint32_t, qemu_irq); |
80337b66 | 1451 | |
7e1543c2 PB |
1452 | /* pl031.c */ |
1453 | void pl031_init(uint32_t base, qemu_irq irq); | |
1454 | ||
bdd5003a | 1455 | /* pl110.c */ |
d537cf6c | 1456 | void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int); |
bdd5003a | 1457 | |
cdbdb648 | 1458 | /* pl011.c */ |
d537cf6c | 1459 | void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr); |
cdbdb648 PB |
1460 | |
1461 | /* pl050.c */ | |
d537cf6c | 1462 | void pl050_init(uint32_t base, qemu_irq irq, int is_mouse); |
cdbdb648 PB |
1463 | |
1464 | /* pl080.c */ | |
d537cf6c | 1465 | void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); |
cdbdb648 | 1466 | |
a1bb27b1 PB |
1467 | /* pl181.c */ |
1468 | void pl181_init(uint32_t base, BlockDriverState *bd, | |
d537cf6c | 1469 | qemu_irq irq0, qemu_irq irq1); |
a1bb27b1 | 1470 | |
cdbdb648 | 1471 | /* pl190.c */ |
d537cf6c | 1472 | qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq); |
cdbdb648 PB |
1473 | |
1474 | /* arm-timer.c */ | |
d537cf6c PB |
1475 | void sp804_init(uint32_t base, qemu_irq irq); |
1476 | void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); | |
cdbdb648 | 1477 | |
e69954b9 PB |
1478 | /* arm_sysctl.c */ |
1479 | void arm_sysctl_init(uint32_t base, uint32_t sys_id); | |
1480 | ||
1481 | /* arm_gic.c */ | |
d537cf6c | 1482 | qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq); |
e69954b9 | 1483 | |
16406950 PB |
1484 | /* arm_boot.c */ |
1485 | ||
daf90626 | 1486 | void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
16406950 | 1487 | const char *kernel_cmdline, const char *initrd_filename, |
9d551997 | 1488 | int board_id, target_phys_addr_t loader_start); |
16406950 | 1489 | |
27c7ca7e FB |
1490 | /* sh7750.c */ |
1491 | struct SH7750State; | |
1492 | ||
008a8818 | 1493 | struct SH7750State *sh7750_init(CPUState * cpu); |
27c7ca7e FB |
1494 | |
1495 | typedef struct { | |
1496 | /* The callback will be triggered if any of the designated lines change */ | |
1497 | uint16_t portamask_trigger; | |
1498 | uint16_t portbmask_trigger; | |
1499 | /* Return 0 if no action was taken */ | |
1500 | int (*port_change_cb) (uint16_t porta, uint16_t portb, | |
1501 | uint16_t * periph_pdtra, | |
1502 | uint16_t * periph_portdira, | |
1503 | uint16_t * periph_pdtrb, | |
1504 | uint16_t * periph_portdirb); | |
1505 | } sh7750_io_device; | |
1506 | ||
1507 | int sh7750_register_io_device(struct SH7750State *s, | |
1508 | sh7750_io_device * device); | |
1509 | /* tc58128.c */ | |
1510 | int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); | |
1511 | ||
29133e9a | 1512 | /* NOR flash devices */ |
86f55663 JM |
1513 | #define MAX_PFLASH 4 |
1514 | extern BlockDriverState *pflash_table[MAX_PFLASH]; | |
29133e9a FB |
1515 | typedef struct pflash_t pflash_t; |
1516 | ||
71db710f | 1517 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
29133e9a | 1518 | BlockDriverState *bs, |
71db710f | 1519 | uint32_t sector_len, int nb_blocs, int width, |
5fafdf24 | 1520 | uint16_t id0, uint16_t id1, |
29133e9a FB |
1521 | uint16_t id2, uint16_t id3); |
1522 | ||
3e3d5815 AZ |
1523 | /* nand.c */ |
1524 | struct nand_flash_s; | |
1525 | struct nand_flash_s *nand_init(int manf_id, int chip_id); | |
1526 | void nand_done(struct nand_flash_s *s); | |
5fafdf24 | 1527 | void nand_setpins(struct nand_flash_s *s, |
3e3d5815 AZ |
1528 | int cle, int ale, int ce, int wp, int gnd); |
1529 | void nand_getpins(struct nand_flash_s *s, int *rb); | |
1530 | void nand_setio(struct nand_flash_s *s, uint8_t value); | |
1531 | uint8_t nand_getio(struct nand_flash_s *s); | |
1532 | ||
1533 | #define NAND_MFR_TOSHIBA 0x98 | |
1534 | #define NAND_MFR_SAMSUNG 0xec | |
1535 | #define NAND_MFR_FUJITSU 0x04 | |
1536 | #define NAND_MFR_NATIONAL 0x8f | |
1537 | #define NAND_MFR_RENESAS 0x07 | |
1538 | #define NAND_MFR_STMICRO 0x20 | |
1539 | #define NAND_MFR_HYNIX 0xad | |
1540 | #define NAND_MFR_MICRON 0x2c | |
1541 | ||
1542 | #include "ecc.h" | |
1543 | ||
2a1d1880 AZ |
1544 | /* GPIO */ |
1545 | typedef void (*gpio_handler_t)(int line, int level, void *opaque); | |
1546 | ||
fd5a3b33 AZ |
1547 | /* ads7846.c */ |
1548 | struct ads7846_state_s; | |
1549 | uint32_t ads7846_read(void *opaque); | |
1550 | void ads7846_write(void *opaque, uint32_t value); | |
1551 | struct ads7846_state_s *ads7846_init(qemu_irq penirq); | |
1552 | ||
c824cacd AZ |
1553 | /* max111x.c */ |
1554 | struct max111x_s; | |
1555 | uint32_t max111x_read(void *opaque); | |
1556 | void max111x_write(void *opaque, uint32_t value); | |
1557 | struct max111x_s *max1110_init(qemu_irq cb); | |
1558 | struct max111x_s *max1111_init(qemu_irq cb); | |
1559 | void max111x_set_input(struct max111x_s *s, int line, uint8_t value); | |
1560 | ||
201a51fc AZ |
1561 | /* PCMCIA/Cardbus */ |
1562 | ||
1563 | struct pcmcia_socket_s { | |
1564 | qemu_irq irq; | |
1565 | int attached; | |
1566 | const char *slot_string; | |
1567 | const char *card_string; | |
1568 | }; | |
1569 | ||
1570 | void pcmcia_socket_register(struct pcmcia_socket_s *socket); | |
1571 | void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); | |
1572 | void pcmcia_info(void); | |
1573 | ||
1574 | struct pcmcia_card_s { | |
1575 | void *state; | |
1576 | struct pcmcia_socket_s *slot; | |
1577 | int (*attach)(void *state); | |
1578 | int (*detach)(void *state); | |
1579 | const uint8_t *cis; | |
1580 | int cis_len; | |
1581 | ||
1582 | /* Only valid if attached */ | |
9e315fa9 AZ |
1583 | uint8_t (*attr_read)(void *state, uint32_t address); |
1584 | void (*attr_write)(void *state, uint32_t address, uint8_t value); | |
1585 | uint16_t (*common_read)(void *state, uint32_t address); | |
1586 | void (*common_write)(void *state, uint32_t address, uint16_t value); | |
1587 | uint16_t (*io_read)(void *state, uint32_t address); | |
1588 | void (*io_write)(void *state, uint32_t address, uint16_t value); | |
201a51fc AZ |
1589 | }; |
1590 | ||
1591 | #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ | |
1592 | #define CISTPL_NO_LINK 0x14 /* No Link Tuple */ | |
1593 | #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ | |
1594 | #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ | |
1595 | #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ | |
1596 | #define CISTPL_CONFIG 0x1a /* Configuration Tuple */ | |
1597 | #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ | |
1598 | #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ | |
1599 | #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ | |
1600 | #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ | |
1601 | #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ | |
1602 | #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ | |
1603 | #define CISTPL_FUNCID 0x21 /* Function ID Tuple */ | |
1604 | #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ | |
1605 | #define CISTPL_END 0xff /* Tuple End */ | |
1606 | #define CISTPL_ENDMARK 0xff | |
1607 | ||
1608 | /* dscm1xxxx.c */ | |
1609 | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv); | |
1610 | ||
6963d7af PB |
1611 | /* ptimer.c */ |
1612 | typedef struct ptimer_state ptimer_state; | |
1613 | typedef void (*ptimer_cb)(void *opaque); | |
1614 | ||
1615 | ptimer_state *ptimer_init(QEMUBH *bh); | |
1616 | void ptimer_set_period(ptimer_state *s, int64_t period); | |
1617 | void ptimer_set_freq(ptimer_state *s, uint32_t freq); | |
8d05ea8a BS |
1618 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); |
1619 | uint64_t ptimer_get_count(ptimer_state *s); | |
1620 | void ptimer_set_count(ptimer_state *s, uint64_t count); | |
6963d7af PB |
1621 | void ptimer_run(ptimer_state *s, int oneshot); |
1622 | void ptimer_stop(ptimer_state *s); | |
8d05ea8a BS |
1623 | void qemu_put_ptimer(QEMUFile *f, ptimer_state *s); |
1624 | void qemu_get_ptimer(QEMUFile *f, ptimer_state *s); | |
6963d7af | 1625 | |
c1713132 AZ |
1626 | #include "hw/pxa.h" |
1627 | ||
c3d2689d AZ |
1628 | #include "hw/omap.h" |
1629 | ||
20dcee94 PB |
1630 | /* mcf_uart.c */ |
1631 | uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); | |
1632 | void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); | |
1633 | void *mcf_uart_init(qemu_irq irq, CharDriverState *chr); | |
1634 | void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, | |
1635 | CharDriverState *chr); | |
1636 | ||
1637 | /* mcf_intc.c */ | |
1638 | qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); | |
1639 | ||
7e049b8a PB |
1640 | /* mcf_fec.c */ |
1641 | void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq); | |
1642 | ||
0633879f PB |
1643 | /* mcf5206.c */ |
1644 | qemu_irq *mcf5206_init(uint32_t base, CPUState *env); | |
1645 | ||
1646 | /* an5206.c */ | |
1647 | extern QEMUMachine an5206_machine; | |
1648 | ||
20dcee94 PB |
1649 | /* mcf5208.c */ |
1650 | extern QEMUMachine mcf5208evb_machine; | |
1651 | ||
4046d913 PB |
1652 | #include "gdbstub.h" |
1653 | ||
ea2384d3 FB |
1654 | #endif /* defined(QEMU_TOOL) */ |
1655 | ||
c4b1fcc0 | 1656 | /* monitor.c */ |
82c643ff | 1657 | void monitor_init(CharDriverState *hd, int show_banner); |
ea2384d3 FB |
1658 | void term_puts(const char *str); |
1659 | void term_vprintf(const char *fmt, va_list ap); | |
40c3bac3 | 1660 | void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
fef30743 | 1661 | void term_print_filename(const char *filename); |
c4b1fcc0 FB |
1662 | void term_flush(void); |
1663 | void term_print_help(void); | |
ea2384d3 FB |
1664 | void monitor_readline(const char *prompt, int is_password, |
1665 | char *buf, int buf_size); | |
1666 | ||
1667 | /* readline.c */ | |
1668 | typedef void ReadLineFunc(void *opaque, const char *str); | |
1669 | ||
1670 | extern int completion_index; | |
1671 | void add_completion(const char *str); | |
1672 | void readline_handle_byte(int ch); | |
1673 | void readline_find_completion(const char *cmdline); | |
1674 | const char *readline_get_history(unsigned int index); | |
1675 | void readline_start(const char *prompt, int is_password, | |
1676 | ReadLineFunc *readline_func, void *opaque); | |
c4b1fcc0 | 1677 | |
5e6ad6f9 FB |
1678 | void kqemu_record_dump(void); |
1679 | ||
fc01f7e7 | 1680 | #endif /* VL_H */ |