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-no-frame option for sdl, by Christian Laursen.
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fc01f7e7
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1/*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#ifndef VL_H
25#define VL_H
26
67b915a5
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27/* we put basic includes here to avoid repeating them in device drivers */
28#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <inttypes.h>
85571bc7 33#include <limits.h>
8a7ddc38 34#include <time.h>
67b915a5
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35#include <ctype.h>
36#include <errno.h>
37#include <unistd.h>
38#include <fcntl.h>
7d3505c5 39#include <sys/stat.h>
67b915a5
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40
41#ifndef O_LARGEFILE
42#define O_LARGEFILE 0
43#endif
40c3bac3
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44#ifndef O_BINARY
45#define O_BINARY 0
46#endif
67b915a5 47
71c2fd5c
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48#ifndef ENOMEDIUM
49#define ENOMEDIUM ENODEV
50#endif
2e9671da 51
67b915a5 52#ifdef _WIN32
a18e524a 53#include <windows.h>
ac62f715 54#define fsync _commit
57d1a2b6
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55#define lseek _lseeki64
56#define ENOTSUP 4096
beac80cd
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57extern int qemu_ftruncate64(int, int64_t);
58#define ftruncate qemu_ftruncate64
59
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60
61static inline char *realpath(const char *path, char *resolved_path)
62{
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65}
ec3757de
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66
67#define PRId64 "I64d"
26a76461
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68#define PRIx64 "I64x"
69#define PRIu64 "I64u"
70#define PRIo64 "I64o"
67b915a5 71#endif
8a7ddc38 72
ea2384d3
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73#ifdef QEMU_TOOL
74
75/* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77#include "config-host.h"
78#include <setjmp.h>
79#include "osdep.h"
80#include "bswap.h"
81
82#else
83
4f209290 84#include "audio/audio.h"
16f62432
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85#include "cpu.h"
86
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87#endif /* !defined(QEMU_TOOL) */
88
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89#ifndef glue
90#define xglue(x, y) x ## y
91#define glue(x, y) xglue(x, y)
92#define stringify(s) tostring(s)
93#define tostring(s) #s
94#endif
95
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96#ifndef MIN
97#define MIN(a, b) (((a) < (b)) ? (a) : (b))
98#endif
99#ifndef MAX
100#define MAX(a, b) (((a) > (b)) ? (a) : (b))
101#endif
102
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103/* cutils.c */
104void pstrcpy(char *buf, int buf_size, const char *str);
105char *pstrcat(char *buf, int buf_size, const char *s);
106int strstart(const char *str, const char *val, const char **ptr);
107int stristart(const char *str, const char *val, const char **ptr);
108
33e3963e 109/* vl.c */
80cabfad 110uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
313aa567 111
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112void hw_error(const char *fmt, ...);
113
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114extern const char *bios_dir;
115
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116extern int vm_running;
117
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118typedef struct vm_change_state_entry VMChangeStateEntry;
119typedef void VMChangeStateHandler(void *opaque, int running);
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120typedef void VMStopHandler(void *opaque, int reason);
121
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122VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
123 void *opaque);
124void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
125
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126int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
127void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
128
129void vm_start(void);
130void vm_stop(int reason);
131
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132typedef void QEMUResetHandler(void *opaque);
133
134void qemu_register_reset(QEMUResetHandler *func, void *opaque);
135void qemu_system_reset_request(void);
136void qemu_system_shutdown_request(void);
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137void qemu_system_powerdown_request(void);
138#if !defined(TARGET_SPARC)
139// Please implement a power failure function to signal the OS
140#define qemu_system_powerdown() do{}while(0)
141#else
142void qemu_system_powerdown(void);
143#endif
bb0c6722 144
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145void main_loop_wait(int timeout);
146
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147extern int ram_size;
148extern int bios_size;
ee22c2f7 149extern int rtc_utc;
1f04275e 150extern int cirrus_vga_enabled;
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151extern int graphic_width;
152extern int graphic_height;
153extern int graphic_depth;
3d11d0eb 154extern const char *keyboard_layout;
d993e026 155extern int kqemu_allowed;
a09db21f 156extern int win2k_install_hack;
bb36d470 157extern int usb_enabled;
6a00d601 158extern int smp_cpus;
667accab 159extern int no_quit;
8e71621f 160extern int semihosting_enabled;
3c07f8e8 161extern int autostart;
0ced6589 162
9ae02555
TS
163#define MAX_OPTION_ROMS 16
164extern const char *option_rom[MAX_OPTION_ROMS];
165extern int nb_option_roms;
166
0ced6589 167/* XXX: make it dynamic */
970ac5a3 168#define MAX_BIOS_SIZE (4 * 1024 * 1024)
75956cf0 169#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
d5295253 170#define BIOS_SIZE ((512 + 32) * 1024)
6af0bf9c 171#elif defined(TARGET_MIPS)
567daa49 172#define BIOS_SIZE (4 * 1024 * 1024)
0ced6589 173#endif
aaaa7df6 174
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175/* keyboard/mouse support */
176
177#define MOUSE_EVENT_LBUTTON 0x01
178#define MOUSE_EVENT_RBUTTON 0x02
179#define MOUSE_EVENT_MBUTTON 0x04
180
181typedef void QEMUPutKBDEvent(void *opaque, int keycode);
182typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
183
455204eb
TS
184typedef struct QEMUPutMouseEntry {
185 QEMUPutMouseEvent *qemu_put_mouse_event;
186 void *qemu_put_mouse_event_opaque;
187 int qemu_put_mouse_event_absolute;
188 char *qemu_put_mouse_event_name;
189
190 /* used internally by qemu for handling mice */
191 struct QEMUPutMouseEntry *next;
192} QEMUPutMouseEntry;
193
63066f4f 194void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
455204eb
TS
195QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
196 void *opaque, int absolute,
197 const char *name);
198void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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199
200void kbd_put_keycode(int keycode);
201void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
09b26c5e 202int kbd_mouse_is_absolute(void);
63066f4f 203
455204eb
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204void do_info_mice(void);
205void do_mouse_set(int index);
206
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207/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
208 constants) */
209#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
210#define QEMU_KEY_BACKSPACE 0x007f
211#define QEMU_KEY_UP QEMU_KEY_ESC1('A')
212#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
213#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
214#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
215#define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
216#define QEMU_KEY_END QEMU_KEY_ESC1(4)
217#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
218#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
219#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
220
221#define QEMU_KEY_CTRL_UP 0xe400
222#define QEMU_KEY_CTRL_DOWN 0xe401
223#define QEMU_KEY_CTRL_LEFT 0xe402
224#define QEMU_KEY_CTRL_RIGHT 0xe403
225#define QEMU_KEY_CTRL_HOME 0xe404
226#define QEMU_KEY_CTRL_END 0xe405
227#define QEMU_KEY_CTRL_PAGEUP 0xe406
228#define QEMU_KEY_CTRL_PAGEDOWN 0xe407
229
230void kbd_put_keysym(int keysym);
231
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232/* async I/O support */
233
234typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
235typedef int IOCanRWHandler(void *opaque);
7c9d8e07 236typedef void IOHandler(void *opaque);
c20709aa 237
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238int qemu_set_fd_handler2(int fd,
239 IOCanRWHandler *fd_read_poll,
240 IOHandler *fd_read,
241 IOHandler *fd_write,
242 void *opaque);
243int qemu_set_fd_handler(int fd,
244 IOHandler *fd_read,
245 IOHandler *fd_write,
246 void *opaque);
c20709aa 247
f331110f
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248/* Polling handling */
249
250/* return TRUE if no sleep should be done afterwards */
251typedef int PollingFunc(void *opaque);
252
253int qemu_add_polling_cb(PollingFunc *func, void *opaque);
254void qemu_del_polling_cb(PollingFunc *func, void *opaque);
255
a18e524a
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256#ifdef _WIN32
257/* Wait objects handling */
258typedef void WaitObjectFunc(void *opaque);
259
260int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
261void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
262#endif
263
86e94dea
TS
264typedef struct QEMUBH QEMUBH;
265
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266/* character device */
267
268#define CHR_EVENT_BREAK 0 /* serial break char */
ea2384d3 269#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
86e94dea 270#define CHR_EVENT_RESET 2 /* new connection established */
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271
272
273#define CHR_IOCTL_SERIAL_SET_PARAMS 1
274typedef struct {
275 int speed;
276 int parity;
277 int data_bits;
278 int stop_bits;
279} QEMUSerialSetParams;
280
281#define CHR_IOCTL_SERIAL_SET_BREAK 2
282
283#define CHR_IOCTL_PP_READ_DATA 3
284#define CHR_IOCTL_PP_WRITE_DATA 4
285#define CHR_IOCTL_PP_READ_CONTROL 5
286#define CHR_IOCTL_PP_WRITE_CONTROL 6
287#define CHR_IOCTL_PP_READ_STATUS 7
5867c88a
TS
288#define CHR_IOCTL_PP_EPP_READ_ADDR 8
289#define CHR_IOCTL_PP_EPP_READ 9
290#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
291#define CHR_IOCTL_PP_EPP_WRITE 11
2122c51a 292
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293typedef void IOEventHandler(void *opaque, int event);
294
295typedef struct CharDriverState {
296 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
e5b0bc44 297 void (*chr_update_read_handler)(struct CharDriverState *s);
2122c51a 298 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
82c643ff 299 IOEventHandler *chr_event;
e5b0bc44
PB
300 IOCanRWHandler *chr_can_read;
301 IOReadHandler *chr_read;
302 void *handler_opaque;
eb45f5fe 303 void (*chr_send_event)(struct CharDriverState *chr, int event);
f331110f 304 void (*chr_close)(struct CharDriverState *chr);
82c643ff 305 void *opaque;
20d8a3ed 306 int focus;
86e94dea 307 QEMUBH *bh;
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308} CharDriverState;
309
5856de80 310CharDriverState *qemu_chr_open(const char *filename);
82c643ff
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311void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
312int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
ea2384d3 313void qemu_chr_send_event(CharDriverState *s, int event);
e5b0bc44
PB
314void qemu_chr_add_handlers(CharDriverState *s,
315 IOCanRWHandler *fd_can_read,
316 IOReadHandler *fd_read,
317 IOEventHandler *fd_event,
318 void *opaque);
2122c51a 319int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
86e94dea 320void qemu_chr_reset(CharDriverState *s);
e5b0bc44
PB
321int qemu_chr_can_read(CharDriverState *s);
322void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
f8d179e3 323
82c643ff
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324/* consoles */
325
326typedef struct DisplayState DisplayState;
327typedef struct TextConsole TextConsole;
328
95219897
PB
329typedef void (*vga_hw_update_ptr)(void *);
330typedef void (*vga_hw_invalidate_ptr)(void *);
331typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
332
333TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
334 vga_hw_invalidate_ptr invalidate,
335 vga_hw_screen_dump_ptr screen_dump,
336 void *opaque);
337void vga_hw_update(void);
338void vga_hw_invalidate(void);
339void vga_hw_screen_dump(const char *filename);
340
341int is_graphic_console(void);
82c643ff
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342CharDriverState *text_console_init(DisplayState *ds);
343void console_select(unsigned int index);
344
8d11df9e
FB
345/* serial ports */
346
347#define MAX_SERIAL_PORTS 4
348
349extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
350
6508fe59
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351/* parallel ports */
352
353#define MAX_PARALLEL_PORTS 3
354
355extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
356
5867c88a
TS
357struct ParallelIOArg {
358 void *buffer;
359 int count;
360};
361
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FB
362/* VLANs support */
363
364typedef struct VLANClientState VLANClientState;
365
366struct VLANClientState {
367 IOReadHandler *fd_read;
d861b05e
PB
368 /* Packets may still be sent if this returns zero. It's used to
369 rate-limit the slirp code. */
370 IOCanRWHandler *fd_can_read;
7c9d8e07
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371 void *opaque;
372 struct VLANClientState *next;
373 struct VLANState *vlan;
374 char info_str[256];
375};
376
377typedef struct VLANState {
378 int id;
379 VLANClientState *first_client;
380 struct VLANState *next;
381} VLANState;
382
383VLANState *qemu_find_vlan(int id);
384VLANClientState *qemu_new_vlan_client(VLANState *vlan,
d861b05e
PB
385 IOReadHandler *fd_read,
386 IOCanRWHandler *fd_can_read,
387 void *opaque);
388int qemu_can_send_packet(VLANClientState *vc);
7c9d8e07 389void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
d861b05e 390void qemu_handler_true(void *opaque);
7c9d8e07
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391
392void do_info_network(void);
393
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394/* TAP win32 */
395int tap_win32_init(VLANState *vlan, const char *ifname);
7fb843f8 396
7c9d8e07 397/* NIC info */
c4b1fcc0
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398
399#define MAX_NICS 8
400
7c9d8e07 401typedef struct NICInfo {
c4b1fcc0 402 uint8_t macaddr[6];
a41b2ff2 403 const char *model;
7c9d8e07
FB
404 VLANState *vlan;
405} NICInfo;
c4b1fcc0
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406
407extern int nb_nics;
7c9d8e07 408extern NICInfo nd_table[MAX_NICS];
8a7ddc38
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409
410/* timers */
411
412typedef struct QEMUClock QEMUClock;
413typedef struct QEMUTimer QEMUTimer;
414typedef void QEMUTimerCB(void *opaque);
415
416/* The real time clock should be used only for stuff which does not
417 change the virtual machine state, as it is run even if the virtual
69b91039 418 machine is stopped. The real time clock has a frequency of 1000
8a7ddc38
FB
419 Hz. */
420extern QEMUClock *rt_clock;
421
e80cfcfc 422/* The virtual clock is only run during the emulation. It is stopped
8a7ddc38
FB
423 when the virtual machine is stopped. Virtual timers use a high
424 precision clock, usually cpu cycles (use ticks_per_sec). */
425extern QEMUClock *vm_clock;
426
427int64_t qemu_get_clock(QEMUClock *clock);
428
429QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
430void qemu_free_timer(QEMUTimer *ts);
431void qemu_del_timer(QEMUTimer *ts);
432void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
433int qemu_timer_pending(QEMUTimer *ts);
434
435extern int64_t ticks_per_sec;
436extern int pit_min_timer_count;
437
1dce7c3c 438int64_t cpu_get_ticks(void);
8a7ddc38
FB
439void cpu_enable_ticks(void);
440void cpu_disable_ticks(void);
441
442/* VM Load/Save */
443
faea38e7 444typedef struct QEMUFile QEMUFile;
8a7ddc38 445
faea38e7
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446QEMUFile *qemu_fopen(const char *filename, const char *mode);
447void qemu_fflush(QEMUFile *f);
448void qemu_fclose(QEMUFile *f);
8a7ddc38
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449void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
450void qemu_put_byte(QEMUFile *f, int v);
451void qemu_put_be16(QEMUFile *f, unsigned int v);
452void qemu_put_be32(QEMUFile *f, unsigned int v);
453void qemu_put_be64(QEMUFile *f, uint64_t v);
454int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
455int qemu_get_byte(QEMUFile *f);
456unsigned int qemu_get_be16(QEMUFile *f);
457unsigned int qemu_get_be32(QEMUFile *f);
458uint64_t qemu_get_be64(QEMUFile *f);
459
460static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
461{
462 qemu_put_be64(f, *pv);
463}
464
465static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
466{
467 qemu_put_be32(f, *pv);
468}
469
470static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
471{
472 qemu_put_be16(f, *pv);
473}
474
475static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
476{
477 qemu_put_byte(f, *pv);
478}
479
480static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
481{
482 *pv = qemu_get_be64(f);
483}
484
485static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
486{
487 *pv = qemu_get_be32(f);
488}
489
490static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
491{
492 *pv = qemu_get_be16(f);
493}
494
495static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
496{
497 *pv = qemu_get_byte(f);
498}
499
c27004ec
FB
500#if TARGET_LONG_BITS == 64
501#define qemu_put_betl qemu_put_be64
502#define qemu_get_betl qemu_get_be64
503#define qemu_put_betls qemu_put_be64s
504#define qemu_get_betls qemu_get_be64s
505#else
506#define qemu_put_betl qemu_put_be32
507#define qemu_get_betl qemu_get_be32
508#define qemu_put_betls qemu_put_be32s
509#define qemu_get_betls qemu_get_be32s
510#endif
511
8a7ddc38
FB
512int64_t qemu_ftell(QEMUFile *f);
513int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
514
515typedef void SaveStateHandler(QEMUFile *f, void *opaque);
516typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
517
8a7ddc38
FB
518int register_savevm(const char *idstr,
519 int instance_id,
520 int version_id,
521 SaveStateHandler *save_state,
522 LoadStateHandler *load_state,
523 void *opaque);
524void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
525void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
c4b1fcc0 526
6a00d601
FB
527void cpu_save(QEMUFile *f, void *opaque);
528int cpu_load(QEMUFile *f, void *opaque, int version_id);
529
faea38e7
FB
530void do_savevm(const char *name);
531void do_loadvm(const char *name);
532void do_delvm(const char *name);
533void do_info_snapshots(void);
534
83f64091 535/* bottom halves */
83f64091
FB
536typedef void QEMUBHFunc(void *opaque);
537
538QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
539void qemu_bh_schedule(QEMUBH *bh);
540void qemu_bh_cancel(QEMUBH *bh);
541void qemu_bh_delete(QEMUBH *bh);
6eb5733a 542int qemu_bh_poll(void);
83f64091 543
fc01f7e7
FB
544/* block.c */
545typedef struct BlockDriverState BlockDriverState;
ea2384d3
FB
546typedef struct BlockDriver BlockDriver;
547
548extern BlockDriver bdrv_raw;
19cb3738 549extern BlockDriver bdrv_host_device;
ea2384d3
FB
550extern BlockDriver bdrv_cow;
551extern BlockDriver bdrv_qcow;
552extern BlockDriver bdrv_vmdk;
3c56521b 553extern BlockDriver bdrv_cloop;
585d0ed9 554extern BlockDriver bdrv_dmg;
a8753c34 555extern BlockDriver bdrv_bochs;
6a0f9e82 556extern BlockDriver bdrv_vpc;
de167e41 557extern BlockDriver bdrv_vvfat;
faea38e7
FB
558extern BlockDriver bdrv_qcow2;
559
560typedef struct BlockDriverInfo {
561 /* in bytes, 0 if irrelevant */
562 int cluster_size;
563 /* offset at which the VM state can be saved (0 if not possible) */
564 int64_t vm_state_offset;
565} BlockDriverInfo;
566
567typedef struct QEMUSnapshotInfo {
568 char id_str[128]; /* unique snapshot id */
569 /* the following fields are informative. They are not needed for
570 the consistency of the snapshot */
571 char name[256]; /* user choosen name */
572 uint32_t vm_state_size; /* VM state info size */
573 uint32_t date_sec; /* UTC date of the snapshot */
574 uint32_t date_nsec;
575 uint64_t vm_clock_nsec; /* VM clock relative to boot */
576} QEMUSnapshotInfo;
ea2384d3 577
83f64091
FB
578#define BDRV_O_RDONLY 0x0000
579#define BDRV_O_RDWR 0x0002
580#define BDRV_O_ACCESS 0x0003
581#define BDRV_O_CREAT 0x0004 /* create an empty file */
582#define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
583#define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
584 use a disk image format on top of
585 it (default for
586 bdrv_file_open()) */
587
ea2384d3
FB
588void bdrv_init(void);
589BlockDriver *bdrv_find_format(const char *format_name);
590int bdrv_create(BlockDriver *drv,
591 const char *filename, int64_t size_in_sectors,
592 const char *backing_file, int flags);
c4b1fcc0
FB
593BlockDriverState *bdrv_new(const char *device_name);
594void bdrv_delete(BlockDriverState *bs);
83f64091
FB
595int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
596int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
597int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
ea2384d3 598 BlockDriver *drv);
fc01f7e7
FB
599void bdrv_close(BlockDriverState *bs);
600int bdrv_read(BlockDriverState *bs, int64_t sector_num,
601 uint8_t *buf, int nb_sectors);
602int bdrv_write(BlockDriverState *bs, int64_t sector_num,
603 const uint8_t *buf, int nb_sectors);
83f64091
FB
604int bdrv_pread(BlockDriverState *bs, int64_t offset,
605 void *buf, int count);
606int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
607 const void *buf, int count);
608int bdrv_truncate(BlockDriverState *bs, int64_t offset);
609int64_t bdrv_getlength(BlockDriverState *bs);
fc01f7e7 610void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
33e3963e 611int bdrv_commit(BlockDriverState *bs);
77fef8c1 612void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
83f64091
FB
613/* async block I/O */
614typedef struct BlockDriverAIOCB BlockDriverAIOCB;
615typedef void BlockDriverCompletionFunc(void *opaque, int ret);
616
ce1a14dc
PB
617BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
618 uint8_t *buf, int nb_sectors,
619 BlockDriverCompletionFunc *cb, void *opaque);
620BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
621 const uint8_t *buf, int nb_sectors,
622 BlockDriverCompletionFunc *cb, void *opaque);
83f64091 623void bdrv_aio_cancel(BlockDriverAIOCB *acb);
83f64091
FB
624
625void qemu_aio_init(void);
626void qemu_aio_poll(void);
6192bc37 627void qemu_aio_flush(void);
83f64091
FB
628void qemu_aio_wait_start(void);
629void qemu_aio_wait(void);
630void qemu_aio_wait_end(void);
631
7a6cba61
PB
632/* Ensure contents are flushed to disk. */
633void bdrv_flush(BlockDriverState *bs);
33e3963e 634
c4b1fcc0
FB
635#define BDRV_TYPE_HD 0
636#define BDRV_TYPE_CDROM 1
637#define BDRV_TYPE_FLOPPY 2
4dbb0f50
TS
638#define BIOS_ATA_TRANSLATION_AUTO 0
639#define BIOS_ATA_TRANSLATION_NONE 1
640#define BIOS_ATA_TRANSLATION_LBA 2
641#define BIOS_ATA_TRANSLATION_LARGE 3
642#define BIOS_ATA_TRANSLATION_RECHS 4
c4b1fcc0
FB
643
644void bdrv_set_geometry_hint(BlockDriverState *bs,
645 int cyls, int heads, int secs);
646void bdrv_set_type_hint(BlockDriverState *bs, int type);
46d4767d 647void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
c4b1fcc0
FB
648void bdrv_get_geometry_hint(BlockDriverState *bs,
649 int *pcyls, int *pheads, int *psecs);
650int bdrv_get_type_hint(BlockDriverState *bs);
46d4767d 651int bdrv_get_translation_hint(BlockDriverState *bs);
c4b1fcc0
FB
652int bdrv_is_removable(BlockDriverState *bs);
653int bdrv_is_read_only(BlockDriverState *bs);
654int bdrv_is_inserted(BlockDriverState *bs);
19cb3738 655int bdrv_media_changed(BlockDriverState *bs);
c4b1fcc0
FB
656int bdrv_is_locked(BlockDriverState *bs);
657void bdrv_set_locked(BlockDriverState *bs, int locked);
19cb3738 658void bdrv_eject(BlockDriverState *bs, int eject_flag);
c4b1fcc0
FB
659void bdrv_set_change_cb(BlockDriverState *bs,
660 void (*change_cb)(void *opaque), void *opaque);
ea2384d3 661void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
c4b1fcc0
FB
662void bdrv_info(void);
663BlockDriverState *bdrv_find(const char *name);
82c643ff 664void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
ea2384d3
FB
665int bdrv_is_encrypted(BlockDriverState *bs);
666int bdrv_set_key(BlockDriverState *bs, const char *key);
667void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
668 void *opaque);
669const char *bdrv_get_device_name(BlockDriverState *bs);
faea38e7
FB
670int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
671 const uint8_t *buf, int nb_sectors);
672int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
c4b1fcc0 673
83f64091
FB
674void bdrv_get_backing_filename(BlockDriverState *bs,
675 char *filename, int filename_size);
faea38e7
FB
676int bdrv_snapshot_create(BlockDriverState *bs,
677 QEMUSnapshotInfo *sn_info);
678int bdrv_snapshot_goto(BlockDriverState *bs,
679 const char *snapshot_id);
680int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
681int bdrv_snapshot_list(BlockDriverState *bs,
682 QEMUSnapshotInfo **psn_info);
683char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
684
685char *get_human_readable_size(char *buf, int buf_size, int64_t size);
83f64091
FB
686int path_is_absolute(const char *path);
687void path_combine(char *dest, int dest_size,
688 const char *base_path,
689 const char *filename);
ea2384d3
FB
690
691#ifndef QEMU_TOOL
54fa5af5
FB
692
693typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
694 int boot_device,
695 DisplayState *ds, const char **fd_filename, int snapshot,
696 const char *kernel_filename, const char *kernel_cmdline,
697 const char *initrd_filename);
698
699typedef struct QEMUMachine {
700 const char *name;
701 const char *desc;
702 QEMUMachineInitFunc *init;
703 struct QEMUMachine *next;
704} QEMUMachine;
705
706int qemu_register_machine(QEMUMachine *m);
707
708typedef void SetIRQFunc(void *opaque, int irq_num, int level);
3de388f6 709typedef void IRQRequestFunc(void *opaque, int level);
54fa5af5 710
26aa7d72
FB
711/* ISA bus */
712
713extern target_phys_addr_t isa_mem_base;
714
715typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
716typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
717
718int register_ioport_read(int start, int length, int size,
719 IOPortReadFunc *func, void *opaque);
720int register_ioport_write(int start, int length, int size,
721 IOPortWriteFunc *func, void *opaque);
69b91039
FB
722void isa_unassign_ioport(int start, int length);
723
aef445bd
PB
724void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
725
69b91039
FB
726/* PCI bus */
727
69b91039
FB
728extern target_phys_addr_t pci_mem_base;
729
46e50e9d 730typedef struct PCIBus PCIBus;
69b91039
FB
731typedef struct PCIDevice PCIDevice;
732
733typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
734 uint32_t address, uint32_t data, int len);
735typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
736 uint32_t address, int len);
737typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
738 uint32_t addr, uint32_t size, int type);
739
740#define PCI_ADDRESS_SPACE_MEM 0x00
741#define PCI_ADDRESS_SPACE_IO 0x01
742#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
743
744typedef struct PCIIORegion {
5768f5ac 745 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
69b91039
FB
746 uint32_t size;
747 uint8_t type;
748 PCIMapIORegionFunc *map_func;
749} PCIIORegion;
750
8a8696a3
FB
751#define PCI_ROM_SLOT 6
752#define PCI_NUM_REGIONS 7
502a5395
PB
753
754#define PCI_DEVICES_MAX 64
755
756#define PCI_VENDOR_ID 0x00 /* 16 bits */
757#define PCI_DEVICE_ID 0x02 /* 16 bits */
758#define PCI_COMMAND 0x04 /* 16 bits */
759#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
760#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
761#define PCI_CLASS_DEVICE 0x0a /* Device class */
762#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
763#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
764#define PCI_MIN_GNT 0x3e /* 8 bits */
765#define PCI_MAX_LAT 0x3f /* 8 bits */
766
69b91039
FB
767struct PCIDevice {
768 /* PCI config space */
769 uint8_t config[256];
770
771 /* the following fields are read only */
46e50e9d 772 PCIBus *bus;
69b91039
FB
773 int devfn;
774 char name[64];
8a8696a3 775 PCIIORegion io_regions[PCI_NUM_REGIONS];
69b91039
FB
776
777 /* do not access the following fields */
778 PCIConfigReadFunc *config_read;
779 PCIConfigWriteFunc *config_write;
502a5395 780 /* ??? This is a PC-specific hack, and should be removed. */
5768f5ac 781 int irq_index;
d2b59317
PB
782
783 /* Current IRQ levels. Used internally by the generic PCI code. */
784 int irq_state[4];
69b91039
FB
785};
786
46e50e9d
FB
787PCIDevice *pci_register_device(PCIBus *bus, const char *name,
788 int instance_size, int devfn,
69b91039
FB
789 PCIConfigReadFunc *config_read,
790 PCIConfigWriteFunc *config_write);
791
792void pci_register_io_region(PCIDevice *pci_dev, int region_num,
793 uint32_t size, int type,
794 PCIMapIORegionFunc *map_func);
795
5768f5ac
FB
796void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
797
798uint32_t pci_default_read_config(PCIDevice *d,
799 uint32_t address, int len);
800void pci_default_write_config(PCIDevice *d,
801 uint32_t address, uint32_t val, int len);
89b6b508
FB
802void pci_device_save(PCIDevice *s, QEMUFile *f);
803int pci_device_load(PCIDevice *s, QEMUFile *f);
5768f5ac 804
d2b59317
PB
805typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
806typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
807PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
80b3ada7 808 void *pic, int devfn_min, int nirq);
502a5395 809
abcebc7e 810void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
502a5395
PB
811void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
812uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
813int pci_bus_num(PCIBus *s);
80b3ada7 814void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
9995c51f 815
5768f5ac 816void pci_info(void);
80b3ada7
PB
817PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
818 pci_map_irq_fn map_irq, const char *name);
26aa7d72 819
502a5395 820/* prep_pci.c */
46e50e9d 821PCIBus *pci_prep_init(void);
77d4bc34 822
502a5395
PB
823/* grackle_pci.c */
824PCIBus *pci_grackle_init(uint32_t base, void *pic);
825
826/* unin_pci.c */
827PCIBus *pci_pmac_init(void *pic);
828
829/* apb_pci.c */
830PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
831 void *pic);
832
e69954b9 833PCIBus *pci_vpb_init(void *pic, int irq, int realview);
502a5395
PB
834
835/* piix_pci.c */
f00fc47c
FB
836PCIBus *i440fx_init(PCIDevice **pi440fx_state);
837void i440fx_set_smm(PCIDevice *d, int val);
8f1c91d8 838int piix3_init(PCIBus *bus, int devfn);
f00fc47c 839void i440fx_init_memory_mappings(PCIDevice *d);
a41b2ff2 840
5856de80
TS
841int piix4_init(PCIBus *bus, int devfn);
842
28b9b5af
FB
843/* openpic.c */
844typedef struct openpic_t openpic_t;
54fa5af5 845void openpic_set_irq(void *opaque, int n_IRQ, int level);
7668a27f
FB
846openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
847 CPUState **envp);
28b9b5af 848
54fa5af5
FB
849/* heathrow_pic.c */
850typedef struct HeathrowPICS HeathrowPICS;
851void heathrow_pic_set_irq(void *opaque, int num, int level);
852HeathrowPICS *heathrow_pic_init(int *pmem_index);
853
fde7d5bd
TS
854/* gt64xxx.c */
855PCIBus *pci_gt64120_init(void *pic);
856
6a36d84e
FB
857#ifdef HAS_AUDIO
858struct soundhw {
859 const char *name;
860 const char *descr;
861 int enabled;
862 int isa;
863 union {
864 int (*init_isa) (AudioState *s);
865 int (*init_pci) (PCIBus *bus, AudioState *s);
866 } init;
867};
868
869extern struct soundhw soundhw[];
870#endif
871
313aa567
FB
872/* vga.c */
873
74a14f22 874#define VGA_RAM_SIZE (8192 * 1024)
313aa567 875
82c643ff 876struct DisplayState {
313aa567
FB
877 uint8_t *data;
878 int linesize;
879 int depth;
d3079cd2 880 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
82c643ff
FB
881 int width;
882 int height;
24236869
FB
883 void *opaque;
884
313aa567
FB
885 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
886 void (*dpy_resize)(struct DisplayState *s, int w, int h);
887 void (*dpy_refresh)(struct DisplayState *s);
24236869 888 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
82c643ff 889};
313aa567
FB
890
891static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
892{
893 s->dpy_update(s, x, y, w, h);
894}
895
896static inline void dpy_resize(DisplayState *s, int w, int h)
897{
898 s->dpy_resize(s, w, h);
899}
900
89b6b508
FB
901int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
902 unsigned long vga_ram_offset, int vga_ram_size);
903int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
904 unsigned long vga_ram_offset, int vga_ram_size,
905 unsigned long vga_bios_offset, int vga_bios_size);
313aa567 906
d6bfa22f 907/* cirrus_vga.c */
46e50e9d 908void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
d6bfa22f 909 unsigned long vga_ram_offset, int vga_ram_size);
d6bfa22f
FB
910void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
911 unsigned long vga_ram_offset, int vga_ram_size);
912
313aa567 913/* sdl.c */
43523e93 914void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
313aa567 915
da4dbf74
FB
916/* cocoa.m */
917void cocoa_display_init(DisplayState *ds, int full_screen);
918
24236869 919/* vnc.c */
73fc9742 920void vnc_display_init(DisplayState *ds, const char *display);
a9ce8590 921void do_info_vnc(void);
24236869 922
6070dd07
TS
923/* x_keymap.c */
924extern uint8_t _translate_keycode(const int key);
925
5391d806
FB
926/* ide.c */
927#define MAX_DISKS 4
928
faea38e7 929extern BlockDriverState *bs_table[MAX_DISKS + 1];
5391d806 930
69b91039
FB
931void isa_ide_init(int iobase, int iobase2, int irq,
932 BlockDriverState *hd0, BlockDriverState *hd1);
54fa5af5
FB
933void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
934 int secondary_ide_enabled);
502a5395 935void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
28b9b5af 936int pmac_ide_init (BlockDriverState **hd_table,
54fa5af5 937 SetIRQFunc *set_irq, void *irq_opaque, int irq);
5391d806 938
2e5d83bb
PB
939/* cdrom.c */
940int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
941int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
942
1d14ffa9 943/* es1370.c */
c0fe3827 944int es1370_init (PCIBus *bus, AudioState *s);
1d14ffa9 945
fb065187 946/* sb16.c */
c0fe3827 947int SB16_init (AudioState *s);
fb065187
FB
948
949/* adlib.c */
c0fe3827 950int Adlib_init (AudioState *s);
fb065187
FB
951
952/* gus.c */
c0fe3827 953int GUS_init (AudioState *s);
27503323
FB
954
955/* dma.c */
85571bc7 956typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
27503323 957int DMA_get_channel_mode (int nchan);
85571bc7
FB
958int DMA_read_memory (int nchan, void *buf, int pos, int size);
959int DMA_write_memory (int nchan, void *buf, int pos, int size);
27503323
FB
960void DMA_hold_DREQ (int nchan);
961void DMA_release_DREQ (int nchan);
16f62432 962void DMA_schedule(int nchan);
27503323 963void DMA_run (void);
28b9b5af 964void DMA_init (int high_page_enable);
27503323 965void DMA_register_channel (int nchan,
85571bc7
FB
966 DMA_transfer_handler transfer_handler,
967 void *opaque);
7138fcfb
FB
968/* fdc.c */
969#define MAX_FD 2
970extern BlockDriverState *fd_table[MAX_FD];
971
baca51fa
FB
972typedef struct fdctrl_t fdctrl_t;
973
974fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
975 uint32_t io_base,
976 BlockDriverState **fds);
977int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
7138fcfb 978
80cabfad
FB
979/* ne2000.c */
980
7c9d8e07 981void isa_ne2000_init(int base, int irq, NICInfo *nd);
abcebc7e 982void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
80cabfad 983
a41b2ff2
PB
984/* rtl8139.c */
985
abcebc7e 986void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
a41b2ff2 987
e3c2613f
FB
988/* pcnet.c */
989
abcebc7e 990void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
67e999be
FB
991void pcnet_h_reset(void *opaque);
992void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
993
e3c2613f 994
80cabfad
FB
995/* pckbd.c */
996
80cabfad
FB
997void kbd_init(void);
998
999/* mc146818rtc.c */
1000
8a7ddc38 1001typedef struct RTCState RTCState;
80cabfad 1002
8a7ddc38
FB
1003RTCState *rtc_init(int base, int irq);
1004void rtc_set_memory(RTCState *s, int addr, int val);
1005void rtc_set_date(RTCState *s, const struct tm *tm);
80cabfad
FB
1006
1007/* serial.c */
1008
c4b1fcc0 1009typedef struct SerialState SerialState;
e5d13e2f
FB
1010SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1011 int base, int irq, CharDriverState *chr);
1012SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1013 target_ulong base, int it_shift,
1014 int irq, CharDriverState *chr);
80cabfad 1015
6508fe59
FB
1016/* parallel.c */
1017
1018typedef struct ParallelState ParallelState;
1019ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1020
80cabfad
FB
1021/* i8259.c */
1022
3de388f6
FB
1023typedef struct PicState2 PicState2;
1024extern PicState2 *isa_pic;
80cabfad 1025void pic_set_irq(int irq, int level);
54fa5af5 1026void pic_set_irq_new(void *opaque, int irq, int level);
3de388f6 1027PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
d592d303
FB
1028void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1029 void *alt_irq_opaque);
3de388f6
FB
1030int pic_read_irq(PicState2 *s);
1031void pic_update_irq(PicState2 *s);
1032uint32_t pic_intack_read(PicState2 *s);
c20709aa 1033void pic_info(void);
4a0fb71e 1034void irq_info(void);
80cabfad 1035
c27004ec 1036/* APIC */
d592d303
FB
1037typedef struct IOAPICState IOAPICState;
1038
c27004ec
FB
1039int apic_init(CPUState *env);
1040int apic_get_interrupt(CPUState *env);
d592d303
FB
1041IOAPICState *ioapic_init(void);
1042void ioapic_set_irq(void *opaque, int vector, int level);
c27004ec 1043
80cabfad
FB
1044/* i8254.c */
1045
1046#define PIT_FREQ 1193182
1047
ec844b96
FB
1048typedef struct PITState PITState;
1049
1050PITState *pit_init(int base, int irq);
1051void pit_set_gate(PITState *pit, int channel, int val);
1052int pit_get_gate(PITState *pit, int channel);
fd06c375
FB
1053int pit_get_initial_count(PITState *pit, int channel);
1054int pit_get_mode(PITState *pit, int channel);
ec844b96 1055int pit_get_out(PITState *pit, int channel, int64_t current_time);
80cabfad 1056
fd06c375
FB
1057/* pcspk.c */
1058void pcspk_init(PITState *);
1059int pcspk_audio_init(AudioState *);
1060
3fffc223
TS
1061#include "hw/smbus.h"
1062
6515b203
FB
1063/* acpi.c */
1064extern int acpi_enabled;
502a5395 1065void piix4_pm_init(PCIBus *bus, int devfn);
3fffc223 1066void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
6515b203
FB
1067void acpi_bios_init(void);
1068
3fffc223
TS
1069/* smbus_eeprom.c */
1070SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1071
80cabfad 1072/* pc.c */
54fa5af5 1073extern QEMUMachine pc_machine;
3dbbdc25 1074extern QEMUMachine isapc_machine;
52ca8d6a 1075extern int fd_bootchk;
80cabfad 1076
6a00d601
FB
1077void ioport_set_a20(int enable);
1078int ioport_get_a20(void);
1079
26aa7d72 1080/* ppc.c */
54fa5af5
FB
1081extern QEMUMachine prep_machine;
1082extern QEMUMachine core99_machine;
1083extern QEMUMachine heathrow_machine;
1084
6af0bf9c
FB
1085/* mips_r4k.c */
1086extern QEMUMachine mips_machine;
1087
5856de80
TS
1088/* mips_malta.c */
1089extern QEMUMachine mips_malta_machine;
1090
4de9b249
TS
1091/* mips_int */
1092extern void cpu_mips_irq_request(void *opaque, int irq, int level);
1093
e16fe40c
TS
1094/* mips_timer.c */
1095extern void cpu_mips_clock_init(CPUState *);
1096extern void cpu_mips_irqctrl_init (void);
1097
27c7ca7e
FB
1098/* shix.c */
1099extern QEMUMachine shix_machine;
1100
8cc43fef
FB
1101#ifdef TARGET_PPC
1102ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1103#endif
64201201 1104void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
77d4bc34
FB
1105
1106extern CPUWriteMemoryFunc *PPC_io_write[];
1107extern CPUReadMemoryFunc *PPC_io_read[];
54fa5af5 1108void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
26aa7d72 1109
e95c8d51 1110/* sun4m.c */
54fa5af5 1111extern QEMUMachine sun4m_machine;
ba3c64fb 1112void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
e95c8d51
FB
1113
1114/* iommu.c */
e80cfcfc 1115void *iommu_init(uint32_t addr);
67e999be 1116void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
a917d384 1117 uint8_t *buf, int len, int is_write);
67e999be
FB
1118static inline void sparc_iommu_memory_read(void *opaque,
1119 target_phys_addr_t addr,
1120 uint8_t *buf, int len)
1121{
1122 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1123}
e95c8d51 1124
67e999be
FB
1125static inline void sparc_iommu_memory_write(void *opaque,
1126 target_phys_addr_t addr,
1127 uint8_t *buf, int len)
1128{
1129 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1130}
e95c8d51
FB
1131
1132/* tcx.c */
95219897 1133void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
6f7e9aec 1134 unsigned long vram_offset, int vram_size, int width, int height);
e80cfcfc
FB
1135
1136/* slavio_intctl.c */
1137void *slavio_intctl_init();
ba3c64fb 1138void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
e80cfcfc
FB
1139void slavio_pic_info(void *opaque);
1140void slavio_irq_info(void *opaque);
1141void slavio_pic_set_irq(void *opaque, int irq, int level);
ba3c64fb 1142void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
e95c8d51 1143
5fe141fd
FB
1144/* loader.c */
1145int get_image_size(const char *filename);
1146int load_image(const char *filename, uint8_t *addr);
9ee3c029 1147int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
e80cfcfc
FB
1148int load_aout(const char *filename, uint8_t *addr);
1149
1150/* slavio_timer.c */
ba3c64fb 1151void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
8d5f07fa 1152
e80cfcfc
FB
1153/* slavio_serial.c */
1154SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1155void slavio_serial_ms_kbd_init(int base, int irq);
e95c8d51 1156
3475187d
FB
1157/* slavio_misc.c */
1158void *slavio_misc_init(uint32_t base, int irq);
1159void slavio_set_power_fail(void *opaque, int power_failing);
1160
6f7e9aec 1161/* esp.c */
fa1fb14c 1162void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
67e999be
FB
1163void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1164void esp_reset(void *opaque);
1165
1166/* sparc32_dma.c */
1167void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1168 void *intctl);
1169void ledma_set_irq(void *opaque, int isr);
9b94dc32
FB
1170void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1171 uint8_t *buf, int len, int do_bswap);
1172void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1173 uint8_t *buf, int len, int do_bswap);
67e999be
FB
1174void espdma_raise_irq(void *opaque);
1175void espdma_clear_irq(void *opaque);
1176void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1177void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1178void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1179 void *lance_opaque);
6f7e9aec 1180
b8174937
FB
1181/* cs4231.c */
1182void cs_init(target_phys_addr_t base, int irq, void *intctl);
1183
3475187d
FB
1184/* sun4u.c */
1185extern QEMUMachine sun4u_machine;
1186
64201201
FB
1187/* NVRAM helpers */
1188#include "hw/m48t59.h"
1189
1190void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1191uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1192void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1193uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1194void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1195uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1196void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1197 const unsigned char *str, uint32_t max);
1198int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1199void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1200 uint32_t start, uint32_t count);
1201int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1202 const unsigned char *arch,
1203 uint32_t RAM_size, int boot_device,
1204 uint32_t kernel_image, uint32_t kernel_size,
28b9b5af 1205 const char *cmdline,
64201201 1206 uint32_t initrd_image, uint32_t initrd_size,
28b9b5af
FB
1207 uint32_t NVRAM_image,
1208 int width, int height, int depth);
64201201 1209
63066f4f
FB
1210/* adb.c */
1211
1212#define MAX_ADB_DEVICES 16
1213
e2733d20 1214#define ADB_MAX_OUT_LEN 16
63066f4f 1215
e2733d20 1216typedef struct ADBDevice ADBDevice;
63066f4f 1217
e2733d20
FB
1218/* buf = NULL means polling */
1219typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1220 const uint8_t *buf, int len);
12c28fed
FB
1221typedef int ADBDeviceReset(ADBDevice *d);
1222
63066f4f
FB
1223struct ADBDevice {
1224 struct ADBBusState *bus;
1225 int devaddr;
1226 int handler;
e2733d20 1227 ADBDeviceRequest *devreq;
12c28fed 1228 ADBDeviceReset *devreset;
63066f4f
FB
1229 void *opaque;
1230};
1231
1232typedef struct ADBBusState {
1233 ADBDevice devices[MAX_ADB_DEVICES];
1234 int nb_devices;
e2733d20 1235 int poll_index;
63066f4f
FB
1236} ADBBusState;
1237
e2733d20
FB
1238int adb_request(ADBBusState *s, uint8_t *buf_out,
1239 const uint8_t *buf, int len);
1240int adb_poll(ADBBusState *s, uint8_t *buf_out);
63066f4f
FB
1241
1242ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
e2733d20 1243 ADBDeviceRequest *devreq,
12c28fed 1244 ADBDeviceReset *devreset,
63066f4f
FB
1245 void *opaque);
1246void adb_kbd_init(ADBBusState *bus);
1247void adb_mouse_init(ADBBusState *bus);
1248
1249/* cuda.c */
1250
1251extern ADBBusState adb_bus;
54fa5af5 1252int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
63066f4f 1253
bb36d470
FB
1254#include "hw/usb.h"
1255
a594cfbf
FB
1256/* usb ports of the VM */
1257
0d92ed30
PB
1258void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1259 usb_attachfn attach);
a594cfbf 1260
0d92ed30 1261#define VM_USB_HUB_SIZE 8
a594cfbf
FB
1262
1263void do_usb_add(const char *devname);
1264void do_usb_del(const char *devname);
1265void usb_info(void);
1266
2e5d83bb 1267/* scsi-disk.c */
4d611c9a
PB
1268enum scsi_reason {
1269 SCSI_REASON_DONE, /* Command complete. */
1270 SCSI_REASON_DATA /* Transfer complete, more data required. */
1271};
1272
2e5d83bb 1273typedef struct SCSIDevice SCSIDevice;
a917d384
PB
1274typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1275 uint32_t arg);
2e5d83bb
PB
1276
1277SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
a917d384 1278 int tcq,
2e5d83bb
PB
1279 scsi_completionfn completion,
1280 void *opaque);
1281void scsi_disk_destroy(SCSIDevice *s);
1282
0fc5c15a 1283int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
4d611c9a
PB
1284/* SCSI data transfers are asynchrnonous. However, unlike the block IO
1285 layer the completion routine may be called directly by
1286 scsi_{read,write}_data. */
a917d384
PB
1287void scsi_read_data(SCSIDevice *s, uint32_t tag);
1288int scsi_write_data(SCSIDevice *s, uint32_t tag);
1289void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1290uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
2e5d83bb 1291
7d8406be
PB
1292/* lsi53c895a.c */
1293void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1294void *lsi_scsi_init(PCIBus *bus, int devfn);
1295
b5ff1b31 1296/* integratorcp.c */
40f137e1
PB
1297extern QEMUMachine integratorcp926_machine;
1298extern QEMUMachine integratorcp1026_machine;
b5ff1b31 1299
cdbdb648
PB
1300/* versatilepb.c */
1301extern QEMUMachine versatilepb_machine;
16406950 1302extern QEMUMachine versatileab_machine;
cdbdb648 1303
e69954b9
PB
1304/* realview.c */
1305extern QEMUMachine realview_machine;
1306
daa57963
FB
1307/* ps2.c */
1308void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1309void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1310void ps2_write_mouse(void *, int val);
1311void ps2_write_keyboard(void *, int val);
1312uint32_t ps2_read_data(void *);
1313void ps2_queue(void *, int b);
f94f5d71 1314void ps2_keyboard_set_translation(void *opaque, int mode);
daa57963 1315
80337b66
FB
1316/* smc91c111.c */
1317void smc91c111_init(NICInfo *, uint32_t, void *, int);
1318
bdd5003a 1319/* pl110.c */
95219897 1320void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
bdd5003a 1321
cdbdb648
PB
1322/* pl011.c */
1323void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1324
1325/* pl050.c */
1326void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1327
1328/* pl080.c */
e69954b9 1329void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
cdbdb648
PB
1330
1331/* pl190.c */
1332void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1333
1334/* arm-timer.c */
1335void sp804_init(uint32_t base, void *pic, int irq);
1336void icp_pit_init(uint32_t base, void *pic, int irq);
1337
e69954b9
PB
1338/* arm_sysctl.c */
1339void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1340
1341/* arm_gic.c */
1342void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1343
16406950
PB
1344/* arm_boot.c */
1345
daf90626 1346void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
16406950
PB
1347 const char *kernel_cmdline, const char *initrd_filename,
1348 int board_id);
1349
27c7ca7e
FB
1350/* sh7750.c */
1351struct SH7750State;
1352
008a8818 1353struct SH7750State *sh7750_init(CPUState * cpu);
27c7ca7e
FB
1354
1355typedef struct {
1356 /* The callback will be triggered if any of the designated lines change */
1357 uint16_t portamask_trigger;
1358 uint16_t portbmask_trigger;
1359 /* Return 0 if no action was taken */
1360 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1361 uint16_t * periph_pdtra,
1362 uint16_t * periph_portdira,
1363 uint16_t * periph_pdtrb,
1364 uint16_t * periph_portdirb);
1365} sh7750_io_device;
1366
1367int sh7750_register_io_device(struct SH7750State *s,
1368 sh7750_io_device * device);
1369/* tc58128.c */
1370int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1371
29133e9a
FB
1372/* NOR flash devices */
1373typedef struct pflash_t pflash_t;
1374
1375pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1376 BlockDriverState *bs,
1377 target_ulong sector_len, int nb_blocs, int width,
1378 uint16_t id0, uint16_t id1,
1379 uint16_t id2, uint16_t id3);
1380
4046d913
PB
1381#include "gdbstub.h"
1382
ea2384d3
FB
1383#endif /* defined(QEMU_TOOL) */
1384
c4b1fcc0 1385/* monitor.c */
82c643ff 1386void monitor_init(CharDriverState *hd, int show_banner);
ea2384d3
FB
1387void term_puts(const char *str);
1388void term_vprintf(const char *fmt, va_list ap);
40c3bac3 1389void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
fef30743 1390void term_print_filename(const char *filename);
c4b1fcc0
FB
1391void term_flush(void);
1392void term_print_help(void);
ea2384d3
FB
1393void monitor_readline(const char *prompt, int is_password,
1394 char *buf, int buf_size);
1395
1396/* readline.c */
1397typedef void ReadLineFunc(void *opaque, const char *str);
1398
1399extern int completion_index;
1400void add_completion(const char *str);
1401void readline_handle_byte(int ch);
1402void readline_find_completion(const char *cmdline);
1403const char *readline_get_history(unsigned int index);
1404void readline_start(const char *prompt, int is_password,
1405 ReadLineFunc *readline_func, void *opaque);
c4b1fcc0 1406
5e6ad6f9
FB
1407void kqemu_record_dump(void);
1408
fc01f7e7 1409#endif /* VL_H */