[mirror_ubuntu-hirsute-kernel.git] / Documentation / devicetree / bindings / arm / cpus.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM CPUs bindings

maintainers:
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

description: |+
  The device tree allows to describe the layout of CPUs in a system through
  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  defining properties for every cpu.

  Bindings for CPU nodes follow the Devicetree Specification, available from:

  https://www.devicetree.org/specifications/

  with updates for 32-bit and 64-bit ARM systems provided in this document.

  ================================
  Convention used in this document
  ================================

  This document follows the conventions described in the Devicetree
  Specification, with the addition:

  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
    the reg property contained in bits 7 down to 0

  =====================================
  cpus and cpu node bindings definition
  =====================================

  The ARM architecture, in accordance with the Devicetree Specification,
  requires the cpus and cpu nodes to be present and contain the properties
  described below.

properties:
  reg:
    maxItems: 1
    description: |
      Usage and definition depend on ARM architecture version and
      configuration:

      On uniprocessor ARM architectures previous to v7
      this property is required and must be set to 0.

      On ARM 11 MPcore based systems this property is
        required and matches the CPUID[11:0] register bits.

        Bits [11:0] in the reg cell must be set to
        bits [11:0] in CPU ID register.

        All other bits in the reg cell must be set to 0.

      On 32-bit ARM v7 or later systems this property is
        required and matches the CPU MPIDR[23:0] register
        bits.

        Bits [23:0] in the reg cell must be set to
        bits [23:0] in MPIDR.

        All other bits in the reg cell must be set to 0.

      On ARM v8 64-bit systems this property is required
        and matches the MPIDR_EL1 register affinity bits.

        * If cpus node's #address-cells property is set to 2

          The first reg cell bits [7:0] must be set to
          bits [39:32] of MPIDR_EL1.

          The second reg cell bits [23:0] must be set to
          bits [23:0] of MPIDR_EL1.

        * If cpus node's #address-cells property is set to 1

          The reg cell bits [23:0] must be set to bits [23:0]
          of MPIDR_EL1.

      All other bits in the reg cells must be set to 0.

  compatible:
    enum:
      - arm,arm710t
      - arm,arm720t
      - arm,arm740t
      - arm,arm7ej-s
      - arm,arm7tdmi
      - arm,arm7tdmi-s
      - arm,arm9es
      - arm,arm9ej-s
      - arm,arm920t
      - arm,arm922t
      - arm,arm925
      - arm,arm926e-s
      - arm,arm926ej-s
      - arm,arm940t
      - arm,arm946e-s
      - arm,arm966e-s
      - arm,arm968e-s
      - arm,arm9tdmi
      - arm,arm1020e
      - arm,arm1020t
      - arm,arm1022e
      - arm,arm1026ej-s
      - arm,arm1136j-s
      - arm,arm1136jf-s
      - arm,arm1156t2-s
      - arm,arm1156t2f-s
      - arm,arm1176jzf
      - arm,arm1176jz-s
      - arm,arm1176jzf-s
      - arm,arm11mpcore
      - arm,armv8 # Only for s/w models
      - arm,cortex-a5
      - arm,cortex-a7
      - arm,cortex-a8
      - arm,cortex-a9
      - arm,cortex-a12
      - arm,cortex-a15
      - arm,cortex-a17
      - arm,cortex-a32
      - arm,cortex-a34
      - arm,cortex-a35
      - arm,cortex-a53
      - arm,cortex-a55
      - arm,cortex-a57
      - arm,cortex-a65
      - arm,cortex-a72
      - arm,cortex-a73
      - arm,cortex-a75
      - arm,cortex-a76
      - arm,cortex-a77
      - arm,cortex-m0
      - arm,cortex-m0+
      - arm,cortex-m1
      - arm,cortex-m3
      - arm,cortex-m4
      - arm,cortex-r4
      - arm,cortex-r5
      - arm,cortex-r7
      - arm,neoverse-e1
      - arm,neoverse-n1
      - brcm,brahma-b15
      - brcm,brahma-b53
      - brcm,vulcan
      - cavium,thunder
      - cavium,thunder2
      - faraday,fa526
      - intel,sa110
      - intel,sa1100
      - marvell,feroceon
      - marvell,mohawk
      - marvell,pj4a
      - marvell,pj4b
      - marvell,sheeva-v5
      - marvell,sheeva-v7
      - nvidia,tegra132-denver
      - nvidia,tegra186-denver
      - nvidia,tegra194-carmel
      - qcom,krait
      - qcom,kryo
      - qcom,kryo260
      - qcom,kryo280
      - qcom,kryo385
      - qcom,kryo468
      - qcom,kryo485
      - qcom,scorpion

  enable-method:
    $ref: '/schemas/types.yaml#/definitions/string'
    oneOf:
      # On ARM v8 64-bit this property is required
      - enum:
          - psci
          - spin-table
      # On ARM 32-bit systems this property is optional
      - enum:
          - actions,s500-smp
          - allwinner,sun6i-a31
          - allwinner,sun8i-a23
          - allwinner,sun9i-a80-smp
          - allwinner,sun8i-a83t-smp
          - amlogic,meson8-smp
          - amlogic,meson8b-smp
          - arm,realview-smp
          - aspeed,ast2600-smp
          - brcm,bcm11351-cpu-method
          - brcm,bcm23550
          - brcm,bcm2836-smp
          - brcm,bcm63138
          - brcm,bcm-nsp-smp
          - brcm,brahma-b15
          - marvell,armada-375-smp
          - marvell,armada-380-smp
          - marvell,armada-390-smp
          - marvell,armada-xp-smp
          - marvell,98dx3236-smp
          - marvell,mmp3-smp
          - mediatek,mt6589-smp
          - mediatek,mt81xx-tz-smp
          - qcom,gcc-msm8660
          - qcom,kpss-acc-v1
          - qcom,kpss-acc-v2
          - renesas,apmu
          - renesas,r9a06g032-smp
          - rockchip,rk3036-smp
          - rockchip,rk3066-smp
          - socionext,milbeaut-m10v-smp
          - ste,dbx500-smp
          - ti,am3352
          - ti,am4372

  cpu-release-addr:
    $ref: '/schemas/types.yaml#/definitions/uint64'

    description:
      Required for systems that have an "enable-method"
        property value of "spin-table".
      On ARM v8 64-bit systems must be a two cell
        property identifying a 64-bit zero-initialised
        memory location.

  cpu-idle-states:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    description: |
      List of phandles to idle state nodes supported
      by this cpu (see ./idle-states.yaml).

  capacity-dmips-mhz:
    description:
      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
      DMIPS/MHz, relative to highest capacity-dmips-mhz
      in the system.

  dynamic-power-coefficient:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      A u32 value that represents the running time dynamic
      power coefficient in units of uW/MHz/V^2. The
      coefficient can either be calculated from power
      measurements or derived by analysis.

      The dynamic power consumption of the CPU  is
      proportional to the square of the Voltage (V) and
      the clock frequency (f). The coefficient is used to
      calculate the dynamic power as below -

      Pdyn = dynamic-power-coefficient * V^2 * f

      where voltage is in V, frequency is in MHz.

  power-domains:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    description:
      List of phandles and PM domain specifiers, as defined by bindings of the
      PM domain provider (see also ../power_domain.txt).

  power-domain-names:
    $ref: '/schemas/types.yaml#/definitions/string-array'
    description:
      A list of power domain name strings sorted in the same order as the
      power-domains property.

      For PSCI based platforms, the name corresponding to the index of the PSCI
      PM domain provider, must be "psci".

  qcom,saw:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the SAW* node associated with this CPU.

      Required for systems that have an "enable-method" property
      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"

      * arm/msm/qcom,saw2.txt

  qcom,acc:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the ACC* node associated with this CPU.

      Required for systems that have an "enable-method" property
      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"

      * arm/msm/qcom,kpss-acc.txt

  rockchip,pmu:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the syscon node controlling the cpu core power domains.

      Optional for systems that have an "enable-method"
      property value of "rockchip,rk3066-smp"
      While optional, it is the preferred way to get access to
      the cpu-core power-domains.

  secondary-boot-reg:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: |
      Required for systems that have an "enable-method" property value of
      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".

      This includes the following SoCs: |
      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312

      The secondary-boot-reg property is a u32 value that specifies the
      physical address of the register used to request the ROM holding pen
      code release a secondary CPU. The value written to the register is
      formed by encoding the target CPU id into the low bits of the
      physical start address it should jump to.

if:
  # If the enable-method property contains one of those values
  properties:
    enable-method:
      contains:
        enum:
          - brcm,bcm11351-cpu-method
          - brcm,bcm23550
          - brcm,bcm-nsp-smp
  # and if enable-method is present
  required:
    - enable-method

then:
  required:
    - secondary-boot-reg

required:
  - device_type
  - reg
  - compatible

dependencies:
  rockchip,pmu: [enable-method]

additionalProperties: true

examples:
  - |
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a15";
        reg = <0x0>;
      };

      cpu@1 {
        device_type = "cpu";
        compatible = "arm,cortex-a15";
        reg = <0x1>;
      };

      cpu@100 {
        device_type = "cpu";
        compatible = "arm,cortex-a7";
        reg = <0x100>;
      };

      cpu@101 {
        device_type = "cpu";
        compatible = "arm,cortex-a7";
        reg = <0x101>;
      };
    };

  - |
    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a8";
        reg = <0x0>;
      };
    };

  - |
    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,arm926ej-s";
        reg = <0x0>;
      };
    };

  - |
    //  Example 4 (ARM Cortex-A57 64-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <2>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x0>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@1 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x1>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10000>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10001>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x0>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x1>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10000>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10001>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };
    };
...
Commit	Line	Data
	1	# SPDX-License-Identifier: GPL-2.0
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/arm/cpus.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: ARM CPUs bindings
	8
	9	maintainers:
	10	- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
	11
	12	description: \|+
	13	The device tree allows to describe the layout of CPUs in a system through
	14	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
	15	defining properties for every cpu.
	16
	17	Bindings for CPU nodes follow the Devicetree Specification, available from:
	18
	19	https://www.devicetree.org/specifications/
	20
	21	with updates for 32-bit and 64-bit ARM systems provided in this document.
	22
	23	================================
	24	Convention used in this document
	25	================================
	26
	27	This document follows the conventions described in the Devicetree
	28	Specification, with the addition:
	29
	30	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
	31	the reg property contained in bits 7 down to 0
	32
	33	=====================================
	34	cpus and cpu node bindings definition
	35	=====================================
	36
	37	The ARM architecture, in accordance with the Devicetree Specification,
	38	requires the cpus and cpu nodes to be present and contain the properties
	39	described below.
	40
	41	properties:
	42	reg:
	43	maxItems: 1
	44	description: \|
	45	Usage and definition depend on ARM architecture version and
	46	configuration:
	47
	48	On uniprocessor ARM architectures previous to v7
	49	this property is required and must be set to 0.
	50
	51	On ARM 11 MPcore based systems this property is
	52	required and matches the CPUID[11:0] register bits.
	53
	54	Bits [11:0] in the reg cell must be set to
	55	bits [11:0] in CPU ID register.
	56
	57	All other bits in the reg cell must be set to 0.
	58
	59	On 32-bit ARM v7 or later systems this property is
	60	required and matches the CPU MPIDR[23:0] register
	61	bits.
	62
	63	Bits [23:0] in the reg cell must be set to
	64	bits [23:0] in MPIDR.
	65
	66	All other bits in the reg cell must be set to 0.
	67
	68	On ARM v8 64-bit systems this property is required
	69	and matches the MPIDR_EL1 register affinity bits.
	70
	71	* If cpus node's #address-cells property is set to 2
	72
	73	The first reg cell bits [7:0] must be set to
	74	bits [39:32] of MPIDR_EL1.
	75
	76	The second reg cell bits [23:0] must be set to
	77	bits [23:0] of MPIDR_EL1.
	78
	79	* If cpus node's #address-cells property is set to 1
	80
	81	The reg cell bits [23:0] must be set to bits [23:0]
	82	of MPIDR_EL1.
	83
	84	All other bits in the reg cells must be set to 0.
	85
	86	compatible:
	87	enum:
	88	- arm,arm710t
	89	- arm,arm720t
	90	- arm,arm740t
	91	- arm,arm7ej-s
	92	- arm,arm7tdmi
	93	- arm,arm7tdmi-s
	94	- arm,arm9es
	95	- arm,arm9ej-s
	96	- arm,arm920t
	97	- arm,arm922t
	98	- arm,arm925
	99	- arm,arm926e-s
	100	- arm,arm926ej-s
	101	- arm,arm940t
	102	- arm,arm946e-s
	103	- arm,arm966e-s
	104	- arm,arm968e-s
	105	- arm,arm9tdmi
	106	- arm,arm1020e
	107	- arm,arm1020t
	108	- arm,arm1022e
	109	- arm,arm1026ej-s
	110	- arm,arm1136j-s
	111	- arm,arm1136jf-s
	112	- arm,arm1156t2-s
	113	- arm,arm1156t2f-s
	114	- arm,arm1176jzf
	115	- arm,arm1176jz-s
	116	- arm,arm1176jzf-s
	117	- arm,arm11mpcore
	118	- arm,armv8 # Only for s/w models
	119	- arm,cortex-a5
	120	- arm,cortex-a7
	121	- arm,cortex-a8
	122	- arm,cortex-a9
	123	- arm,cortex-a12
	124	- arm,cortex-a15
	125	- arm,cortex-a17
	126	- arm,cortex-a32
	127	- arm,cortex-a34
	128	- arm,cortex-a35
	129	- arm,cortex-a53
	130	- arm,cortex-a55
	131	- arm,cortex-a57
	132	- arm,cortex-a65
	133	- arm,cortex-a72
	134	- arm,cortex-a73
	135	- arm,cortex-a75
	136	- arm,cortex-a76
	137	- arm,cortex-a77
	138	- arm,cortex-m0
	139	- arm,cortex-m0+
	140	- arm,cortex-m1
	141	- arm,cortex-m3
	142	- arm,cortex-m4
	143	- arm,cortex-r4
	144	- arm,cortex-r5
	145	- arm,cortex-r7
	146	- arm,neoverse-e1
	147	- arm,neoverse-n1
	148	- brcm,brahma-b15
	149	- brcm,brahma-b53
	150	- brcm,vulcan
	151	- cavium,thunder
	152	- cavium,thunder2
	153	- faraday,fa526
	154	- intel,sa110
	155	- intel,sa1100
	156	- marvell,feroceon
	157	- marvell,mohawk
	158	- marvell,pj4a
	159	- marvell,pj4b
	160	- marvell,sheeva-v5
	161	- marvell,sheeva-v7
	162	- nvidia,tegra132-denver
	163	- nvidia,tegra186-denver
	164	- nvidia,tegra194-carmel
	165	- qcom,krait
	166	- qcom,kryo
	167	- qcom,kryo260
	168	- qcom,kryo280
	169	- qcom,kryo385
	170	- qcom,kryo468
	171	- qcom,kryo485
	172	- qcom,scorpion
	173
	174	enable-method:
	175	$ref: '/schemas/types.yaml#/definitions/string'
	176	oneOf:
	177	# On ARM v8 64-bit this property is required
	178	- enum:
	179	- psci
	180	- spin-table
	181	# On ARM 32-bit systems this property is optional
	182	- enum:
	183	- actions,s500-smp
	184	- allwinner,sun6i-a31
	185	- allwinner,sun8i-a23
	186	- allwinner,sun9i-a80-smp
	187	- allwinner,sun8i-a83t-smp
	188	- amlogic,meson8-smp
	189	- amlogic,meson8b-smp
	190	- arm,realview-smp
	191	- aspeed,ast2600-smp
	192	- brcm,bcm11351-cpu-method
	193	- brcm,bcm23550
	194	- brcm,bcm2836-smp
	195	- brcm,bcm63138
	196	- brcm,bcm-nsp-smp
	197	- brcm,brahma-b15
	198	- marvell,armada-375-smp
	199	- marvell,armada-380-smp
	200	- marvell,armada-390-smp
	201	- marvell,armada-xp-smp
	202	- marvell,98dx3236-smp
	203	- marvell,mmp3-smp
	204	- mediatek,mt6589-smp
	205	- mediatek,mt81xx-tz-smp
	206	- qcom,gcc-msm8660
	207	- qcom,kpss-acc-v1
	208	- qcom,kpss-acc-v2
	209	- renesas,apmu
	210	- renesas,r9a06g032-smp
	211	- rockchip,rk3036-smp
	212	- rockchip,rk3066-smp
	213	- socionext,milbeaut-m10v-smp
	214	- ste,dbx500-smp
	215	- ti,am3352
	216	- ti,am4372
	217
	218	cpu-release-addr:
	219	$ref: '/schemas/types.yaml#/definitions/uint64'
	220
	221	description:
	222	Required for systems that have an "enable-method"
	223	property value of "spin-table".
	224	On ARM v8 64-bit systems must be a two cell
	225	property identifying a 64-bit zero-initialised
	226	memory location.
	227
	228	cpu-idle-states:
	229	$ref: '/schemas/types.yaml#/definitions/phandle-array'
	230	description: \|
	231	List of phandles to idle state nodes supported
	232	by this cpu (see ./idle-states.yaml).
	233
	234	capacity-dmips-mhz:
	235	description:
	236	u32 value representing CPU capacity (see ./cpu-capacity.txt) in
	237	DMIPS/MHz, relative to highest capacity-dmips-mhz
	238	in the system.
	239
	240	dynamic-power-coefficient:
	241	$ref: '/schemas/types.yaml#/definitions/uint32'
	242	description:
	243	A u32 value that represents the running time dynamic
	244	power coefficient in units of uW/MHz/V^2. The
	245	coefficient can either be calculated from power
	246	measurements or derived by analysis.
	247
	248	The dynamic power consumption of the CPU is
	249	proportional to the square of the Voltage (V) and
	250	the clock frequency (f). The coefficient is used to
	251	calculate the dynamic power as below -
	252
	253	Pdyn = dynamic-power-coefficient * V^2 * f
	254
	255	where voltage is in V, frequency is in MHz.
	256
	257	power-domains:
	258	$ref: '/schemas/types.yaml#/definitions/phandle-array'
	259	description:
	260	List of phandles and PM domain specifiers, as defined by bindings of the
	261	PM domain provider (see also ../power_domain.txt).
	262
	263	power-domain-names:
	264	$ref: '/schemas/types.yaml#/definitions/string-array'
	265	description:
	266	A list of power domain name strings sorted in the same order as the
	267	power-domains property.
	268
	269	For PSCI based platforms, the name corresponding to the index of the PSCI
	270	PM domain provider, must be "psci".
	271
	272	qcom,saw:
	273	$ref: '/schemas/types.yaml#/definitions/phandle'
	274	description: \|
	275	Specifies the SAW* node associated with this CPU.
	276
	277	Required for systems that have an "enable-method" property
	278	value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
	279
	280	* arm/msm/qcom,saw2.txt
	281
	282	qcom,acc:
	283	$ref: '/schemas/types.yaml#/definitions/phandle'
	284	description: \|
	285	Specifies the ACC* node associated with this CPU.
	286
	287	Required for systems that have an "enable-method" property
	288	value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
	289
	290	* arm/msm/qcom,kpss-acc.txt
	291
	292	rockchip,pmu:
	293	$ref: '/schemas/types.yaml#/definitions/phandle'
	294	description: \|
	295	Specifies the syscon node controlling the cpu core power domains.
	296
	297	Optional for systems that have an "enable-method"
	298	property value of "rockchip,rk3066-smp"
	299	While optional, it is the preferred way to get access to
	300	the cpu-core power-domains.
	301
	302	secondary-boot-reg:
	303	$ref: '/schemas/types.yaml#/definitions/uint32'
	304	description: \|
	305	Required for systems that have an "enable-method" property value of
	306	"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
	307
	308	This includes the following SoCs: \|
	309	BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
	310	BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
	311
	312	The secondary-boot-reg property is a u32 value that specifies the
	313	physical address of the register used to request the ROM holding pen
	314	code release a secondary CPU. The value written to the register is
	315	formed by encoding the target CPU id into the low bits of the
	316	physical start address it should jump to.
	317
	318	if:
	319	# If the enable-method property contains one of those values
	320	properties:
	321	enable-method:
	322	contains:
	323	enum:
	324	- brcm,bcm11351-cpu-method
	325	- brcm,bcm23550
	326	- brcm,bcm-nsp-smp
	327	# and if enable-method is present
	328	required:
	329	- enable-method
	330
	331	then:
	332	required:
	333	- secondary-boot-reg
	334
	335	required:
	336	- device_type
	337	- reg
	338	- compatible
	339
	340	dependencies:
	341	rockchip,pmu: [enable-method]
	342
	343	additionalProperties: true
	344
	345	examples:
	346	- \|
	347	cpus {
	348	#size-cells = <0>;
	349	#address-cells = <1>;
	350
	351	cpu@0 {
	352	device_type = "cpu";
	353	compatible = "arm,cortex-a15";
	354	reg = <0x0>;
	355	};
	356
	357	cpu@1 {
	358	device_type = "cpu";
	359	compatible = "arm,cortex-a15";
	360	reg = <0x1>;
	361	};
	362
	363	cpu@100 {
	364	device_type = "cpu";
	365	compatible = "arm,cortex-a7";
	366	reg = <0x100>;
	367	};
	368
	369	cpu@101 {
	370	device_type = "cpu";
	371	compatible = "arm,cortex-a7";
	372	reg = <0x101>;
	373	};
	374	};
	375
	376	- \|
	377	// Example 2 (Cortex-A8 uniprocessor 32-bit system):
	378	cpus {
	379	#size-cells = <0>;
	380	#address-cells = <1>;
	381
	382	cpu@0 {
	383	device_type = "cpu";
	384	compatible = "arm,cortex-a8";
	385	reg = <0x0>;
	386	};
	387	};
	388
	389	- \|
	390	// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
	391	cpus {
	392	#size-cells = <0>;
	393	#address-cells = <1>;
	394
	395	cpu@0 {
	396	device_type = "cpu";
	397	compatible = "arm,arm926ej-s";
	398	reg = <0x0>;
	399	};
	400	};
	401
	402	- \|
	403	// Example 4 (ARM Cortex-A57 64-bit system):
	404	cpus {
	405	#size-cells = <0>;
	406	#address-cells = <2>;
	407
	408	cpu@0 {
	409	device_type = "cpu";
	410	compatible = "arm,cortex-a57";
	411	reg = <0x0 0x0>;
	412	enable-method = "spin-table";
	413	cpu-release-addr = <0 0x20000000>;
	414	};
	415
	416	cpu@1 {
	417	device_type = "cpu";
	418	compatible = "arm,cortex-a57";
	419	reg = <0x0 0x1>;
	420	enable-method = "spin-table";
	421	cpu-release-addr = <0 0x20000000>;
	422	};
	423
	424	cpu@100 {
	425	device_type = "cpu";
	426	compatible = "arm,cortex-a57";
	427	reg = <0x0 0x100>;
	428	enable-method = "spin-table";
	429	cpu-release-addr = <0 0x20000000>;
	430	};
	431
	432	cpu@101 {
	433	device_type = "cpu";
	434	compatible = "arm,cortex-a57";
	435	reg = <0x0 0x101>;
	436	enable-method = "spin-table";
	437	cpu-release-addr = <0 0x20000000>;
	438	};
	439
	440	cpu@10000 {
	441	device_type = "cpu";
	442	compatible = "arm,cortex-a57";
	443	reg = <0x0 0x10000>;
	444	enable-method = "spin-table";
	445	cpu-release-addr = <0 0x20000000>;
	446	};
	447
	448	cpu@10001 {
	449	device_type = "cpu";
	450	compatible = "arm,cortex-a57";
	451	reg = <0x0 0x10001>;
	452	enable-method = "spin-table";
	453	cpu-release-addr = <0 0x20000000>;
	454	};
	455
	456	cpu@10100 {
	457	device_type = "cpu";
	458	compatible = "arm,cortex-a57";
	459	reg = <0x0 0x10100>;
	460	enable-method = "spin-table";
	461	cpu-release-addr = <0 0x20000000>;
	462	};
	463
	464	cpu@10101 {
	465	device_type = "cpu";
	466	compatible = "arm,cortex-a57";
	467	reg = <0x0 0x10101>;
	468	enable-method = "spin-table";
	469	cpu-release-addr = <0 0x20000000>;
	470	};
	471
	472	cpu@100000000 {
	473	device_type = "cpu";
	474	compatible = "arm,cortex-a57";
	475	reg = <0x1 0x0>;
	476	enable-method = "spin-table";
	477	cpu-release-addr = <0 0x20000000>;
	478	};
	479
	480	cpu@100000001 {
	481	device_type = "cpu";
	482	compatible = "arm,cortex-a57";
	483	reg = <0x1 0x1>;
	484	enable-method = "spin-table";
	485	cpu-release-addr = <0 0x20000000>;
	486	};
	487
	488	cpu@100000100 {
	489	device_type = "cpu";
	490	compatible = "arm,cortex-a57";
	491	reg = <0x1 0x100>;
	492	enable-method = "spin-table";
	493	cpu-release-addr = <0 0x20000000>;
	494	};
	495
	496	cpu@100000101 {
	497	device_type = "cpu";
	498	compatible = "arm,cortex-a57";
	499	reg = <0x1 0x101>;
	500	enable-method = "spin-table";
	501	cpu-release-addr = <0 0x20000000>;
	502	};
	503
	504	cpu@100010000 {
	505	device_type = "cpu";
	506	compatible = "arm,cortex-a57";
	507	reg = <0x1 0x10000>;
	508	enable-method = "spin-table";
	509	cpu-release-addr = <0 0x20000000>;
	510	};
	511
	512	cpu@100010001 {
	513	device_type = "cpu";
	514	compatible = "arm,cortex-a57";
	515	reg = <0x1 0x10001>;
	516	enable-method = "spin-table";
	517	cpu-release-addr = <0 0x20000000>;
	518	};
	519
	520	cpu@100010100 {
	521	device_type = "cpu";
	522	compatible = "arm,cortex-a57";
	523	reg = <0x1 0x10100>;
	524	enable-method = "spin-table";
	525	cpu-release-addr = <0 0x20000000>;
	526	};
	527
	528	cpu@100010101 {
	529	device_type = "cpu";
	530	compatible = "arm,cortex-a57";
	531	reg = <0x1 0x10101>;
	532	enable-method = "spin-table";
	533	cpu-release-addr = <0 0x20000000>;
	534	};
	535	};
	536	...