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Commit | Line | Data |
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1 | config ARM | |
2 | bool | |
3 | default y | |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE | |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
6 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST | |
7 | select ARCH_HAVE_CUSTOM_GPIO_H | |
8 | select ARCH_MIGHT_HAVE_PC_PARPORT | |
9 | select ARCH_USE_BUILTIN_BSWAP | |
10 | select ARCH_USE_CMPXCHG_LOCKREF | |
11 | select ARCH_WANT_IPC_PARSE_VERSION | |
12 | select BUILDTIME_EXTABLE_SORT if MMU | |
13 | select CLONE_BACKWARDS | |
14 | select CPU_PM if (SUSPEND || CPU_IDLE) | |
15 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS | |
16 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) | |
17 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP | |
18 | select GENERIC_IDLE_POLL_SETUP | |
19 | select GENERIC_IRQ_PROBE | |
20 | select GENERIC_IRQ_SHOW | |
21 | select GENERIC_PCI_IOMAP | |
22 | select GENERIC_SCHED_CLOCK | |
23 | select GENERIC_SMP_IDLE_THREAD | |
24 | select GENERIC_STRNCPY_FROM_USER | |
25 | select GENERIC_STRNLEN_USER | |
26 | select HARDIRQS_SW_RESEND | |
27 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL | |
28 | select HAVE_ARCH_KGDB | |
29 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) | |
30 | select HAVE_ARCH_TRACEHOOK | |
31 | select HAVE_BPF_JIT | |
32 | select HAVE_CONTEXT_TRACKING | |
33 | select HAVE_C_RECORDMCOUNT | |
34 | select HAVE_CC_STACKPROTECTOR | |
35 | select HAVE_DEBUG_KMEMLEAK | |
36 | select HAVE_DMA_API_DEBUG | |
37 | select HAVE_DMA_ATTRS | |
38 | select HAVE_DMA_CONTIGUOUS if MMU | |
39 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) | |
40 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU | |
41 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) | |
42 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) | |
43 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) | |
44 | select HAVE_GENERIC_DMA_COHERENT | |
45 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) | |
46 | select HAVE_IDE if PCI || ISA || PCMCIA | |
47 | select HAVE_IRQ_TIME_ACCOUNTING | |
48 | select HAVE_KERNEL_GZIP | |
49 | select HAVE_KERNEL_LZ4 | |
50 | select HAVE_KERNEL_LZMA | |
51 | select HAVE_KERNEL_LZO | |
52 | select HAVE_KERNEL_XZ | |
53 | select HAVE_KPROBES if !XIP_KERNEL | |
54 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
55 | select HAVE_MEMBLOCK | |
56 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND | |
57 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) | |
58 | select HAVE_PERF_EVENTS | |
59 | select HAVE_PERF_REGS | |
60 | select HAVE_PERF_USER_STACK_DUMP | |
61 | select HAVE_REGS_AND_STACK_ACCESS_API | |
62 | select HAVE_SYSCALL_TRACEPOINTS | |
63 | select HAVE_UID16 | |
64 | select HAVE_VIRT_CPU_ACCOUNTING_GEN | |
65 | select IRQ_FORCED_THREADING | |
66 | select KTIME_SCALAR | |
67 | select MODULES_USE_ELF_REL | |
68 | select NO_BOOTMEM | |
69 | select OLD_SIGACTION | |
70 | select OLD_SIGSUSPEND3 | |
71 | select PERF_USE_VMALLOC | |
72 | select RTC_LIB | |
73 | select SYS_SUPPORTS_APM_EMULATION | |
74 | # Above selects are sorted alphabetically; please add new ones | |
75 | # according to that. Thanks. | |
76 | help | |
77 | The ARM series is a line of low-power-consumption RISC chip designs | |
78 | licensed by ARM Ltd and targeted at embedded applications and | |
79 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer | |
80 | manufactured, but legacy ARM-based PC hardware remains popular in | |
81 | Europe. There is an ARM Linux project with a web page at | |
82 | <http://www.arm.linux.org.uk/>. | |
83 | ||
84 | config ARM_HAS_SG_CHAIN | |
85 | bool | |
86 | ||
87 | config NEED_SG_DMA_LENGTH | |
88 | bool | |
89 | ||
90 | config ARM_DMA_USE_IOMMU | |
91 | bool | |
92 | select ARM_HAS_SG_CHAIN | |
93 | select NEED_SG_DMA_LENGTH | |
94 | ||
95 | if ARM_DMA_USE_IOMMU | |
96 | ||
97 | config ARM_DMA_IOMMU_ALIGNMENT | |
98 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
99 | range 4 9 | |
100 | default 8 | |
101 | help | |
102 | DMA mapping framework by default aligns all buffers to the smallest | |
103 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
104 | size. This works well for buffers up to a few hundreds kilobytes, but | |
105 | for larger buffers it just a waste of address space. Drivers which has | |
106 | relatively small addressing window (like 64Mib) might run out of | |
107 | virtual space with just a few allocations. | |
108 | ||
109 | With this parameter you can specify the maximum PAGE_SIZE order for | |
110 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
111 | specified order. The order is expressed as a power of two multiplied | |
112 | by the PAGE_SIZE. | |
113 | ||
114 | endif | |
115 | ||
116 | config HAVE_PWM | |
117 | bool | |
118 | ||
119 | config MIGHT_HAVE_PCI | |
120 | bool | |
121 | ||
122 | config SYS_SUPPORTS_APM_EMULATION | |
123 | bool | |
124 | ||
125 | config HAVE_TCM | |
126 | bool | |
127 | select GENERIC_ALLOCATOR | |
128 | ||
129 | config HAVE_PROC_CPU | |
130 | bool | |
131 | ||
132 | config NO_IOPORT | |
133 | bool | |
134 | ||
135 | config EISA | |
136 | bool | |
137 | ---help--- | |
138 | The Extended Industry Standard Architecture (EISA) bus was | |
139 | developed as an open alternative to the IBM MicroChannel bus. | |
140 | ||
141 | The EISA bus provided some of the features of the IBM MicroChannel | |
142 | bus while maintaining backward compatibility with cards made for | |
143 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
144 | 1995 when it was made obsolete by the PCI bus. | |
145 | ||
146 | Say Y here if you are building a kernel for an EISA-based machine. | |
147 | ||
148 | Otherwise, say N. | |
149 | ||
150 | config SBUS | |
151 | bool | |
152 | ||
153 | config STACKTRACE_SUPPORT | |
154 | bool | |
155 | default y | |
156 | ||
157 | config HAVE_LATENCYTOP_SUPPORT | |
158 | bool | |
159 | depends on !SMP | |
160 | default y | |
161 | ||
162 | config LOCKDEP_SUPPORT | |
163 | bool | |
164 | default y | |
165 | ||
166 | config TRACE_IRQFLAGS_SUPPORT | |
167 | bool | |
168 | default y | |
169 | ||
170 | config RWSEM_GENERIC_SPINLOCK | |
171 | bool | |
172 | default y | |
173 | ||
174 | config RWSEM_XCHGADD_ALGORITHM | |
175 | bool | |
176 | ||
177 | config ARCH_HAS_ILOG2_U32 | |
178 | bool | |
179 | ||
180 | config ARCH_HAS_ILOG2_U64 | |
181 | bool | |
182 | ||
183 | config ARCH_HAS_CPUFREQ | |
184 | bool | |
185 | help | |
186 | Internal node to signify that the ARCH has CPUFREQ support | |
187 | and that the relevant menu configurations are displayed for | |
188 | it. | |
189 | ||
190 | config ARCH_HAS_BANDGAP | |
191 | bool | |
192 | ||
193 | config GENERIC_HWEIGHT | |
194 | bool | |
195 | default y | |
196 | ||
197 | config GENERIC_CALIBRATE_DELAY | |
198 | bool | |
199 | default y | |
200 | ||
201 | config ARCH_MAY_HAVE_PC_FDC | |
202 | bool | |
203 | ||
204 | config ZONE_DMA | |
205 | bool | |
206 | ||
207 | config NEED_DMA_MAP_STATE | |
208 | def_bool y | |
209 | ||
210 | config ARCH_HAS_DMA_SET_COHERENT_MASK | |
211 | bool | |
212 | ||
213 | config GENERIC_ISA_DMA | |
214 | bool | |
215 | ||
216 | config FIQ | |
217 | bool | |
218 | ||
219 | config NEED_RET_TO_USER | |
220 | bool | |
221 | ||
222 | config ARCH_MTD_XIP | |
223 | bool | |
224 | ||
225 | config VECTORS_BASE | |
226 | hex | |
227 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR | |
228 | default DRAM_BASE if REMAP_VECTORS_TO_RAM | |
229 | default 0x00000000 | |
230 | help | |
231 | The base address of exception vectors. This must be two pages | |
232 | in size. | |
233 | ||
234 | config ARM_PATCH_PHYS_VIRT | |
235 | bool "Patch physical to virtual translations at runtime" if EMBEDDED | |
236 | default y | |
237 | depends on !XIP_KERNEL && MMU | |
238 | depends on !ARCH_REALVIEW || !SPARSEMEM | |
239 | help | |
240 | Patch phys-to-virt and virt-to-phys translation functions at | |
241 | boot and module load time according to the position of the | |
242 | kernel in system memory. | |
243 | ||
244 | This can only be used with non-XIP MMU kernels where the base | |
245 | of physical memory is at a 16MB boundary. | |
246 | ||
247 | Only disable this option if you know that you do not require | |
248 | this feature (eg, building a kernel for a single machine) and | |
249 | you need to shrink the kernel to the minimal size. | |
250 | ||
251 | config NEED_MACH_GPIO_H | |
252 | bool | |
253 | help | |
254 | Select this when mach/gpio.h is required to provide special | |
255 | definitions for this platform. The need for mach/gpio.h should | |
256 | be avoided when possible. | |
257 | ||
258 | config NEED_MACH_IO_H | |
259 | bool | |
260 | help | |
261 | Select this when mach/io.h is required to provide special | |
262 | definitions for this platform. The need for mach/io.h should | |
263 | be avoided when possible. | |
264 | ||
265 | config NEED_MACH_MEMORY_H | |
266 | bool | |
267 | help | |
268 | Select this when mach/memory.h is required to provide special | |
269 | definitions for this platform. The need for mach/memory.h should | |
270 | be avoided when possible. | |
271 | ||
272 | config PHYS_OFFSET | |
273 | hex "Physical address of main memory" if MMU | |
274 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H | |
275 | default DRAM_BASE if !MMU | |
276 | help | |
277 | Please provide the physical address corresponding to the | |
278 | location of main memory in your system. | |
279 | ||
280 | config GENERIC_BUG | |
281 | def_bool y | |
282 | depends on BUG | |
283 | ||
284 | source "init/Kconfig" | |
285 | ||
286 | source "kernel/Kconfig.freezer" | |
287 | ||
288 | menu "System Type" | |
289 | ||
290 | config MMU | |
291 | bool "MMU-based Paged Memory Management Support" | |
292 | default y | |
293 | help | |
294 | Select if you want MMU-based virtualised addressing space | |
295 | support by paged memory management. If unsure, say 'Y'. | |
296 | ||
297 | # | |
298 | # The "ARM system type" choice list is ordered alphabetically by option | |
299 | # text. Please add new entries in the option alphabetic order. | |
300 | # | |
301 | choice | |
302 | prompt "ARM system type" | |
303 | default ARCH_VERSATILE if !MMU | |
304 | default ARCH_MULTIPLATFORM if MMU | |
305 | ||
306 | config ARCH_MULTIPLATFORM | |
307 | bool "Allow multiple platforms to be selected" | |
308 | depends on MMU | |
309 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
310 | select ARM_PATCH_PHYS_VIRT | |
311 | select AUTO_ZRELADDR | |
312 | select COMMON_CLK | |
313 | select GENERIC_CLOCKEVENTS | |
314 | select MULTI_IRQ_HANDLER | |
315 | select SPARSE_IRQ | |
316 | select USE_OF | |
317 | ||
318 | config ARCH_INTEGRATOR | |
319 | bool "ARM Ltd. Integrator family" | |
320 | select ARCH_HAS_CPUFREQ | |
321 | select ARM_AMBA | |
322 | select ARM_PATCH_PHYS_VIRT | |
323 | select AUTO_ZRELADDR | |
324 | select COMMON_CLK | |
325 | select COMMON_CLK_VERSATILE | |
326 | select GENERIC_CLOCKEVENTS | |
327 | select HAVE_TCM | |
328 | select ICST | |
329 | select MULTI_IRQ_HANDLER | |
330 | select NEED_MACH_MEMORY_H | |
331 | select PLAT_VERSATILE | |
332 | select SPARSE_IRQ | |
333 | select USE_OF | |
334 | select VERSATILE_FPGA_IRQ | |
335 | help | |
336 | Support for ARM's Integrator platform. | |
337 | ||
338 | config ARCH_REALVIEW | |
339 | bool "ARM Ltd. RealView family" | |
340 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
341 | select ARM_AMBA | |
342 | select ARM_TIMER_SP804 | |
343 | select COMMON_CLK | |
344 | select COMMON_CLK_VERSATILE | |
345 | select GENERIC_CLOCKEVENTS | |
346 | select GPIO_PL061 if GPIOLIB | |
347 | select ICST | |
348 | select NEED_MACH_MEMORY_H | |
349 | select PLAT_VERSATILE | |
350 | select PLAT_VERSATILE_CLCD | |
351 | help | |
352 | This enables support for ARM Ltd RealView boards. | |
353 | ||
354 | config ARCH_VERSATILE | |
355 | bool "ARM Ltd. Versatile family" | |
356 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
357 | select ARM_AMBA | |
358 | select ARM_TIMER_SP804 | |
359 | select ARM_VIC | |
360 | select CLKDEV_LOOKUP | |
361 | select GENERIC_CLOCKEVENTS | |
362 | select HAVE_MACH_CLKDEV | |
363 | select ICST | |
364 | select PLAT_VERSATILE | |
365 | select PLAT_VERSATILE_CLCD | |
366 | select PLAT_VERSATILE_CLOCK | |
367 | select VERSATILE_FPGA_IRQ | |
368 | help | |
369 | This enables support for ARM Ltd Versatile board. | |
370 | ||
371 | config ARCH_AT91 | |
372 | bool "Atmel AT91" | |
373 | select ARCH_REQUIRE_GPIOLIB | |
374 | select CLKDEV_LOOKUP | |
375 | select IRQ_DOMAIN | |
376 | select NEED_MACH_GPIO_H | |
377 | select NEED_MACH_IO_H if PCCARD | |
378 | select PINCTRL | |
379 | select PINCTRL_AT91 if USE_OF | |
380 | help | |
381 | This enables support for systems based on Atmel | |
382 | AT91RM9200 and AT91SAM9* processors. | |
383 | ||
384 | config ARCH_CLPS711X | |
385 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
386 | select ARCH_REQUIRE_GPIOLIB | |
387 | select AUTO_ZRELADDR | |
388 | select CLKSRC_MMIO | |
389 | select COMMON_CLK | |
390 | select CPU_ARM720T | |
391 | select GENERIC_CLOCKEVENTS | |
392 | select MFD_SYSCON | |
393 | select MULTI_IRQ_HANDLER | |
394 | select SPARSE_IRQ | |
395 | help | |
396 | Support for Cirrus Logic 711x/721x/731x based boards. | |
397 | ||
398 | config ARCH_GEMINI | |
399 | bool "Cortina Systems Gemini" | |
400 | select ARCH_REQUIRE_GPIOLIB | |
401 | select CLKSRC_MMIO | |
402 | select CPU_FA526 | |
403 | select GENERIC_CLOCKEVENTS | |
404 | help | |
405 | Support for the Cortina Systems Gemini family SoCs | |
406 | ||
407 | config ARCH_EBSA110 | |
408 | bool "EBSA-110" | |
409 | select ARCH_USES_GETTIMEOFFSET | |
410 | select CPU_SA110 | |
411 | select ISA | |
412 | select NEED_MACH_IO_H | |
413 | select NEED_MACH_MEMORY_H | |
414 | select NO_IOPORT | |
415 | help | |
416 | This is an evaluation board for the StrongARM processor available | |
417 | from Digital. It has limited hardware on-board, including an | |
418 | Ethernet interface, two PCMCIA sockets, two serial ports and a | |
419 | parallel port. | |
420 | ||
421 | config ARCH_EFM32 | |
422 | bool "Energy Micro efm32" | |
423 | depends on !MMU | |
424 | select ARCH_REQUIRE_GPIOLIB | |
425 | select ARM_NVIC | |
426 | # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, | |
427 | # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO | |
428 | select CLKSRC_MMIO | |
429 | select CLKSRC_OF | |
430 | select COMMON_CLK | |
431 | select CPU_V7M | |
432 | select GENERIC_CLOCKEVENTS | |
433 | select NO_DMA | |
434 | select NO_IOPORT | |
435 | select SPARSE_IRQ | |
436 | select USE_OF | |
437 | help | |
438 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
439 | processors. | |
440 | ||
441 | config ARCH_EP93XX | |
442 | bool "EP93xx-based" | |
443 | select ARCH_HAS_HOLES_MEMORYMODEL | |
444 | select ARCH_REQUIRE_GPIOLIB | |
445 | select ARCH_USES_GETTIMEOFFSET | |
446 | select ARM_AMBA | |
447 | select ARM_VIC | |
448 | select CLKDEV_LOOKUP | |
449 | select CPU_ARM920T | |
450 | select NEED_MACH_MEMORY_H | |
451 | help | |
452 | This enables support for the Cirrus EP93xx series of CPUs. | |
453 | ||
454 | config ARCH_FOOTBRIDGE | |
455 | bool "FootBridge" | |
456 | select CPU_SA110 | |
457 | select FOOTBRIDGE | |
458 | select GENERIC_CLOCKEVENTS | |
459 | select HAVE_IDE | |
460 | select NEED_MACH_IO_H if !MMU | |
461 | select NEED_MACH_MEMORY_H | |
462 | help | |
463 | Support for systems based on the DC21285 companion chip | |
464 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
465 | ||
466 | config ARCH_NETX | |
467 | bool "Hilscher NetX based" | |
468 | select ARM_VIC | |
469 | select CLKSRC_MMIO | |
470 | select CPU_ARM926T | |
471 | select GENERIC_CLOCKEVENTS | |
472 | help | |
473 | This enables support for systems based on the Hilscher NetX Soc | |
474 | ||
475 | config ARCH_IOP13XX | |
476 | bool "IOP13xx-based" | |
477 | depends on MMU | |
478 | select CPU_XSC3 | |
479 | select NEED_MACH_MEMORY_H | |
480 | select NEED_RET_TO_USER | |
481 | select PCI | |
482 | select PLAT_IOP | |
483 | select VMSPLIT_1G | |
484 | help | |
485 | Support for Intel's IOP13XX (XScale) family of processors. | |
486 | ||
487 | config ARCH_IOP32X | |
488 | bool "IOP32x-based" | |
489 | depends on MMU | |
490 | select ARCH_REQUIRE_GPIOLIB | |
491 | select CPU_XSCALE | |
492 | select GPIO_IOP | |
493 | select NEED_RET_TO_USER | |
494 | select PCI | |
495 | select PLAT_IOP | |
496 | help | |
497 | Support for Intel's 80219 and IOP32X (XScale) family of | |
498 | processors. | |
499 | ||
500 | config ARCH_IOP33X | |
501 | bool "IOP33x-based" | |
502 | depends on MMU | |
503 | select ARCH_REQUIRE_GPIOLIB | |
504 | select CPU_XSCALE | |
505 | select GPIO_IOP | |
506 | select NEED_RET_TO_USER | |
507 | select PCI | |
508 | select PLAT_IOP | |
509 | help | |
510 | Support for Intel's IOP33X (XScale) family of processors. | |
511 | ||
512 | config ARCH_IXP4XX | |
513 | bool "IXP4xx-based" | |
514 | depends on MMU | |
515 | select ARCH_HAS_DMA_SET_COHERENT_MASK | |
516 | select ARCH_SUPPORTS_BIG_ENDIAN | |
517 | select ARCH_REQUIRE_GPIOLIB | |
518 | select CLKSRC_MMIO | |
519 | select CPU_XSCALE | |
520 | select DMABOUNCE if PCI | |
521 | select GENERIC_CLOCKEVENTS | |
522 | select MIGHT_HAVE_PCI | |
523 | select NEED_MACH_IO_H | |
524 | select USB_EHCI_BIG_ENDIAN_DESC | |
525 | select USB_EHCI_BIG_ENDIAN_MMIO | |
526 | help | |
527 | Support for Intel's IXP4XX (XScale) family of processors. | |
528 | ||
529 | config ARCH_DOVE | |
530 | bool "Marvell Dove" | |
531 | select ARCH_REQUIRE_GPIOLIB | |
532 | select CPU_PJ4 | |
533 | select GENERIC_CLOCKEVENTS | |
534 | select MIGHT_HAVE_PCI | |
535 | select MVEBU_MBUS | |
536 | select PINCTRL | |
537 | select PINCTRL_DOVE | |
538 | select PLAT_ORION_LEGACY | |
539 | select USB_ARCH_HAS_EHCI | |
540 | help | |
541 | Support for the Marvell Dove SoC 88AP510 | |
542 | ||
543 | config ARCH_KIRKWOOD | |
544 | bool "Marvell Kirkwood" | |
545 | select ARCH_HAS_CPUFREQ | |
546 | select ARCH_REQUIRE_GPIOLIB | |
547 | select CPU_FEROCEON | |
548 | select GENERIC_CLOCKEVENTS | |
549 | select MVEBU_MBUS | |
550 | select PCI | |
551 | select PCI_QUIRKS | |
552 | select PINCTRL | |
553 | select PINCTRL_KIRKWOOD | |
554 | select PLAT_ORION_LEGACY | |
555 | help | |
556 | Support for the following Marvell Kirkwood series SoCs: | |
557 | 88F6180, 88F6192 and 88F6281. | |
558 | ||
559 | config ARCH_MV78XX0 | |
560 | bool "Marvell MV78xx0" | |
561 | select ARCH_REQUIRE_GPIOLIB | |
562 | select CPU_FEROCEON | |
563 | select GENERIC_CLOCKEVENTS | |
564 | select MVEBU_MBUS | |
565 | select PCI | |
566 | select PLAT_ORION_LEGACY | |
567 | help | |
568 | Support for the following Marvell MV78xx0 series SoCs: | |
569 | MV781x0, MV782x0. | |
570 | ||
571 | config ARCH_ORION5X | |
572 | bool "Marvell Orion" | |
573 | depends on MMU | |
574 | select ARCH_REQUIRE_GPIOLIB | |
575 | select CPU_FEROCEON | |
576 | select GENERIC_CLOCKEVENTS | |
577 | select MVEBU_MBUS | |
578 | select PCI | |
579 | select PLAT_ORION_LEGACY | |
580 | help | |
581 | Support for the following Marvell Orion 5x series SoCs: | |
582 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), | |
583 | Orion-2 (5281), Orion-1-90 (6183). | |
584 | ||
585 | config ARCH_MMP | |
586 | bool "Marvell PXA168/910/MMP2" | |
587 | depends on MMU | |
588 | select ARCH_REQUIRE_GPIOLIB | |
589 | select CLKDEV_LOOKUP | |
590 | select GENERIC_ALLOCATOR | |
591 | select GENERIC_CLOCKEVENTS | |
592 | select GPIO_PXA | |
593 | select IRQ_DOMAIN | |
594 | select MULTI_IRQ_HANDLER | |
595 | select PINCTRL | |
596 | select PLAT_PXA | |
597 | select SPARSE_IRQ | |
598 | help | |
599 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. | |
600 | ||
601 | config ARCH_KS8695 | |
602 | bool "Micrel/Kendin KS8695" | |
603 | select ARCH_REQUIRE_GPIOLIB | |
604 | select CLKSRC_MMIO | |
605 | select CPU_ARM922T | |
606 | select GENERIC_CLOCKEVENTS | |
607 | select NEED_MACH_MEMORY_H | |
608 | help | |
609 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
610 | System-on-Chip devices. | |
611 | ||
612 | config ARCH_W90X900 | |
613 | bool "Nuvoton W90X900 CPU" | |
614 | select ARCH_REQUIRE_GPIOLIB | |
615 | select CLKDEV_LOOKUP | |
616 | select CLKSRC_MMIO | |
617 | select CPU_ARM926T | |
618 | select GENERIC_CLOCKEVENTS | |
619 | help | |
620 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, | |
621 | At present, the w90x900 has been renamed nuc900, regarding | |
622 | the ARM series product line, you can login the following | |
623 | link address to know more. | |
624 | ||
625 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
626 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
627 | ||
628 | config ARCH_LPC32XX | |
629 | bool "NXP LPC32XX" | |
630 | select ARCH_REQUIRE_GPIOLIB | |
631 | select ARM_AMBA | |
632 | select CLKDEV_LOOKUP | |
633 | select CLKSRC_MMIO | |
634 | select CPU_ARM926T | |
635 | select GENERIC_CLOCKEVENTS | |
636 | select HAVE_IDE | |
637 | select HAVE_PWM | |
638 | select USB_ARCH_HAS_OHCI | |
639 | select USE_OF | |
640 | help | |
641 | Support for the NXP LPC32XX family of processors | |
642 | ||
643 | config ARCH_PXA | |
644 | bool "PXA2xx/PXA3xx-based" | |
645 | depends on MMU | |
646 | select ARCH_HAS_CPUFREQ | |
647 | select ARCH_MTD_XIP | |
648 | select ARCH_REQUIRE_GPIOLIB | |
649 | select ARM_CPU_SUSPEND if PM | |
650 | select AUTO_ZRELADDR | |
651 | select CLKDEV_LOOKUP | |
652 | select CLKSRC_MMIO | |
653 | select GENERIC_CLOCKEVENTS | |
654 | select GPIO_PXA | |
655 | select HAVE_IDE | |
656 | select MULTI_IRQ_HANDLER | |
657 | select PLAT_PXA | |
658 | select SPARSE_IRQ | |
659 | help | |
660 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | |
661 | ||
662 | config ARCH_MSM_NODT | |
663 | bool "Qualcomm MSM" | |
664 | select ARCH_MSM | |
665 | select ARCH_REQUIRE_GPIOLIB | |
666 | select COMMON_CLK | |
667 | select GENERIC_CLOCKEVENTS | |
668 | help | |
669 | Support for Qualcomm MSM/QSD based systems. This runs on the | |
670 | apps processor of the MSM/QSD and depends on a shared memory | |
671 | interface to the modem processor which runs the baseband | |
672 | stack and controls some vital subsystems | |
673 | (clock and power control, etc). | |
674 | ||
675 | config ARCH_SHMOBILE_LEGACY | |
676 | bool "Renesas ARM SoCs (non-multiplatform)" | |
677 | select ARCH_SHMOBILE | |
678 | select ARM_PATCH_PHYS_VIRT | |
679 | select CLKDEV_LOOKUP | |
680 | select GENERIC_CLOCKEVENTS | |
681 | select HAVE_ARM_SCU if SMP | |
682 | select HAVE_ARM_TWD if SMP | |
683 | select HAVE_MACH_CLKDEV | |
684 | select HAVE_SMP | |
685 | select MIGHT_HAVE_CACHE_L2X0 | |
686 | select MULTI_IRQ_HANDLER | |
687 | select NO_IOPORT | |
688 | select PINCTRL | |
689 | select PM_GENERIC_DOMAINS if PM | |
690 | select SPARSE_IRQ | |
691 | help | |
692 | Support for Renesas ARM SoC platforms using a non-multiplatform | |
693 | kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car | |
694 | and RZ families. | |
695 | ||
696 | config ARCH_RPC | |
697 | bool "RiscPC" | |
698 | select ARCH_ACORN | |
699 | select ARCH_MAY_HAVE_PC_FDC | |
700 | select ARCH_SPARSEMEM_ENABLE | |
701 | select ARCH_USES_GETTIMEOFFSET | |
702 | select FIQ | |
703 | select HAVE_IDE | |
704 | select HAVE_PATA_PLATFORM | |
705 | select ISA_DMA_API | |
706 | select NEED_MACH_IO_H | |
707 | select NEED_MACH_MEMORY_H | |
708 | select NO_IOPORT | |
709 | select VIRT_TO_BUS | |
710 | help | |
711 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
712 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
713 | ||
714 | config ARCH_SA1100 | |
715 | bool "SA1100-based" | |
716 | select ARCH_HAS_CPUFREQ | |
717 | select ARCH_MTD_XIP | |
718 | select ARCH_REQUIRE_GPIOLIB | |
719 | select ARCH_SPARSEMEM_ENABLE | |
720 | select CLKDEV_LOOKUP | |
721 | select CLKSRC_MMIO | |
722 | select CPU_FREQ | |
723 | select CPU_SA1100 | |
724 | select GENERIC_CLOCKEVENTS | |
725 | select HAVE_IDE | |
726 | select ISA | |
727 | select NEED_MACH_MEMORY_H | |
728 | select SPARSE_IRQ | |
729 | help | |
730 | Support for StrongARM 11x0 based boards. | |
731 | ||
732 | config ARCH_S3C24XX | |
733 | bool "Samsung S3C24XX SoCs" | |
734 | select ARCH_HAS_CPUFREQ | |
735 | select ARCH_REQUIRE_GPIOLIB | |
736 | select CLKDEV_LOOKUP | |
737 | select CLKSRC_SAMSUNG_PWM | |
738 | select GENERIC_CLOCKEVENTS | |
739 | select GPIO_SAMSUNG | |
740 | select HAVE_S3C2410_I2C if I2C | |
741 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
742 | select HAVE_S3C_RTC if RTC_CLASS | |
743 | select MULTI_IRQ_HANDLER | |
744 | select NEED_MACH_IO_H | |
745 | select SAMSUNG_ATAGS | |
746 | help | |
747 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 | |
748 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
749 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
750 | Samsung SMDK2410 development board (and derivatives). | |
751 | ||
752 | config ARCH_S3C64XX | |
753 | bool "Samsung S3C64XX" | |
754 | select ARCH_HAS_CPUFREQ | |
755 | select ARCH_REQUIRE_GPIOLIB | |
756 | select ARM_AMBA | |
757 | select ARM_VIC | |
758 | select CLKDEV_LOOKUP | |
759 | select CLKSRC_SAMSUNG_PWM | |
760 | select COMMON_CLK | |
761 | select CPU_V6K | |
762 | select GENERIC_CLOCKEVENTS | |
763 | select GPIO_SAMSUNG | |
764 | select HAVE_S3C2410_I2C if I2C | |
765 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
766 | select HAVE_TCM | |
767 | select NO_IOPORT | |
768 | select PLAT_SAMSUNG | |
769 | select PM_GENERIC_DOMAINS | |
770 | select S3C_DEV_NAND | |
771 | select S3C_GPIO_TRACK | |
772 | select SAMSUNG_ATAGS | |
773 | select SAMSUNG_WAKEMASK | |
774 | select SAMSUNG_WDT_RESET | |
775 | select USB_ARCH_HAS_OHCI | |
776 | help | |
777 | Samsung S3C64XX series based systems | |
778 | ||
779 | config ARCH_S5P64X0 | |
780 | bool "Samsung S5P6440 S5P6450" | |
781 | select CLKDEV_LOOKUP | |
782 | select CLKSRC_SAMSUNG_PWM | |
783 | select CPU_V6 | |
784 | select GENERIC_CLOCKEVENTS | |
785 | select GPIO_SAMSUNG | |
786 | select HAVE_S3C2410_I2C if I2C | |
787 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
788 | select HAVE_S3C_RTC if RTC_CLASS | |
789 | select NEED_MACH_GPIO_H | |
790 | select SAMSUNG_ATAGS | |
791 | select SAMSUNG_WDT_RESET | |
792 | help | |
793 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, | |
794 | SMDK6450. | |
795 | ||
796 | config ARCH_S5PC100 | |
797 | bool "Samsung S5PC100" | |
798 | select ARCH_REQUIRE_GPIOLIB | |
799 | select CLKDEV_LOOKUP | |
800 | select CLKSRC_SAMSUNG_PWM | |
801 | select CPU_V7 | |
802 | select GENERIC_CLOCKEVENTS | |
803 | select GPIO_SAMSUNG | |
804 | select HAVE_S3C2410_I2C if I2C | |
805 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
806 | select HAVE_S3C_RTC if RTC_CLASS | |
807 | select NEED_MACH_GPIO_H | |
808 | select SAMSUNG_ATAGS | |
809 | select SAMSUNG_WDT_RESET | |
810 | help | |
811 | Samsung S5PC100 series based systems | |
812 | ||
813 | config ARCH_S5PV210 | |
814 | bool "Samsung S5PV210/S5PC110" | |
815 | select ARCH_HAS_CPUFREQ | |
816 | select ARCH_HAS_HOLES_MEMORYMODEL | |
817 | select ARCH_SPARSEMEM_ENABLE | |
818 | select CLKDEV_LOOKUP | |
819 | select CLKSRC_SAMSUNG_PWM | |
820 | select CPU_V7 | |
821 | select GENERIC_CLOCKEVENTS | |
822 | select GPIO_SAMSUNG | |
823 | select HAVE_S3C2410_I2C if I2C | |
824 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
825 | select HAVE_S3C_RTC if RTC_CLASS | |
826 | select NEED_MACH_GPIO_H | |
827 | select NEED_MACH_MEMORY_H | |
828 | select SAMSUNG_ATAGS | |
829 | help | |
830 | Samsung S5PV210/S5PC110 series based systems | |
831 | ||
832 | config ARCH_EXYNOS | |
833 | bool "Samsung EXYNOS" | |
834 | select ARCH_HAS_CPUFREQ | |
835 | select ARCH_HAS_HOLES_MEMORYMODEL | |
836 | select ARCH_REQUIRE_GPIOLIB | |
837 | select ARCH_SPARSEMEM_ENABLE | |
838 | select ARM_GIC | |
839 | select COMMON_CLK | |
840 | select CPU_V7 | |
841 | select GENERIC_CLOCKEVENTS | |
842 | select HAVE_S3C2410_I2C if I2C | |
843 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
844 | select HAVE_S3C_RTC if RTC_CLASS | |
845 | select NEED_MACH_MEMORY_H | |
846 | select SPARSE_IRQ | |
847 | select USE_OF | |
848 | help | |
849 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) | |
850 | ||
851 | config ARCH_DAVINCI | |
852 | bool "TI DaVinci" | |
853 | select ARCH_HAS_HOLES_MEMORYMODEL | |
854 | select ARCH_REQUIRE_GPIOLIB | |
855 | select CLKDEV_LOOKUP | |
856 | select GENERIC_ALLOCATOR | |
857 | select GENERIC_CLOCKEVENTS | |
858 | select GENERIC_IRQ_CHIP | |
859 | select HAVE_IDE | |
860 | select TI_PRIV_EDMA | |
861 | select USE_OF | |
862 | select ZONE_DMA | |
863 | help | |
864 | Support for TI's DaVinci platform. | |
865 | ||
866 | config ARCH_OMAP1 | |
867 | bool "TI OMAP1" | |
868 | depends on MMU | |
869 | select ARCH_HAS_CPUFREQ | |
870 | select ARCH_HAS_HOLES_MEMORYMODEL | |
871 | select ARCH_OMAP | |
872 | select ARCH_REQUIRE_GPIOLIB | |
873 | select CLKDEV_LOOKUP | |
874 | select CLKSRC_MMIO | |
875 | select GENERIC_CLOCKEVENTS | |
876 | select GENERIC_IRQ_CHIP | |
877 | select HAVE_IDE | |
878 | select IRQ_DOMAIN | |
879 | select NEED_MACH_IO_H if PCCARD | |
880 | select NEED_MACH_MEMORY_H | |
881 | help | |
882 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) | |
883 | ||
884 | endchoice | |
885 | ||
886 | menu "Multiple platform selection" | |
887 | depends on ARCH_MULTIPLATFORM | |
888 | ||
889 | comment "CPU Core family selection" | |
890 | ||
891 | config ARCH_MULTI_V4T | |
892 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
893 | depends on !ARCH_MULTI_V6_V7 | |
894 | select ARCH_MULTI_V4_V5 | |
895 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ | |
896 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
897 | CPU_ARM925T || CPU_ARM940T) | |
898 | ||
899 | config ARCH_MULTI_V5 | |
900 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
901 | depends on !ARCH_MULTI_V6_V7 | |
902 | select ARCH_MULTI_V4_V5 | |
903 | select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ | |
904 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
905 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
906 | ||
907 | config ARCH_MULTI_V4_V5 | |
908 | bool | |
909 | ||
910 | config ARCH_MULTI_V6 | |
911 | bool "ARMv6 based platforms (ARM11)" | |
912 | select ARCH_MULTI_V6_V7 | |
913 | select CPU_V6 | |
914 | ||
915 | config ARCH_MULTI_V7 | |
916 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" | |
917 | default y | |
918 | select ARCH_MULTI_V6_V7 | |
919 | select CPU_V7 | |
920 | select HAVE_SMP | |
921 | ||
922 | config ARCH_MULTI_V6_V7 | |
923 | bool | |
924 | ||
925 | config ARCH_MULTI_CPU_AUTO | |
926 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
927 | select ARCH_MULTI_V5 | |
928 | ||
929 | endmenu | |
930 | ||
931 | # | |
932 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
933 | # Kconfigs may be included either alphabetically (according to the | |
934 | # plat- suffix) or along side the corresponding mach-* source. | |
935 | # | |
936 | source "arch/arm/mach-mvebu/Kconfig" | |
937 | ||
938 | source "arch/arm/mach-at91/Kconfig" | |
939 | ||
940 | source "arch/arm/mach-bcm/Kconfig" | |
941 | ||
942 | source "arch/arm/mach-bcm2835/Kconfig" | |
943 | ||
944 | source "arch/arm/mach-berlin/Kconfig" | |
945 | ||
946 | source "arch/arm/mach-clps711x/Kconfig" | |
947 | ||
948 | source "arch/arm/mach-cns3xxx/Kconfig" | |
949 | ||
950 | source "arch/arm/mach-davinci/Kconfig" | |
951 | ||
952 | source "arch/arm/mach-dove/Kconfig" | |
953 | ||
954 | source "arch/arm/mach-ep93xx/Kconfig" | |
955 | ||
956 | source "arch/arm/mach-footbridge/Kconfig" | |
957 | ||
958 | source "arch/arm/mach-gemini/Kconfig" | |
959 | ||
960 | source "arch/arm/mach-highbank/Kconfig" | |
961 | ||
962 | source "arch/arm/mach-hisi/Kconfig" | |
963 | ||
964 | source "arch/arm/mach-integrator/Kconfig" | |
965 | ||
966 | source "arch/arm/mach-iop32x/Kconfig" | |
967 | ||
968 | source "arch/arm/mach-iop33x/Kconfig" | |
969 | ||
970 | source "arch/arm/mach-iop13xx/Kconfig" | |
971 | ||
972 | source "arch/arm/mach-ixp4xx/Kconfig" | |
973 | ||
974 | source "arch/arm/mach-keystone/Kconfig" | |
975 | ||
976 | source "arch/arm/mach-kirkwood/Kconfig" | |
977 | ||
978 | source "arch/arm/mach-ks8695/Kconfig" | |
979 | ||
980 | source "arch/arm/mach-msm/Kconfig" | |
981 | ||
982 | source "arch/arm/mach-moxart/Kconfig" | |
983 | ||
984 | source "arch/arm/mach-mv78xx0/Kconfig" | |
985 | ||
986 | source "arch/arm/mach-imx/Kconfig" | |
987 | ||
988 | source "arch/arm/mach-mxs/Kconfig" | |
989 | ||
990 | source "arch/arm/mach-netx/Kconfig" | |
991 | ||
992 | source "arch/arm/mach-nomadik/Kconfig" | |
993 | ||
994 | source "arch/arm/mach-nspire/Kconfig" | |
995 | ||
996 | source "arch/arm/plat-omap/Kconfig" | |
997 | ||
998 | source "arch/arm/mach-omap1/Kconfig" | |
999 | ||
1000 | source "arch/arm/mach-omap2/Kconfig" | |
1001 | ||
1002 | source "arch/arm/mach-orion5x/Kconfig" | |
1003 | ||
1004 | source "arch/arm/mach-picoxcell/Kconfig" | |
1005 | ||
1006 | source "arch/arm/mach-pxa/Kconfig" | |
1007 | source "arch/arm/plat-pxa/Kconfig" | |
1008 | ||
1009 | source "arch/arm/mach-mmp/Kconfig" | |
1010 | ||
1011 | source "arch/arm/mach-realview/Kconfig" | |
1012 | ||
1013 | source "arch/arm/mach-rockchip/Kconfig" | |
1014 | ||
1015 | source "arch/arm/mach-sa1100/Kconfig" | |
1016 | ||
1017 | source "arch/arm/plat-samsung/Kconfig" | |
1018 | ||
1019 | source "arch/arm/mach-socfpga/Kconfig" | |
1020 | ||
1021 | source "arch/arm/mach-spear/Kconfig" | |
1022 | ||
1023 | source "arch/arm/mach-sti/Kconfig" | |
1024 | ||
1025 | source "arch/arm/mach-s3c24xx/Kconfig" | |
1026 | ||
1027 | source "arch/arm/mach-s3c64xx/Kconfig" | |
1028 | ||
1029 | source "arch/arm/mach-s5p64x0/Kconfig" | |
1030 | ||
1031 | source "arch/arm/mach-s5pc100/Kconfig" | |
1032 | ||
1033 | source "arch/arm/mach-s5pv210/Kconfig" | |
1034 | ||
1035 | source "arch/arm/mach-exynos/Kconfig" | |
1036 | ||
1037 | source "arch/arm/mach-shmobile/Kconfig" | |
1038 | ||
1039 | source "arch/arm/mach-sunxi/Kconfig" | |
1040 | ||
1041 | source "arch/arm/mach-prima2/Kconfig" | |
1042 | ||
1043 | source "arch/arm/mach-tegra/Kconfig" | |
1044 | ||
1045 | source "arch/arm/mach-u300/Kconfig" | |
1046 | ||
1047 | source "arch/arm/mach-ux500/Kconfig" | |
1048 | ||
1049 | source "arch/arm/mach-versatile/Kconfig" | |
1050 | ||
1051 | source "arch/arm/mach-vexpress/Kconfig" | |
1052 | source "arch/arm/plat-versatile/Kconfig" | |
1053 | ||
1054 | source "arch/arm/mach-virt/Kconfig" | |
1055 | ||
1056 | source "arch/arm/mach-vt8500/Kconfig" | |
1057 | ||
1058 | source "arch/arm/mach-w90x900/Kconfig" | |
1059 | ||
1060 | source "arch/arm/mach-zynq/Kconfig" | |
1061 | ||
1062 | # Definitions to make life easier | |
1063 | config ARCH_ACORN | |
1064 | bool | |
1065 | ||
1066 | config PLAT_IOP | |
1067 | bool | |
1068 | select GENERIC_CLOCKEVENTS | |
1069 | ||
1070 | config PLAT_ORION | |
1071 | bool | |
1072 | select CLKSRC_MMIO | |
1073 | select COMMON_CLK | |
1074 | select GENERIC_IRQ_CHIP | |
1075 | select IRQ_DOMAIN | |
1076 | ||
1077 | config PLAT_ORION_LEGACY | |
1078 | bool | |
1079 | select PLAT_ORION | |
1080 | ||
1081 | config PLAT_PXA | |
1082 | bool | |
1083 | ||
1084 | config PLAT_VERSATILE | |
1085 | bool | |
1086 | ||
1087 | config ARM_TIMER_SP804 | |
1088 | bool | |
1089 | select CLKSRC_MMIO | |
1090 | select CLKSRC_OF if OF | |
1091 | ||
1092 | source "arch/arm/firmware/Kconfig" | |
1093 | ||
1094 | source arch/arm/mm/Kconfig | |
1095 | ||
1096 | config ARM_NR_BANKS | |
1097 | int | |
1098 | default 16 if ARCH_EP93XX | |
1099 | default 8 | |
1100 | ||
1101 | config IWMMXT | |
1102 | bool "Enable iWMMXt support" if !CPU_PJ4 | |
1103 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 | |
1104 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 | |
1105 | help | |
1106 | Enable support for iWMMXt context switching at run time if | |
1107 | running on a CPU that supports it. | |
1108 | ||
1109 | config MULTI_IRQ_HANDLER | |
1110 | bool | |
1111 | help | |
1112 | Allow each machine to specify it's own IRQ handler at run time. | |
1113 | ||
1114 | if !MMU | |
1115 | source "arch/arm/Kconfig-nommu" | |
1116 | endif | |
1117 | ||
1118 | config PJ4B_ERRATA_4742 | |
1119 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1120 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1121 | default y | |
1122 | help | |
1123 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1124 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1125 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1126 | instructions. This sensitivity can result in a CPU hang scenario. | |
1127 | Workaround: | |
1128 | The software must insert either a Data Synchronization Barrier (DSB) | |
1129 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1130 | instruction | |
1131 | ||
1132 | config ARM_ERRATA_326103 | |
1133 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1134 | depends on CPU_V6 | |
1135 | help | |
1136 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1137 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1138 | treat the access as a read, preventing a COW from occurring and | |
1139 | causing the faulting task to livelock. | |
1140 | ||
1141 | config ARM_ERRATA_411920 | |
1142 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
1143 | depends on CPU_V6 || CPU_V6K | |
1144 | help | |
1145 | Invalidation of the Instruction Cache operation can | |
1146 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1147 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1148 | recommended workaround. | |
1149 | ||
1150 | config ARM_ERRATA_430973 | |
1151 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1152 | depends on CPU_V7 | |
1153 | help | |
1154 | This option enables the workaround for the 430973 Cortex-A8 | |
1155 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1156 | interworking branch is replaced with another code sequence at the | |
1157 | same virtual address, whether due to self-modifying code or virtual | |
1158 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1159 | stale interworking branch prediction. This results in Cortex-A8 | |
1160 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1161 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1162 | and also flushes the branch target cache at every context switch. | |
1163 | Note that setting specific bits in the ACTLR register may not be | |
1164 | available in non-secure mode. | |
1165 | ||
1166 | config ARM_ERRATA_458693 | |
1167 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1168 | depends on CPU_V7 | |
1169 | depends on !ARCH_MULTIPLATFORM | |
1170 | help | |
1171 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1172 | erratum. For very specific sequences of memory operations, it is | |
1173 | possible for a hazard condition intended for a cache line to instead | |
1174 | be incorrectly associated with a different cache line. This false | |
1175 | hazard might then cause a processor deadlock. The workaround enables | |
1176 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1177 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1178 | register may not be available in non-secure mode. | |
1179 | ||
1180 | config ARM_ERRATA_460075 | |
1181 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1182 | depends on CPU_V7 | |
1183 | depends on !ARCH_MULTIPLATFORM | |
1184 | help | |
1185 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1186 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1187 | situation in which recent store transactions to the L2 cache are lost | |
1188 | and overwritten with stale memory contents from external memory. The | |
1189 | workaround disables the write-allocate mode for the L2 cache via the | |
1190 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1191 | may not be available in non-secure mode. | |
1192 | ||
1193 | config ARM_ERRATA_742230 | |
1194 | bool "ARM errata: DMB operation may be faulty" | |
1195 | depends on CPU_V7 && SMP | |
1196 | depends on !ARCH_MULTIPLATFORM | |
1197 | help | |
1198 | This option enables the workaround for the 742230 Cortex-A9 | |
1199 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1200 | between two write operations may not ensure the correct visibility | |
1201 | ordering of the two writes. This workaround sets a specific bit in | |
1202 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1203 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1204 | the two writes. | |
1205 | ||
1206 | config ARM_ERRATA_742231 | |
1207 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1208 | depends on CPU_V7 && SMP | |
1209 | depends on !ARCH_MULTIPLATFORM | |
1210 | help | |
1211 | This option enables the workaround for the 742231 Cortex-A9 | |
1212 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1213 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1214 | accessing some data located in the same cache line, may get corrupted | |
1215 | data due to bad handling of the address hazard when the line gets | |
1216 | replaced from one of the CPUs at the same time as another CPU is | |
1217 | accessing it. This workaround sets specific bits in the diagnostic | |
1218 | register of the Cortex-A9 which reduces the linefill issuing | |
1219 | capabilities of the processor. | |
1220 | ||
1221 | config PL310_ERRATA_588369 | |
1222 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" | |
1223 | depends on CACHE_L2X0 | |
1224 | help | |
1225 | The PL310 L2 cache controller implements three types of Clean & | |
1226 | Invalidate maintenance operations: by Physical Address | |
1227 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1228 | They are architecturally defined to behave as the execution of a | |
1229 | clean operation followed immediately by an invalidate operation, | |
1230 | both performing to the same memory location. This functionality | |
1231 | is not correctly implemented in PL310 as clean lines are not | |
1232 | invalidated as a result of these operations. | |
1233 | ||
1234 | config ARM_ERRATA_643719 | |
1235 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1236 | depends on CPU_V7 && SMP | |
1237 | help | |
1238 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1239 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1240 | register returns zero when it should return one. The workaround | |
1241 | corrects this value, ensuring cache maintenance operations which use | |
1242 | it behave as intended and avoiding data corruption. | |
1243 | ||
1244 | config ARM_ERRATA_720789 | |
1245 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
1246 | depends on CPU_V7 | |
1247 | help | |
1248 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1249 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1250 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1251 | As a consequence of this erratum, some TLB entries which should be | |
1252 | invalidated are not, resulting in an incoherency in the system page | |
1253 | tables. The workaround changes the TLB flushing routines to invalidate | |
1254 | entries regardless of the ASID. | |
1255 | ||
1256 | config PL310_ERRATA_727915 | |
1257 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" | |
1258 | depends on CACHE_L2X0 | |
1259 | help | |
1260 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1261 | operation (offset 0x7FC). This operation runs in background so that | |
1262 | PL310 can handle normal accesses while it is in progress. Under very | |
1263 | rare circumstances, due to this erratum, write data can be lost when | |
1264 | PL310 treats a cacheable write transaction during a Clean & | |
1265 | Invalidate by Way operation. | |
1266 | ||
1267 | config ARM_ERRATA_743622 | |
1268 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1269 | depends on CPU_V7 | |
1270 | depends on !ARCH_MULTIPLATFORM | |
1271 | help | |
1272 | This option enables the workaround for the 743622 Cortex-A9 | |
1273 | (r2p*) erratum. Under very rare conditions, a faulty | |
1274 | optimisation in the Cortex-A9 Store Buffer may lead to data | |
1275 | corruption. This workaround sets a specific bit in the diagnostic | |
1276 | register of the Cortex-A9 which disables the Store Buffer | |
1277 | optimisation, preventing the defect from occurring. This has no | |
1278 | visible impact on the overall performance or power consumption of the | |
1279 | processor. | |
1280 | ||
1281 | config ARM_ERRATA_751472 | |
1282 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
1283 | depends on CPU_V7 | |
1284 | depends on !ARCH_MULTIPLATFORM | |
1285 | help | |
1286 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1287 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1288 | completion of a following broadcasted operation if the second | |
1289 | operation is received by a CPU before the ICIALLUIS has completed, | |
1290 | potentially leading to corrupted entries in the cache or TLB. | |
1291 | ||
1292 | config PL310_ERRATA_753970 | |
1293 | bool "PL310 errata: cache sync operation may be faulty" | |
1294 | depends on CACHE_PL310 | |
1295 | help | |
1296 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1297 | ||
1298 | Under some condition the effect of cache sync operation on | |
1299 | the store buffer still remains when the operation completes. | |
1300 | This means that the store buffer is always asked to drain and | |
1301 | this prevents it from merging any further writes. The workaround | |
1302 | is to replace the normal offset of cache sync operation (0x730) | |
1303 | by another offset targeting an unmapped PL310 register 0x740. | |
1304 | This has the same effect as the cache sync operation: store buffer | |
1305 | drain and waiting for all buffers empty. | |
1306 | ||
1307 | config ARM_ERRATA_754322 | |
1308 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1309 | depends on CPU_V7 | |
1310 | help | |
1311 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1312 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1313 | which starts prior to an ASID switch but completes afterwards. This | |
1314 | can populate the micro-TLB with a stale entry which may be hit with | |
1315 | the new ASID. This workaround places two dsb instructions in the mm | |
1316 | switching code so that no page table walks can cross the ASID switch. | |
1317 | ||
1318 | config ARM_ERRATA_754327 | |
1319 | bool "ARM errata: no automatic Store Buffer drain" | |
1320 | depends on CPU_V7 && SMP | |
1321 | help | |
1322 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1323 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1324 | mechanism and therefore a livelock may occur if an external agent | |
1325 | continuously polls a memory location waiting to observe an update. | |
1326 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1327 | written polling loops from denying visibility of updates to memory. | |
1328 | ||
1329 | config ARM_ERRATA_364296 | |
1330 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
1331 | depends on CPU_V6 | |
1332 | help | |
1333 | This options enables the workaround for the 364296 ARM1136 | |
1334 | r0p2 erratum (possible cache data corruption with | |
1335 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1336 | the auxiliary control register and the FI bit in the control | |
1337 | register, thus disabling hit-under-miss without putting the | |
1338 | processor into full low interrupt latency mode. ARM11MPCore | |
1339 | is not affected. | |
1340 | ||
1341 | config ARM_ERRATA_764369 | |
1342 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1343 | depends on CPU_V7 && SMP | |
1344 | help | |
1345 | This option enables the workaround for erratum 764369 | |
1346 | affecting Cortex-A9 MPCore with two or more processors (all | |
1347 | current revisions). Under certain timing circumstances, a data | |
1348 | cache line maintenance operation by MVA targeting an Inner | |
1349 | Shareable memory region may fail to proceed up to either the | |
1350 | Point of Coherency or to the Point of Unification of the | |
1351 | system. This workaround adds a DSB instruction before the | |
1352 | relevant cache maintenance functions and sets a specific bit | |
1353 | in the diagnostic control register of the SCU. | |
1354 | ||
1355 | config PL310_ERRATA_769419 | |
1356 | bool "PL310 errata: no automatic Store Buffer drain" | |
1357 | depends on CACHE_L2X0 | |
1358 | help | |
1359 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1360 | not automatically drain. This can cause normal, non-cacheable | |
1361 | writes to be retained when the memory system is idle, leading | |
1362 | to suboptimal I/O performance for drivers using coherent DMA. | |
1363 | This option adds a write barrier to the cpu_idle loop so that, | |
1364 | on systems with an outer cache, the store buffer is drained | |
1365 | explicitly. | |
1366 | ||
1367 | config ARM_ERRATA_775420 | |
1368 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1369 | depends on CPU_V7 | |
1370 | help | |
1371 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1372 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1373 | operation aborts with MMU exception, it might cause the processor | |
1374 | to deadlock. This workaround puts DSB before executing ISB if | |
1375 | an abort may occur on cache maintenance. | |
1376 | ||
1377 | config ARM_ERRATA_798181 | |
1378 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1379 | depends on CPU_V7 && SMP | |
1380 | help | |
1381 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1382 | adequately shooting down all use of the old entries. This | |
1383 | option enables the Linux kernel workaround for this erratum | |
1384 | which sends an IPI to the CPUs that are running the same ASID | |
1385 | as the one being invalidated. | |
1386 | ||
1387 | config ARM_ERRATA_773022 | |
1388 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1389 | depends on CPU_V7 | |
1390 | help | |
1391 | This option enables the workaround for the 773022 Cortex-A15 | |
1392 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1393 | loop buffer may deliver incorrect instructions. This | |
1394 | workaround disables the loop buffer to avoid the erratum. | |
1395 | ||
1396 | endmenu | |
1397 | ||
1398 | source "arch/arm/common/Kconfig" | |
1399 | ||
1400 | menu "Bus support" | |
1401 | ||
1402 | config ARM_AMBA | |
1403 | bool | |
1404 | ||
1405 | config ISA | |
1406 | bool | |
1407 | help | |
1408 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1409 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1410 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1411 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1412 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1413 | ||
1414 | # Select ISA DMA controller support | |
1415 | config ISA_DMA | |
1416 | bool | |
1417 | select ISA_DMA_API | |
1418 | ||
1419 | # Select ISA DMA interface | |
1420 | config ISA_DMA_API | |
1421 | bool | |
1422 | ||
1423 | config PCI | |
1424 | bool "PCI support" if MIGHT_HAVE_PCI | |
1425 | help | |
1426 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1427 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1428 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1429 | VESA. If you have PCI, say Y, otherwise N. | |
1430 | ||
1431 | config PCI_DOMAINS | |
1432 | bool | |
1433 | depends on PCI | |
1434 | ||
1435 | config PCI_NANOENGINE | |
1436 | bool "BSE nanoEngine PCI support" | |
1437 | depends on SA1100_NANOENGINE | |
1438 | help | |
1439 | Enable PCI on the BSE nanoEngine board. | |
1440 | ||
1441 | config PCI_SYSCALL | |
1442 | def_bool PCI | |
1443 | ||
1444 | config PCI_HOST_ITE8152 | |
1445 | bool | |
1446 | depends on PCI && MACH_ARMCORE | |
1447 | default y | |
1448 | select DMABOUNCE | |
1449 | ||
1450 | source "drivers/pci/Kconfig" | |
1451 | source "drivers/pci/pcie/Kconfig" | |
1452 | ||
1453 | source "drivers/pcmcia/Kconfig" | |
1454 | ||
1455 | endmenu | |
1456 | ||
1457 | menu "Kernel Features" | |
1458 | ||
1459 | config HAVE_SMP | |
1460 | bool | |
1461 | help | |
1462 | This option should be selected by machines which have an SMP- | |
1463 | capable CPU. | |
1464 | ||
1465 | The only effect of this option is to make the SMP-related | |
1466 | options available to the user for configuration. | |
1467 | ||
1468 | config SMP | |
1469 | bool "Symmetric Multi-Processing" | |
1470 | depends on CPU_V6K || CPU_V7 | |
1471 | depends on GENERIC_CLOCKEVENTS | |
1472 | depends on HAVE_SMP | |
1473 | depends on MMU || ARM_MPU | |
1474 | help | |
1475 | This enables support for systems with more than one CPU. If you have | |
1476 | a system with only one CPU, say N. If you have a system with more | |
1477 | than one CPU, say Y. | |
1478 | ||
1479 | If you say N here, the kernel will run on uni- and multiprocessor | |
1480 | machines, but will use only one CPU of a multiprocessor machine. If | |
1481 | you say Y here, the kernel will run on many, but not all, | |
1482 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1483 | will run faster if you say N here. | |
1484 | ||
1485 | See also <file:Documentation/x86/i386/IO-APIC.txt>, | |
1486 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at | |
1487 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. | |
1488 | ||
1489 | If you don't know what to do here, say N. | |
1490 | ||
1491 | config SMP_ON_UP | |
1492 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
1493 | depends on SMP && !XIP_KERNEL && MMU | |
1494 | default y | |
1495 | help | |
1496 | SMP kernels contain instructions which fail on non-SMP processors. | |
1497 | Enabling this option allows the kernel to modify itself to make | |
1498 | these instructions safe. Disabling it allows about 1K of space | |
1499 | savings. | |
1500 | ||
1501 | If you don't know what to do here, say Y. | |
1502 | ||
1503 | config ARM_CPU_TOPOLOGY | |
1504 | bool "Support cpu topology definition" | |
1505 | depends on SMP && CPU_V7 | |
1506 | default y | |
1507 | help | |
1508 | Support ARM cpu topology definition. The MPIDR register defines | |
1509 | affinity between processors which is then used to describe the cpu | |
1510 | topology of an ARM System. | |
1511 | ||
1512 | config SCHED_MC | |
1513 | bool "Multi-core scheduler support" | |
1514 | depends on ARM_CPU_TOPOLOGY | |
1515 | help | |
1516 | Multi-core scheduler support improves the CPU scheduler's decision | |
1517 | making when dealing with multi-core CPU chips at a cost of slightly | |
1518 | increased overhead in some places. If unsure say N here. | |
1519 | ||
1520 | config SCHED_SMT | |
1521 | bool "SMT scheduler support" | |
1522 | depends on ARM_CPU_TOPOLOGY | |
1523 | help | |
1524 | Improves the CPU scheduler's decision making when dealing with | |
1525 | MultiThreading at a cost of slightly increased overhead in some | |
1526 | places. If unsure say N here. | |
1527 | ||
1528 | config HAVE_ARM_SCU | |
1529 | bool | |
1530 | help | |
1531 | This option enables support for the ARM system coherency unit | |
1532 | ||
1533 | config HAVE_ARM_ARCH_TIMER | |
1534 | bool "Architected timer support" | |
1535 | depends on CPU_V7 | |
1536 | select ARM_ARCH_TIMER | |
1537 | select GENERIC_CLOCKEVENTS | |
1538 | help | |
1539 | This option enables support for the ARM architected timer | |
1540 | ||
1541 | config HAVE_ARM_TWD | |
1542 | bool | |
1543 | depends on SMP | |
1544 | select CLKSRC_OF if OF | |
1545 | help | |
1546 | This options enables support for the ARM timer and watchdog unit | |
1547 | ||
1548 | config MCPM | |
1549 | bool "Multi-Cluster Power Management" | |
1550 | depends on CPU_V7 && SMP | |
1551 | help | |
1552 | This option provides the common power management infrastructure | |
1553 | for (multi-)cluster based systems, such as big.LITTLE based | |
1554 | systems. | |
1555 | ||
1556 | config BIG_LITTLE | |
1557 | bool "big.LITTLE support (Experimental)" | |
1558 | depends on CPU_V7 && SMP | |
1559 | select MCPM | |
1560 | help | |
1561 | This option enables support selections for the big.LITTLE | |
1562 | system architecture. | |
1563 | ||
1564 | config BL_SWITCHER | |
1565 | bool "big.LITTLE switcher support" | |
1566 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU | |
1567 | select CPU_PM | |
1568 | select ARM_CPU_SUSPEND | |
1569 | help | |
1570 | The big.LITTLE "switcher" provides the core functionality to | |
1571 | transparently handle transition between a cluster of A15's | |
1572 | and a cluster of A7's in a big.LITTLE system. | |
1573 | ||
1574 | config BL_SWITCHER_DUMMY_IF | |
1575 | tristate "Simple big.LITTLE switcher user interface" | |
1576 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1577 | help | |
1578 | This is a simple and dummy char dev interface to control | |
1579 | the big.LITTLE switcher core code. It is meant for | |
1580 | debugging purposes only. | |
1581 | ||
1582 | choice | |
1583 | prompt "Memory split" | |
1584 | default VMSPLIT_3G | |
1585 | help | |
1586 | Select the desired split between kernel and user memory. | |
1587 | ||
1588 | If you are not absolutely sure what you are doing, leave this | |
1589 | option alone! | |
1590 | ||
1591 | config VMSPLIT_3G | |
1592 | bool "3G/1G user/kernel split" | |
1593 | config VMSPLIT_2G | |
1594 | bool "2G/2G user/kernel split" | |
1595 | config VMSPLIT_1G | |
1596 | bool "1G/3G user/kernel split" | |
1597 | endchoice | |
1598 | ||
1599 | config PAGE_OFFSET | |
1600 | hex | |
1601 | default 0x40000000 if VMSPLIT_1G | |
1602 | default 0x80000000 if VMSPLIT_2G | |
1603 | default 0xC0000000 | |
1604 | ||
1605 | config NR_CPUS | |
1606 | int "Maximum number of CPUs (2-32)" | |
1607 | range 2 32 | |
1608 | depends on SMP | |
1609 | default "4" | |
1610 | ||
1611 | config HOTPLUG_CPU | |
1612 | bool "Support for hot-pluggable CPUs" | |
1613 | depends on SMP | |
1614 | help | |
1615 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1616 | can be controlled through /sys/devices/system/cpu. | |
1617 | ||
1618 | config ARM_PSCI | |
1619 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1620 | depends on CPU_V7 | |
1621 | help | |
1622 | Say Y here if you want Linux to communicate with system firmware | |
1623 | implementing the PSCI specification for CPU-centric power | |
1624 | management operations described in ARM document number ARM DEN | |
1625 | 0022A ("Power State Coordination Interface System Software on | |
1626 | ARM processors"). | |
1627 | ||
1628 | # The GPIO number here must be sorted by descending number. In case of | |
1629 | # a multiplatform kernel, we just want the highest value required by the | |
1630 | # selected platforms. | |
1631 | config ARCH_NR_GPIO | |
1632 | int | |
1633 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA | |
1634 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX | |
1635 | default 392 if ARCH_U8500 | |
1636 | default 352 if ARCH_VT8500 | |
1637 | default 288 if ARCH_SUNXI | |
1638 | default 264 if MACH_H4700 | |
1639 | default 0 | |
1640 | help | |
1641 | Maximum number of GPIOs in the system. | |
1642 | ||
1643 | If unsure, leave the default value. | |
1644 | ||
1645 | source kernel/Kconfig.preempt | |
1646 | ||
1647 | config HZ_FIXED | |
1648 | int | |
1649 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ | |
1650 | ARCH_S5PV210 || ARCH_EXYNOS4 | |
1651 | default AT91_TIMER_HZ if ARCH_AT91 | |
1652 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY | |
1653 | default 0 | |
1654 | ||
1655 | choice | |
1656 | depends on HZ_FIXED = 0 | |
1657 | prompt "Timer frequency" | |
1658 | ||
1659 | config HZ_100 | |
1660 | bool "100 Hz" | |
1661 | ||
1662 | config HZ_200 | |
1663 | bool "200 Hz" | |
1664 | ||
1665 | config HZ_250 | |
1666 | bool "250 Hz" | |
1667 | ||
1668 | config HZ_300 | |
1669 | bool "300 Hz" | |
1670 | ||
1671 | config HZ_500 | |
1672 | bool "500 Hz" | |
1673 | ||
1674 | config HZ_1000 | |
1675 | bool "1000 Hz" | |
1676 | ||
1677 | endchoice | |
1678 | ||
1679 | config HZ | |
1680 | int | |
1681 | default HZ_FIXED if HZ_FIXED != 0 | |
1682 | default 100 if HZ_100 | |
1683 | default 200 if HZ_200 | |
1684 | default 250 if HZ_250 | |
1685 | default 300 if HZ_300 | |
1686 | default 500 if HZ_500 | |
1687 | default 1000 | |
1688 | ||
1689 | config SCHED_HRTICK | |
1690 | def_bool HIGH_RES_TIMERS | |
1691 | ||
1692 | config THUMB2_KERNEL | |
1693 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY | |
1694 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K | |
1695 | default y if CPU_THUMBONLY | |
1696 | select AEABI | |
1697 | select ARM_ASM_UNIFIED | |
1698 | select ARM_UNWIND | |
1699 | help | |
1700 | By enabling this option, the kernel will be compiled in | |
1701 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1702 | ARM-Thumb syntax is needed. | |
1703 | ||
1704 | If unsure, say N. | |
1705 | ||
1706 | config THUMB2_AVOID_R_ARM_THM_JUMP11 | |
1707 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1708 | depends on THUMB2_KERNEL && MODULES | |
1709 | default y | |
1710 | help | |
1711 | Various binutils versions can resolve Thumb-2 branches to | |
1712 | locally-defined, preemptible global symbols as short-range "b.n" | |
1713 | branch instructions. | |
1714 | ||
1715 | This is a problem, because there's no guarantee the final | |
1716 | destination of the symbol, or any candidate locations for a | |
1717 | trampoline, are within range of the branch. For this reason, the | |
1718 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1719 | relocation in modules at all, and it makes little sense to add | |
1720 | support. | |
1721 | ||
1722 | The symptom is that the kernel fails with an "unsupported | |
1723 | relocation" error when loading some modules. | |
1724 | ||
1725 | Until fixed tools are available, passing | |
1726 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1727 | code which hits this problem, at the cost of a bit of extra runtime | |
1728 | stack usage in some cases. | |
1729 | ||
1730 | The problem is described in more detail at: | |
1731 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1732 | ||
1733 | Only Thumb-2 kernels are affected. | |
1734 | ||
1735 | Unless you are sure your tools don't have this problem, say Y. | |
1736 | ||
1737 | config ARM_ASM_UNIFIED | |
1738 | bool | |
1739 | ||
1740 | config AEABI | |
1741 | bool "Use the ARM EABI to compile the kernel" | |
1742 | help | |
1743 | This option allows for the kernel to be compiled using the latest | |
1744 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1745 | space environment that is also compiled with EABI. | |
1746 | ||
1747 | Since there are major incompatibilities between the legacy ABI and | |
1748 | EABI, especially with regard to structure member alignment, this | |
1749 | option also changes the kernel syscall calling convention to | |
1750 | disambiguate both ABIs and allow for backward compatibility support | |
1751 | (selected with CONFIG_OABI_COMPAT). | |
1752 | ||
1753 | To use this you need GCC version 4.0.0 or later. | |
1754 | ||
1755 | config OABI_COMPAT | |
1756 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" | |
1757 | depends on AEABI && !THUMB2_KERNEL | |
1758 | help | |
1759 | This option preserves the old syscall interface along with the | |
1760 | new (ARM EABI) one. It also provides a compatibility layer to | |
1761 | intercept syscalls that have structure arguments which layout | |
1762 | in memory differs between the legacy ABI and the new ARM EABI | |
1763 | (only for non "thumb" binaries). This option adds a tiny | |
1764 | overhead to all syscalls and produces a slightly larger kernel. | |
1765 | ||
1766 | The seccomp filter system will not be available when this is | |
1767 | selected, since there is no way yet to sensibly distinguish | |
1768 | between calling conventions during filtering. | |
1769 | ||
1770 | If you know you'll be using only pure EABI user space then you | |
1771 | can say N here. If this option is not selected and you attempt | |
1772 | to execute a legacy ABI binary then the result will be | |
1773 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1774 | at all). If in doubt say N. | |
1775 | ||
1776 | config ARCH_HAS_HOLES_MEMORYMODEL | |
1777 | bool | |
1778 | ||
1779 | config ARCH_SPARSEMEM_ENABLE | |
1780 | bool | |
1781 | ||
1782 | config ARCH_SPARSEMEM_DEFAULT | |
1783 | def_bool ARCH_SPARSEMEM_ENABLE | |
1784 | ||
1785 | config ARCH_SELECT_MEMORY_MODEL | |
1786 | def_bool ARCH_SPARSEMEM_ENABLE | |
1787 | ||
1788 | config HAVE_ARCH_PFN_VALID | |
1789 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1790 | ||
1791 | config HIGHMEM | |
1792 | bool "High Memory Support" | |
1793 | depends on MMU | |
1794 | help | |
1795 | The address space of ARM processors is only 4 Gigabytes large | |
1796 | and it has to accommodate user address space, kernel address | |
1797 | space as well as some memory mapped IO. That means that, if you | |
1798 | have a large amount of physical memory and/or IO, not all of the | |
1799 | memory can be "permanently mapped" by the kernel. The physical | |
1800 | memory that is not permanently mapped is called "high memory". | |
1801 | ||
1802 | Depending on the selected kernel/user memory split, minimum | |
1803 | vmalloc space and actual amount of RAM, you may not need this | |
1804 | option which should result in a slightly faster kernel. | |
1805 | ||
1806 | If unsure, say n. | |
1807 | ||
1808 | config HIGHPTE | |
1809 | bool "Allocate 2nd-level pagetables from highmem" | |
1810 | depends on HIGHMEM | |
1811 | ||
1812 | config HW_PERF_EVENTS | |
1813 | bool "Enable hardware performance counter support for perf events" | |
1814 | depends on PERF_EVENTS | |
1815 | default y | |
1816 | help | |
1817 | Enable hardware performance counter support for perf events. If | |
1818 | disabled, perf events will use software events only. | |
1819 | ||
1820 | config SYS_SUPPORTS_HUGETLBFS | |
1821 | def_bool y | |
1822 | depends on ARM_LPAE | |
1823 | ||
1824 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE | |
1825 | def_bool y | |
1826 | depends on ARM_LPAE | |
1827 | ||
1828 | config ARCH_WANT_GENERAL_HUGETLB | |
1829 | def_bool y | |
1830 | ||
1831 | source "mm/Kconfig" | |
1832 | ||
1833 | config FORCE_MAX_ZONEORDER | |
1834 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY | |
1835 | range 11 64 if ARCH_SHMOBILE_LEGACY | |
1836 | default "12" if SOC_AM33XX | |
1837 | default "9" if SA1111 || ARCH_EFM32 | |
1838 | default "11" | |
1839 | help | |
1840 | The kernel memory allocator divides physically contiguous memory | |
1841 | blocks into "zones", where each zone is a power of two number of | |
1842 | pages. This option selects the largest power of two that the kernel | |
1843 | keeps in the memory allocator. If you need to allocate very large | |
1844 | blocks of physically contiguous memory, then you may need to | |
1845 | increase this value. | |
1846 | ||
1847 | This config option is actually maximum order plus one. For example, | |
1848 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1849 | ||
1850 | config ALIGNMENT_TRAP | |
1851 | bool | |
1852 | depends on CPU_CP15_MMU | |
1853 | default y if !ARCH_EBSA110 | |
1854 | select HAVE_PROC_CPU if PROC_FS | |
1855 | help | |
1856 | ARM processors cannot fetch/store information which is not | |
1857 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an | |
1858 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1859 | fetch/store instructions will be emulated in software if you say | |
1860 | here, which has a severe performance impact. This is necessary for | |
1861 | correct operation of some network protocols. With an IP-only | |
1862 | configuration it is safe to say N, otherwise say Y. | |
1863 | ||
1864 | config UACCESS_WITH_MEMCPY | |
1865 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" | |
1866 | depends on MMU | |
1867 | default y if CPU_FEROCEON | |
1868 | help | |
1869 | Implement faster copy_to_user and clear_user methods for CPU | |
1870 | cores where a 8-word STM instruction give significantly higher | |
1871 | memory write throughput than a sequence of individual 32bit stores. | |
1872 | ||
1873 | A possible side effect is a slight increase in scheduling latency | |
1874 | between threads sharing the same address space if they invoke | |
1875 | such copy operations with large buffers. | |
1876 | ||
1877 | However, if the CPU data cache is using a write-allocate mode, | |
1878 | this option is unlikely to provide any performance gain. | |
1879 | ||
1880 | config SECCOMP | |
1881 | bool | |
1882 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1883 | ---help--- | |
1884 | This kernel feature is useful for number crunching applications | |
1885 | that may need to compute untrusted bytecode during their | |
1886 | execution. By using pipes or other transports made available to | |
1887 | the process as file descriptors supporting the read/write | |
1888 | syscalls, it's possible to isolate those applications in | |
1889 | their own address space using seccomp. Once seccomp is | |
1890 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1891 | and the task is only allowed to execute a few safe syscalls | |
1892 | defined by each seccomp mode. | |
1893 | ||
1894 | config SWIOTLB | |
1895 | def_bool y | |
1896 | ||
1897 | config IOMMU_HELPER | |
1898 | def_bool SWIOTLB | |
1899 | ||
1900 | config XEN_DOM0 | |
1901 | def_bool y | |
1902 | depends on XEN | |
1903 | ||
1904 | config XEN | |
1905 | bool "Xen guest support on ARM (EXPERIMENTAL)" | |
1906 | depends on ARM && AEABI && OF | |
1907 | depends on CPU_V7 && !CPU_V6 | |
1908 | depends on !GENERIC_ATOMIC64 | |
1909 | select ARM_PSCI | |
1910 | select SWIOTLB_XEN | |
1911 | select ARCH_DMA_ADDR_T_64BIT | |
1912 | help | |
1913 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1914 | ||
1915 | endmenu | |
1916 | ||
1917 | menu "Boot options" | |
1918 | ||
1919 | config USE_OF | |
1920 | bool "Flattened Device Tree support" | |
1921 | select IRQ_DOMAIN | |
1922 | select OF | |
1923 | select OF_EARLY_FLATTREE | |
1924 | help | |
1925 | Include support for flattened device tree machine descriptions. | |
1926 | ||
1927 | config ATAGS | |
1928 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1929 | default y | |
1930 | help | |
1931 | This is the traditional way of passing data to the kernel at boot | |
1932 | time. If you are solely relying on the flattened device tree (or | |
1933 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1934 | to remove ATAGS support from your kernel binary. If unsure, | |
1935 | leave this to y. | |
1936 | ||
1937 | config DEPRECATED_PARAM_STRUCT | |
1938 | bool "Provide old way to pass kernel parameters" | |
1939 | depends on ATAGS | |
1940 | help | |
1941 | This was deprecated in 2001 and announced to live on for 5 years. | |
1942 | Some old boot loaders still use this way. | |
1943 | ||
1944 | # Compressed boot loader in ROM. Yes, we really want to ask about | |
1945 | # TEXT and BSS so we preserve their values in the config files. | |
1946 | config ZBOOT_ROM_TEXT | |
1947 | hex "Compressed ROM boot loader base address" | |
1948 | default "0" | |
1949 | help | |
1950 | The physical address at which the ROM-able zImage is to be | |
1951 | placed in the target. Platforms which normally make use of | |
1952 | ROM-able zImage formats normally set this to a suitable | |
1953 | value in their defconfig file. | |
1954 | ||
1955 | If ZBOOT_ROM is not enabled, this has no effect. | |
1956 | ||
1957 | config ZBOOT_ROM_BSS | |
1958 | hex "Compressed ROM boot loader BSS address" | |
1959 | default "0" | |
1960 | help | |
1961 | The base address of an area of read/write memory in the target | |
1962 | for the ROM-able zImage which must be available while the | |
1963 | decompressor is running. It must be large enough to hold the | |
1964 | entire decompressed kernel plus an additional 128 KiB. | |
1965 | Platforms which normally make use of ROM-able zImage formats | |
1966 | normally set this to a suitable value in their defconfig file. | |
1967 | ||
1968 | If ZBOOT_ROM is not enabled, this has no effect. | |
1969 | ||
1970 | config ZBOOT_ROM | |
1971 | bool "Compressed boot loader in ROM/flash" | |
1972 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1973 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR | |
1974 | help | |
1975 | Say Y here if you intend to execute your compressed kernel image | |
1976 | (zImage) directly from ROM or flash. If unsure, say N. | |
1977 | ||
1978 | choice | |
1979 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
1980 | depends on ZBOOT_ROM && ARCH_SH7372 | |
1981 | default ZBOOT_ROM_NONE | |
1982 | help | |
1983 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
1984 | With this enabled it is possible to write the ROM-able zImage | |
1985 | kernel image to an MMC or SD card and boot the kernel straight | |
1986 | from the reset vector. At reset the processor Mask ROM will load | |
1987 | the first part of the ROM-able zImage which in turn loads the | |
1988 | rest the kernel image to RAM. | |
1989 | ||
1990 | config ZBOOT_ROM_NONE | |
1991 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1992 | help | |
1993 | Do not load image from SD or MMC | |
1994 | ||
1995 | config ZBOOT_ROM_MMCIF | |
1996 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
1997 | help | |
1998 | Load image from MMCIF hardware block. | |
1999 | ||
2000 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
2001 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
2002 | help | |
2003 | Load image from SDHI hardware block | |
2004 | ||
2005 | endchoice | |
2006 | ||
2007 | config ARM_APPENDED_DTB | |
2008 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
2009 | depends on OF | |
2010 | help | |
2011 | With this option, the boot code will look for a device tree binary | |
2012 | (DTB) appended to zImage | |
2013 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
2014 | ||
2015 | This is meant as a backward compatibility convenience for those | |
2016 | systems with a bootloader that can't be upgraded to accommodate | |
2017 | the documented boot protocol using a device tree. | |
2018 | ||
2019 | Beware that there is very little in terms of protection against | |
2020 | this option being confused by leftover garbage in memory that might | |
2021 | look like a DTB header after a reboot if no actual DTB is appended | |
2022 | to zImage. Do not leave this option active in a production kernel | |
2023 | if you don't intend to always append a DTB. Proper passing of the | |
2024 | location into r2 of a bootloader provided DTB is always preferable | |
2025 | to this option. | |
2026 | ||
2027 | config ARM_ATAG_DTB_COMPAT | |
2028 | bool "Supplement the appended DTB with traditional ATAG information" | |
2029 | depends on ARM_APPENDED_DTB | |
2030 | help | |
2031 | Some old bootloaders can't be updated to a DTB capable one, yet | |
2032 | they provide ATAGs with memory configuration, the ramdisk address, | |
2033 | the kernel cmdline string, etc. Such information is dynamically | |
2034 | provided by the bootloader and can't always be stored in a static | |
2035 | DTB. To allow a device tree enabled kernel to be used with such | |
2036 | bootloaders, this option allows zImage to extract the information | |
2037 | from the ATAG list and store it at run time into the appended DTB. | |
2038 | ||
2039 | choice | |
2040 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
2041 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
2042 | ||
2043 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
2044 | bool "Use bootloader kernel arguments if available" | |
2045 | help | |
2046 | Uses the command-line options passed by the boot loader instead of | |
2047 | the device tree bootargs property. If the boot loader doesn't provide | |
2048 | any, the device tree bootargs property will be used. | |
2049 | ||
2050 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
2051 | bool "Extend with bootloader kernel arguments" | |
2052 | help | |
2053 | The command-line arguments provided by the boot loader will be | |
2054 | appended to the the device tree bootargs property. | |
2055 | ||
2056 | endchoice | |
2057 | ||
2058 | config CMDLINE | |
2059 | string "Default kernel command string" | |
2060 | default "" | |
2061 | help | |
2062 | On some architectures (EBSA110 and CATS), there is currently no way | |
2063 | for the boot loader to pass arguments to the kernel. For these | |
2064 | architectures, you should supply some command-line options at build | |
2065 | time by entering them here. As a minimum, you should specify the | |
2066 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
2067 | ||
2068 | choice | |
2069 | prompt "Kernel command line type" if CMDLINE != "" | |
2070 | default CMDLINE_FROM_BOOTLOADER | |
2071 | depends on ATAGS | |
2072 | ||
2073 | config CMDLINE_FROM_BOOTLOADER | |
2074 | bool "Use bootloader kernel arguments if available" | |
2075 | help | |
2076 | Uses the command-line options passed by the boot loader. If | |
2077 | the boot loader doesn't provide any, the default kernel command | |
2078 | string provided in CMDLINE will be used. | |
2079 | ||
2080 | config CMDLINE_EXTEND | |
2081 | bool "Extend bootloader kernel arguments" | |
2082 | help | |
2083 | The command-line arguments provided by the boot loader will be | |
2084 | appended to the default kernel command string. | |
2085 | ||
2086 | config CMDLINE_FORCE | |
2087 | bool "Always use the default kernel command string" | |
2088 | help | |
2089 | Always use the default kernel command string, even if the boot | |
2090 | loader passes other arguments to the kernel. | |
2091 | This is useful if you cannot or don't want to change the | |
2092 | command-line options your boot loader passes to the kernel. | |
2093 | endchoice | |
2094 | ||
2095 | config XIP_KERNEL | |
2096 | bool "Kernel Execute-In-Place from ROM" | |
2097 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM | |
2098 | help | |
2099 | Execute-In-Place allows the kernel to run from non-volatile storage | |
2100 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
2101 | space since the text section of the kernel is not loaded from flash | |
2102 | to RAM. Read-write sections, such as the data section and stack, | |
2103 | are still copied to RAM. The XIP kernel is not compressed since | |
2104 | it has to run directly from flash, so it will take more space to | |
2105 | store it. The flash address used to link the kernel object files, | |
2106 | and for storing it, is configuration dependent. Therefore, if you | |
2107 | say Y here, you must know the proper physical address where to | |
2108 | store the kernel image depending on your own flash memory usage. | |
2109 | ||
2110 | Also note that the make target becomes "make xipImage" rather than | |
2111 | "make zImage" or "make Image". The final kernel binary to put in | |
2112 | ROM memory will be arch/arm/boot/xipImage. | |
2113 | ||
2114 | If unsure, say N. | |
2115 | ||
2116 | config XIP_PHYS_ADDR | |
2117 | hex "XIP Kernel Physical Location" | |
2118 | depends on XIP_KERNEL | |
2119 | default "0x00080000" | |
2120 | help | |
2121 | This is the physical address in your flash memory the kernel will | |
2122 | be linked for and stored to. This address is dependent on your | |
2123 | own flash usage. | |
2124 | ||
2125 | config KEXEC | |
2126 | bool "Kexec system call (EXPERIMENTAL)" | |
2127 | depends on (!SMP || PM_SLEEP_SMP) | |
2128 | help | |
2129 | kexec is a system call that implements the ability to shutdown your | |
2130 | current kernel, and to start another kernel. It is like a reboot | |
2131 | but it is independent of the system firmware. And like a reboot | |
2132 | you can start any kernel with it, not just Linux. | |
2133 | ||
2134 | It is an ongoing process to be certain the hardware in a machine | |
2135 | is properly shutdown, so do not be surprised if this code does not | |
2136 | initially work for you. | |
2137 | ||
2138 | config ATAGS_PROC | |
2139 | bool "Export atags in procfs" | |
2140 | depends on ATAGS && KEXEC | |
2141 | default y | |
2142 | help | |
2143 | Should the atags used to boot the kernel be exported in an "atags" | |
2144 | file in procfs. Useful with kexec. | |
2145 | ||
2146 | config CRASH_DUMP | |
2147 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
2148 | help | |
2149 | Generate crash dump after being started by kexec. This should | |
2150 | be normally only set in special crash dump kernels which are | |
2151 | loaded in the main kernel with kexec-tools into a specially | |
2152 | reserved region and then later executed after a crash by | |
2153 | kdump/kexec. The crash dump kernel must be compiled to a | |
2154 | memory address not used by the main kernel | |
2155 | ||
2156 | For more details see Documentation/kdump/kdump.txt | |
2157 | ||
2158 | config AUTO_ZRELADDR | |
2159 | bool "Auto calculation of the decompressed kernel image address" | |
2160 | help | |
2161 | ZRELADDR is the physical address where the decompressed kernel | |
2162 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2163 | will be determined at run-time by masking the current IP with | |
2164 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2165 | from start of memory. | |
2166 | ||
2167 | endmenu | |
2168 | ||
2169 | menu "CPU Power Management" | |
2170 | ||
2171 | if ARCH_HAS_CPUFREQ | |
2172 | source "drivers/cpufreq/Kconfig" | |
2173 | endif | |
2174 | ||
2175 | source "drivers/cpuidle/Kconfig" | |
2176 | ||
2177 | endmenu | |
2178 | ||
2179 | menu "Floating point emulation" | |
2180 | ||
2181 | comment "At least one emulation must be selected" | |
2182 | ||
2183 | config FPE_NWFPE | |
2184 | bool "NWFPE math emulation" | |
2185 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL | |
2186 | ---help--- | |
2187 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2188 | This is necessary to run most binaries. Linux does not currently | |
2189 | support floating point hardware so you need to say Y here even if | |
2190 | your machine has an FPA or floating point co-processor podule. | |
2191 | ||
2192 | You may say N here if you are going to load the Acorn FPEmulator | |
2193 | early in the bootup. | |
2194 | ||
2195 | config FPE_NWFPE_XP | |
2196 | bool "Support extended precision" | |
2197 | depends on FPE_NWFPE | |
2198 | help | |
2199 | Say Y to include 80-bit support in the kernel floating-point | |
2200 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2201 | Note that gcc does not generate 80-bit operations by default, | |
2202 | so in most cases this option only enlarges the size of the | |
2203 | floating point emulator without any good reason. | |
2204 | ||
2205 | You almost surely want to say N here. | |
2206 | ||
2207 | config FPE_FASTFPE | |
2208 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
2209 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 | |
2210 | ---help--- | |
2211 | Say Y here to include the FAST floating point emulator in the kernel. | |
2212 | This is an experimental much faster emulator which now also has full | |
2213 | precision for the mantissa. It does not support any exceptions. | |
2214 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2215 | ||
2216 | It should be sufficient for most programs. It may be not suitable | |
2217 | for scientific calculations, but you have to check this for yourself. | |
2218 | If you do not feel you need a faster FP emulation you should better | |
2219 | choose NWFPE. | |
2220 | ||
2221 | config VFP | |
2222 | bool "VFP-format floating point maths" | |
2223 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON | |
2224 | help | |
2225 | Say Y to include VFP support code in the kernel. This is needed | |
2226 | if your hardware includes a VFP unit. | |
2227 | ||
2228 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2229 | release notes and additional status information. | |
2230 | ||
2231 | Say N if your target does not have VFP hardware. | |
2232 | ||
2233 | config VFPv3 | |
2234 | bool | |
2235 | depends on VFP | |
2236 | default y if CPU_V7 | |
2237 | ||
2238 | config NEON | |
2239 | bool "Advanced SIMD (NEON) Extension support" | |
2240 | depends on VFPv3 && CPU_V7 | |
2241 | help | |
2242 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2243 | Extension. | |
2244 | ||
2245 | config KERNEL_MODE_NEON | |
2246 | bool "Support for NEON in kernel mode" | |
2247 | depends on NEON && AEABI | |
2248 | help | |
2249 | Say Y to include support for NEON in kernel mode. | |
2250 | ||
2251 | endmenu | |
2252 | ||
2253 | menu "Userspace binary formats" | |
2254 | ||
2255 | source "fs/Kconfig.binfmt" | |
2256 | ||
2257 | config ARTHUR | |
2258 | tristate "RISC OS personality" | |
2259 | depends on !AEABI | |
2260 | help | |
2261 | Say Y here to include the kernel code necessary if you want to run | |
2262 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2263 | experimental; if this sounds frightening, say N and sleep in peace. | |
2264 | You can also say M here to compile this support as a module (which | |
2265 | will be called arthur). | |
2266 | ||
2267 | endmenu | |
2268 | ||
2269 | menu "Power management options" | |
2270 | ||
2271 | source "kernel/power/Kconfig" | |
2272 | ||
2273 | config ARCH_SUSPEND_POSSIBLE | |
2274 | depends on !ARCH_S5PC100 | |
2275 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ | |
2276 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK | |
2277 | def_bool y | |
2278 | ||
2279 | config ARM_CPU_SUSPEND | |
2280 | def_bool PM_SLEEP | |
2281 | ||
2282 | endmenu | |
2283 | ||
2284 | source "net/Kconfig" | |
2285 | ||
2286 | source "drivers/Kconfig" | |
2287 | ||
2288 | source "fs/Kconfig" | |
2289 | ||
2290 | source "arch/arm/Kconfig.debug" | |
2291 | ||
2292 | source "security/Kconfig" | |
2293 | ||
2294 | source "crypto/Kconfig" | |
2295 | ||
2296 | source "lib/Kconfig" | |
2297 | ||
2298 | source "arch/arm/kvm/Kconfig" |