[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos5440.dtsi

/*
 * SAMSUNG EXYNOS5440 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <dt-bindings/clock/exynos5440.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "samsung,exynos5440", "samsung,exynos5";

	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial_0;
		serial1 = &serial_1;
		spi0 = &spi_0;
		tmuctrl0 = &tmuctrl_0;
		tmuctrl1 = &tmuctrl_1;
		tmuctrl2 = &tmuctrl_2;
	};

	clock: clock-controller@160000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@2E0000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg =	<0x2E1000 0x1000>,
			<0x2E2000 0x2000>,
			<0x2E4000 0x2000>,
			<0x2E6000 0x2000>;
		interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,cortex-a15-timer",
			     "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <50000000>;
	};

	cpufreq@160000 {
		compatible = "samsung,exynos5440-cpufreq";
		reg = <0x160000 0x1000>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		operating-points = <
				/* KHz	  uV */
				1500000 1100000
				1400000 1075000
				1300000 1050000
				1200000 1025000
				1100000 1000000
				1000000 975000
				900000  950000
				800000  925000
		>;
	};

	serial_0: serial@B0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xB0000 0x1000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial_1: serial@C0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xC0000 0x1000>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	spi_0: spi@D0000 {
		compatible = "samsung,exynos5440-spi";
		reg = <0xD0000 0x100>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		samsung,spi-src-clk = <0>;
		num-cs = <1>;
		clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
		clock-names = "spi", "spi_busclk0";
	};

	pin_ctrl: pinctrl@E0000 {
		compatible = "samsung,exynos5440-pinctrl";
		reg = <0xE0000 0x1000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#gpio-cells = <2>;

		fan: fan {
			samsung,exynos5440-pin-function = <1>;
		};

		hdd_led0: hdd_led0 {
			samsung,exynos5440-pin-function = <2>;
		};

		hdd_led1: hdd_led1 {
			samsung,exynos5440-pin-function = <3>;
		};

		uart1: uart1 {
			samsung,exynos5440-pin-function = <4>;
		};
	};

	i2c@F0000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0xF0000 0x1000>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	i2c@100000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0x100000 0x1000>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	watchdog@110000 {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x110000 0x1000>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "watchdog";
	};

	gmac: ethernet@00230000 {
		compatible = "snps,dwmac-3.70a", "snps,dwmac";
		reg = <0x00230000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 31 4>;
		interrupt-names = "macirq";
		phy-mode = "sgmii";
		clocks = <&clock CLK_GMAC0>;
		clock-names = "stmmaceth";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;
	};

	rtc@130000 {
		compatible = "samsung,s3c6410-rtc";
		reg = <0x130000 0x1000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "rtc";
	};

	tmuctrl_0: tmuctrl@160118 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160118 0x230>, <0x160368 0x10>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_1: tmuctrl@16011C {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x16011C 0x230>, <0x160368 0x10>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_2: tmuctrl@160120 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160120 0x230>, <0x160368 0x10>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	thermal-zones {
		cpu0_thermal: cpu0-thermal {
			thermal-sensors = <&tmuctrl_0>;
			#include "exynos5440-trip-points.dtsi"
		};
		cpu1_thermal: cpu1-thermal {
		       thermal-sensors = <&tmuctrl_1>;
		       #include "exynos5440-trip-points.dtsi"
		};
		cpu2_thermal: cpu2-thermal {
		       thermal-sensors = <&tmuctrl_2>;
		       #include "exynos5440-trip-points.dtsi"
		};
	};

	sata@210000 {
		compatible = "snps,exynos5440-ahci";
		reg = <0x210000 0x10000>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_SATA>;
		clock-names = "sata";
	};

	ohci@220000 {
		compatible = "samsung,exynos5440-ohci";
		reg = <0x220000 0x1000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	ehci@221000 {
		compatible = "samsung,exynos5440-ehci";
		reg = <0x221000 0x1000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	pcie_0: pcie@290000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x290000 0x1000
			0x270000 0x1000
			0x271000 0x40>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 53>;
		num-lanes = <4>;
		status = "disabled";
	};

	pcie_1: pcie@2a0000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x2a0000 0x1000
			0x272000 0x1000
			0x271040 0x40>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 56>;
		num-lanes = <4>;
		status = "disabled";
	};
};
Commit	Line	Data
	1	/*
	2	* SAMSUNG EXYNOS5440 SoC device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <dt-bindings/clock/exynos5440.h>
	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
	14	#include <dt-bindings/interrupt-controller/irq.h>
	15
	16	/ {
	17	compatible = "samsung,exynos5440", "samsung,exynos5";
	18
	19	interrupt-parent = <&gic>;
	20	#address-cells = <1>;
	21	#size-cells = <1>;
	22
	23	aliases {
	24	serial0 = &serial_0;
	25	serial1 = &serial_1;
	26	spi0 = &spi_0;
	27	tmuctrl0 = &tmuctrl_0;
	28	tmuctrl1 = &tmuctrl_1;
	29	tmuctrl2 = &tmuctrl_2;
	30	};
	31
	32	clock: clock-controller@160000 {
	33	compatible = "samsung,exynos5440-clock";
	34	reg = <0x160000 0x1000>;
	35	#clock-cells = <1>;
	36	};
	37
	38	gic: interrupt-controller@2E0000 {
	39	compatible = "arm,cortex-a15-gic";
	40	#interrupt-cells = <3>;
	41	interrupt-controller;
	42	reg = <0x2E1000 0x1000>,
	43	<0x2E2000 0x2000>,
	44	<0x2E4000 0x2000>,
	45	<0x2E6000 0x2000>;
	46	interrupts = <GIC_PPI 9
	47	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	48	};
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53
	54	cpu@0 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a15";
	57	reg = <0>;
	58	};
	59	cpu@1 {
	60	device_type = "cpu";
	61	compatible = "arm,cortex-a15";
	62	reg = <1>;
	63	};
	64	cpu@2 {
	65	device_type = "cpu";
	66	compatible = "arm,cortex-a15";
	67	reg = <2>;
	68	};
	69	cpu@3 {
	70	device_type = "cpu";
	71	compatible = "arm,cortex-a15";
	72	reg = <3>;
	73	};
	74	};
	75
	76	arm-pmu {
	77	compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
	78	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	80	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	81	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	82	};
	83
	84	timer {
	85	compatible = "arm,cortex-a15-timer",
	86	"arm,armv7-timer";
	87	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	88	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	89	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	90	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	91	clock-frequency = <50000000>;
	92	};
	93
	94	cpufreq@160000 {
	95	compatible = "samsung,exynos5440-cpufreq";
	96	reg = <0x160000 0x1000>;
	97	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	98	operating-points = <
	99	/* KHz uV */
	100	1500000 1100000
	101	1400000 1075000
	102	1300000 1050000
	103	1200000 1025000
	104	1100000 1000000
	105	1000000 975000
	106	900000 950000
	107	800000 925000
	108	>;
	109	};
	110
	111	serial_0: serial@B0000 {
	112	compatible = "samsung,exynos4210-uart";
	113	reg = <0xB0000 0x1000>;
	114	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	115	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
	116	clock-names = "uart", "clk_uart_baud0";
	117	};
	118
	119	serial_1: serial@C0000 {
	120	compatible = "samsung,exynos4210-uart";
	121	reg = <0xC0000 0x1000>;
	122	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	123	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
	124	clock-names = "uart", "clk_uart_baud0";
	125	};
	126
	127	spi_0: spi@D0000 {
	128	compatible = "samsung,exynos5440-spi";
	129	reg = <0xD0000 0x100>;
	130	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	131	#address-cells = <1>;
	132	#size-cells = <0>;
	133	samsung,spi-src-clk = <0>;
	134	num-cs = <1>;
	135	clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
	136	clock-names = "spi", "spi_busclk0";
	137	};
	138
	139	pin_ctrl: pinctrl@E0000 {
	140	compatible = "samsung,exynos5440-pinctrl";
	141	reg = <0xE0000 0x1000>;
	142	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	143	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	144	<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	145	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	146	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	147	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	148	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	149	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	150	interrupt-controller;
	151	#interrupt-cells = <2>;
	152	#gpio-cells = <2>;
	153
	154	fan: fan {
	155	samsung,exynos5440-pin-function = <1>;
	156	};
	157
	158	hdd_led0: hdd_led0 {
	159	samsung,exynos5440-pin-function = <2>;
	160	};
	161
	162	hdd_led1: hdd_led1 {
	163	samsung,exynos5440-pin-function = <3>;
	164	};
	165
	166	uart1: uart1 {
	167	samsung,exynos5440-pin-function = <4>;
	168	};
	169	};
	170
	171	i2c@F0000 {
	172	compatible = "samsung,exynos5440-i2c";
	173	reg = <0xF0000 0x1000>;
	174	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	clocks = <&clock CLK_B_125>;
	178	clock-names = "i2c";
	179	};
	180
	181	i2c@100000 {
	182	compatible = "samsung,exynos5440-i2c";
	183	reg = <0x100000 0x1000>;
	184	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	clocks = <&clock CLK_B_125>;
	188	clock-names = "i2c";
	189	};
	190
	191	watchdog@110000 {
	192	compatible = "samsung,s3c2410-wdt";
	193	reg = <0x110000 0x1000>;
	194	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	195	clocks = <&clock CLK_B_125>;
	196	clock-names = "watchdog";
	197	};
	198
	199	gmac: ethernet@00230000 {
	200	compatible = "snps,dwmac-3.70a", "snps,dwmac";
	201	reg = <0x00230000 0x8000>;
	202	interrupt-parent = <&gic>;
	203	interrupts = <GIC_SPI 31 4>;
	204	interrupt-names = "macirq";
	205	phy-mode = "sgmii";
	206	clocks = <&clock CLK_GMAC0>;
	207	clock-names = "stmmaceth";
	208	};
	209
	210	amba {
	211	#address-cells = <1>;
	212	#size-cells = <1>;
	213	compatible = "simple-bus";
	214	interrupt-parent = <&gic>;
	215	ranges;
	216	};
	217
	218	rtc@130000 {
	219	compatible = "samsung,s3c6410-rtc";
	220	reg = <0x130000 0x1000>;
	221	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	222	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	223	clocks = <&clock CLK_B_125>;
	224	clock-names = "rtc";
	225	};
	226
	227	tmuctrl_0: tmuctrl@160118 {
	228	compatible = "samsung,exynos5440-tmu";
	229	reg = <0x160118 0x230>, <0x160368 0x10>;
	230	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	231	clocks = <&clock CLK_B_125>;
	232	clock-names = "tmu_apbif";
	233	#include "exynos5440-tmu-sensor-conf.dtsi"
	234	};
	235
	236	tmuctrl_1: tmuctrl@16011C {
	237	compatible = "samsung,exynos5440-tmu";
	238	reg = <0x16011C 0x230>, <0x160368 0x10>;
	239	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	240	clocks = <&clock CLK_B_125>;
	241	clock-names = "tmu_apbif";
	242	#include "exynos5440-tmu-sensor-conf.dtsi"
	243	};
	244
	245	tmuctrl_2: tmuctrl@160120 {
	246	compatible = "samsung,exynos5440-tmu";
	247	reg = <0x160120 0x230>, <0x160368 0x10>;
	248	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	249	clocks = <&clock CLK_B_125>;
	250	clock-names = "tmu_apbif";
	251	#include "exynos5440-tmu-sensor-conf.dtsi"
	252	};
	253
	254	thermal-zones {
	255	cpu0_thermal: cpu0-thermal {
	256	thermal-sensors = <&tmuctrl_0>;
	257	#include "exynos5440-trip-points.dtsi"
	258	};
	259	cpu1_thermal: cpu1-thermal {
	260	thermal-sensors = <&tmuctrl_1>;
	261	#include "exynos5440-trip-points.dtsi"
	262	};
	263	cpu2_thermal: cpu2-thermal {
	264	thermal-sensors = <&tmuctrl_2>;
	265	#include "exynos5440-trip-points.dtsi"
	266	};
	267	};
	268
	269	sata@210000 {
	270	compatible = "snps,exynos5440-ahci";
	271	reg = <0x210000 0x10000>;
	272	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	273	clocks = <&clock CLK_SATA>;
	274	clock-names = "sata";
	275	};
	276
	277	ohci@220000 {
	278	compatible = "samsung,exynos5440-ohci";
	279	reg = <0x220000 0x1000>;
	280	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	281	clocks = <&clock CLK_USB>;
	282	clock-names = "usbhost";
	283	};
	284
	285	ehci@221000 {
	286	compatible = "samsung,exynos5440-ehci";
	287	reg = <0x221000 0x1000>;
	288	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	289	clocks = <&clock CLK_USB>;
	290	clock-names = "usbhost";
	291	};
	292
	293	pcie_0: pcie@290000 {
	294	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	295	reg = <0x290000 0x1000
	296	0x270000 0x1000
	297	0x271000 0x40>;
	298	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	299	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	300	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	301	clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
	302	clock-names = "pcie", "pcie_bus";
	303	#address-cells = <3>;
	304	#size-cells = <2>;
	305	device_type = "pci";
	306	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
	307	0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
	308	0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
	309	#interrupt-cells = <1>;
	310	interrupt-map-mask = <0 0 0 0>;
	311	interrupt-map = <0x0 0 &gic 53>;
	312	num-lanes = <4>;
	313	status = "disabled";
	314	};
	315
	316	pcie_1: pcie@2a0000 {
	317	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	318	reg = <0x2a0000 0x1000
	319	0x272000 0x1000
	320	0x271040 0x40>;
	321	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	322	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	324	clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
	325	clock-names = "pcie", "pcie_bus";
	326	#address-cells = <3>;
	327	#size-cells = <2>;
	328	device_type = "pci";
	329	ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
	330	0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
	331	0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
	332	#interrupt-cells = <1>;
	333	interrupt-map-mask = <0 0 0 0>;
	334	interrupt-map = <0x0 0 &gic 56>;
	335	num-lanes = <4>;
	336	status = "disabled";
	337	};
	338	};