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1 | /* | |
2 | * Copyright 2014 Iain Paton <ipaton0@gmail.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | #include "imx6dl.dtsi" | |
12 | #include <dt-bindings/gpio/gpio.h> | |
13 | ||
14 | / { | |
15 | model = "RIoTboard i.MX6S"; | |
16 | compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; | |
17 | ||
18 | memory { | |
19 | reg = <0x10000000 0x40000000>; | |
20 | }; | |
21 | ||
22 | regulators { | |
23 | compatible = "simple-bus"; | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | ||
27 | reg_2p5v: regulator@0 { | |
28 | compatible = "regulator-fixed"; | |
29 | reg = <0>; | |
30 | regulator-name = "2P5V"; | |
31 | regulator-min-microvolt = <2500000>; | |
32 | regulator-max-microvolt = <2500000>; | |
33 | }; | |
34 | ||
35 | reg_3p3v: regulator@1 { | |
36 | compatible = "regulator-fixed"; | |
37 | reg = <1>; | |
38 | regulator-name = "3P3V"; | |
39 | regulator-min-microvolt = <3300000>; | |
40 | regulator-max-microvolt = <3300000>; | |
41 | }; | |
42 | ||
43 | reg_usb_otg_vbus: regulator@2 { | |
44 | compatible = "regulator-fixed"; | |
45 | reg = <2>; | |
46 | regulator-name = "usb_otg_vbus"; | |
47 | regulator-min-microvolt = <5000000>; | |
48 | regulator-max-microvolt = <5000000>; | |
49 | gpio = <&gpio3 22 0>; | |
50 | enable-active-high; | |
51 | }; | |
52 | }; | |
53 | ||
54 | leds { | |
55 | compatible = "gpio-leds"; | |
56 | pinctrl-names = "default"; | |
57 | pinctrl-0 = <&pinctrl_led>; | |
58 | ||
59 | led0: user1 { | |
60 | label = "user1"; | |
61 | gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; | |
62 | default-state = "on"; | |
63 | linux,default-trigger = "heartbeat"; | |
64 | }; | |
65 | ||
66 | led1: user2 { | |
67 | label = "user2"; | |
68 | gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; | |
69 | default-state = "off"; | |
70 | }; | |
71 | }; | |
72 | ||
73 | sound { | |
74 | compatible = "fsl,imx-audio-sgtl5000"; | |
75 | model = "imx6-riotboard-sgtl5000"; | |
76 | ssi-controller = <&ssi1>; | |
77 | audio-codec = <&codec>; | |
78 | audio-routing = | |
79 | "MIC_IN", "Mic Jack", | |
80 | "Mic Jack", "Mic Bias", | |
81 | "Headphone Jack", "HP_OUT"; | |
82 | mux-int-port = <1>; | |
83 | mux-ext-port = <3>; | |
84 | }; | |
85 | }; | |
86 | ||
87 | &audmux { | |
88 | pinctrl-names = "default"; | |
89 | pinctrl-0 = <&pinctrl_audmux>; | |
90 | status = "okay"; | |
91 | }; | |
92 | ||
93 | &fec { | |
94 | pinctrl-names = "default"; | |
95 | pinctrl-0 = <&pinctrl_enet>; | |
96 | phy-mode = "rgmii"; | |
97 | phy-reset-gpios = <&gpio3 31 0>; | |
98 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
100 | status = "okay"; | |
101 | }; | |
102 | ||
103 | &hdmi { | |
104 | ddc-i2c-bus = <&i2c2>; | |
105 | status = "okay"; | |
106 | }; | |
107 | ||
108 | &i2c1 { | |
109 | clock-frequency = <100000>; | |
110 | pinctrl-names = "default"; | |
111 | pinctrl-0 = <&pinctrl_i2c1>; | |
112 | status = "okay"; | |
113 | ||
114 | codec: sgtl5000@0a { | |
115 | compatible = "fsl,sgtl5000"; | |
116 | reg = <0x0a>; | |
117 | clocks = <&clks 201>; | |
118 | VDDA-supply = <®_2p5v>; | |
119 | VDDIO-supply = <®_3p3v>; | |
120 | }; | |
121 | ||
122 | pmic: pf0100@08 { | |
123 | compatible = "fsl,pfuze100"; | |
124 | reg = <0x08>; | |
125 | interrupt-parent = <&gpio5>; | |
126 | interrupts = <16 8>; | |
127 | ||
128 | regulators { | |
129 | reg_vddcore: sw1ab { /* VDDARM_IN */ | |
130 | regulator-min-microvolt = <300000>; | |
131 | regulator-max-microvolt = <1875000>; | |
132 | regulator-always-on; | |
133 | }; | |
134 | ||
135 | reg_vddsoc: sw1c { /* VDDSOC_IN */ | |
136 | regulator-min-microvolt = <300000>; | |
137 | regulator-max-microvolt = <1875000>; | |
138 | regulator-always-on; | |
139 | }; | |
140 | ||
141 | reg_gen_3v3: sw2 { /* VDDHIGH_IN */ | |
142 | regulator-min-microvolt = <800000>; | |
143 | regulator-max-microvolt = <3300000>; | |
144 | regulator-always-on; | |
145 | }; | |
146 | ||
147 | reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ | |
148 | regulator-min-microvolt = <400000>; | |
149 | regulator-max-microvolt = <1975000>; | |
150 | regulator-always-on; | |
151 | }; | |
152 | ||
153 | reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ | |
154 | regulator-min-microvolt = <400000>; | |
155 | regulator-max-microvolt = <1975000>; | |
156 | regulator-always-on; | |
157 | }; | |
158 | ||
159 | reg_ddr_vtt: sw4 { /* MIPI conn */ | |
160 | regulator-min-microvolt = <400000>; | |
161 | regulator-max-microvolt = <1975000>; | |
162 | regulator-always-on; | |
163 | }; | |
164 | ||
165 | reg_5v_600mA: swbst { /* not used */ | |
166 | regulator-min-microvolt = <5000000>; | |
167 | regulator-max-microvolt = <5150000>; | |
168 | }; | |
169 | ||
170 | reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ | |
171 | regulator-min-microvolt = <1500000>; | |
172 | regulator-max-microvolt = <3000000>; | |
173 | regulator-always-on; | |
174 | }; | |
175 | ||
176 | vref_reg: vrefddr { /* VREF_DDR */ | |
177 | regulator-boot-on; | |
178 | regulator-always-on; | |
179 | }; | |
180 | ||
181 | reg_vgen1_1v5: vgen1 { /* not used */ | |
182 | regulator-min-microvolt = <800000>; | |
183 | regulator-max-microvolt = <1550000>; | |
184 | }; | |
185 | ||
186 | reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ | |
187 | regulator-min-microvolt = <800000>; | |
188 | regulator-max-microvolt = <1550000>; | |
189 | regulator-always-on; | |
190 | }; | |
191 | ||
192 | reg_vgen3_2v8: vgen3 { /* not used */ | |
193 | regulator-min-microvolt = <1800000>; | |
194 | regulator-max-microvolt = <3300000>; | |
195 | }; | |
196 | reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ | |
197 | regulator-min-microvolt = <1800000>; | |
198 | regulator-max-microvolt = <3300000>; | |
199 | regulator-always-on; | |
200 | }; | |
201 | ||
202 | reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ | |
203 | regulator-min-microvolt = <1800000>; | |
204 | regulator-max-microvolt = <3300000>; | |
205 | regulator-always-on; | |
206 | }; | |
207 | ||
208 | reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ | |
209 | regulator-min-microvolt = <1800000>; | |
210 | regulator-max-microvolt = <3300000>; | |
211 | regulator-always-on; | |
212 | }; | |
213 | }; | |
214 | }; | |
215 | }; | |
216 | ||
217 | &i2c2 { | |
218 | clock-frequency = <100000>; | |
219 | pinctrl-names = "default"; | |
220 | pinctrl-0 = <&pinctrl_i2c2>; | |
221 | status = "okay"; | |
222 | }; | |
223 | ||
224 | &i2c4 { | |
225 | clock-frequency = <100000>; | |
226 | pinctrl-names = "default"; | |
227 | pinctrl-0 = <&pinctrl_i2c4>; | |
228 | clocks = <&clks 116>; | |
229 | status = "okay"; | |
230 | }; | |
231 | ||
232 | &pwm1 { | |
233 | pinctrl-names = "default"; | |
234 | pinctrl-0 = <&pinctrl_pwm1>; | |
235 | status = "okay"; | |
236 | }; | |
237 | ||
238 | &pwm2 { | |
239 | pinctrl-names = "default"; | |
240 | pinctrl-0 = <&pinctrl_pwm2>; | |
241 | status = "okay"; | |
242 | }; | |
243 | ||
244 | &pwm3 { | |
245 | pinctrl-names = "default"; | |
246 | pinctrl-0 = <&pinctrl_pwm3>; | |
247 | status = "okay"; | |
248 | }; | |
249 | ||
250 | &pwm4 { | |
251 | pinctrl-names = "default"; | |
252 | pinctrl-0 = <&pinctrl_pwm4>; | |
253 | status = "okay"; | |
254 | }; | |
255 | ||
256 | &ssi1 { | |
257 | status = "okay"; | |
258 | }; | |
259 | ||
260 | &uart1 { | |
261 | pinctrl-names = "default"; | |
262 | pinctrl-0 = <&pinctrl_uart1>; | |
263 | status = "okay"; | |
264 | }; | |
265 | ||
266 | &uart2 { | |
267 | pinctrl-names = "default"; | |
268 | pinctrl-0 = <&pinctrl_uart2>; | |
269 | status = "okay"; | |
270 | }; | |
271 | ||
272 | &uart3 { | |
273 | pinctrl-names = "default"; | |
274 | pinctrl-0 = <&pinctrl_uart3>; | |
275 | status = "okay"; | |
276 | }; | |
277 | ||
278 | &uart4 { | |
279 | pinctrl-names = "default"; | |
280 | pinctrl-0 = <&pinctrl_uart4>; | |
281 | status = "okay"; | |
282 | }; | |
283 | ||
284 | &uart5 { | |
285 | pinctrl-names = "default"; | |
286 | pinctrl-0 = <&pinctrl_uart5>; | |
287 | status = "okay"; | |
288 | }; | |
289 | ||
290 | &usbh1 { | |
291 | dr_mode = "host"; | |
292 | disable-over-current; | |
293 | status = "okay"; | |
294 | }; | |
295 | ||
296 | &usbotg { | |
297 | vbus-supply = <®_usb_otg_vbus>; | |
298 | pinctrl-names = "default"; | |
299 | pinctrl-0 = <&pinctrl_usbotg>; | |
300 | disable-over-current; | |
301 | dr_mode = "otg"; | |
302 | status = "okay"; | |
303 | }; | |
304 | ||
305 | &usdhc2 { | |
306 | pinctrl-names = "default"; | |
307 | pinctrl-0 = <&pinctrl_usdhc2>; | |
308 | cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | |
309 | wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
310 | vmmc-supply = <®_3p3v>; | |
311 | status = "okay"; | |
312 | }; | |
313 | ||
314 | &usdhc3 { | |
315 | pinctrl-names = "default"; | |
316 | pinctrl-0 = <&pinctrl_usdhc3>; | |
317 | cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; | |
318 | wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; | |
319 | vmmc-supply = <®_3p3v>; | |
320 | status = "okay"; | |
321 | }; | |
322 | ||
323 | &usdhc4 { | |
324 | pinctrl-names = "default"; | |
325 | pinctrl-0 = <&pinctrl_usdhc4>; | |
326 | vmmc-supply = <®_3p3v>; | |
327 | non-removable; | |
328 | status = "okay"; | |
329 | }; | |
330 | ||
331 | &iomuxc { | |
332 | pinctrl-names = "default"; | |
333 | ||
334 | imx6-riotboard { | |
335 | pinctrl_audmux: audmuxgrp { | |
336 | fsl,pins = < | |
337 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | |
338 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | |
339 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | |
340 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | |
341 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ | |
342 | >; | |
343 | }; | |
344 | ||
345 | pinctrl_ecspi1: ecspi1grp { | |
346 | fsl,pins = < | |
347 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | |
348 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | |
349 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | |
350 | MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ | |
351 | >; | |
352 | }; | |
353 | ||
354 | pinctrl_ecspi2: ecspi2grp { | |
355 | fsl,pins = < | |
356 | MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ | |
357 | MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 | |
358 | MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 | |
359 | MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ | |
360 | MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 | |
361 | >; | |
362 | }; | |
363 | ||
364 | pinctrl_ecspi3: ecspi3grp { | |
365 | fsl,pins = < | |
366 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | |
367 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | |
368 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | |
369 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ | |
370 | MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ | |
371 | >; | |
372 | }; | |
373 | ||
374 | pinctrl_enet: enetgrp { | |
375 | fsl,pins = < | |
376 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
377 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
378 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
379 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
380 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
381 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
382 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
383 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
384 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ | |
385 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ | |
386 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ | |
387 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ | |
388 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ | |
389 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ | |
390 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ | |
391 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ | |
392 | MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ | |
393 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ | |
394 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | |
395 | >; | |
396 | }; | |
397 | ||
398 | pinctrl_i2c1: i2c1grp { | |
399 | fsl,pins = < | |
400 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | |
401 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | |
402 | >; | |
403 | }; | |
404 | ||
405 | pinctrl_i2c2: i2c2grp { | |
406 | fsl,pins = < | |
407 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | |
408 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
409 | >; | |
410 | }; | |
411 | ||
412 | pinctrl_i2c3: i2c3grp { | |
413 | fsl,pins = < | |
414 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | |
415 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | |
416 | >; | |
417 | }; | |
418 | ||
419 | pinctrl_i2c4: i2c4grp { | |
420 | fsl,pins = < | |
421 | MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 | |
422 | MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 | |
423 | >; | |
424 | }; | |
425 | ||
426 | pinctrl_led: ledgrp { | |
427 | fsl,pins = < | |
428 | MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ | |
429 | MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ | |
430 | >; | |
431 | }; | |
432 | ||
433 | pinctrl_pwm1: pwm1grp { | |
434 | fsl,pins = < | |
435 | MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 | |
436 | >; | |
437 | }; | |
438 | ||
439 | pinctrl_pwm2: pwm2grp { | |
440 | fsl,pins = < | |
441 | MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 | |
442 | >; | |
443 | }; | |
444 | ||
445 | pinctrl_pwm3: pwm3grp { | |
446 | fsl,pins = < | |
447 | MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 | |
448 | >; | |
449 | }; | |
450 | ||
451 | pinctrl_pwm4: pwm4grp { | |
452 | fsl,pins = < | |
453 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | |
454 | >; | |
455 | }; | |
456 | ||
457 | pinctrl_uart1: uart1grp { | |
458 | fsl,pins = < | |
459 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | |
460 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | |
461 | >; | |
462 | }; | |
463 | ||
464 | pinctrl_uart2: uart2grp { | |
465 | fsl,pins = < | |
466 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | |
467 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | |
468 | >; | |
469 | }; | |
470 | ||
471 | pinctrl_uart3: uart3grp { | |
472 | fsl,pins = < | |
473 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |
474 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |
475 | >; | |
476 | }; | |
477 | ||
478 | pinctrl_uart4: uart4grp { | |
479 | fsl,pins = < | |
480 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |
481 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | |
482 | >; | |
483 | }; | |
484 | ||
485 | pinctrl_uart5: uart5grp { | |
486 | fsl,pins = < | |
487 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | |
488 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | |
489 | >; | |
490 | }; | |
491 | ||
492 | pinctrl_usbotg: usbotggrp { | |
493 | fsl,pins = < | |
494 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | |
495 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ | |
496 | MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 | |
497 | >; | |
498 | }; | |
499 | ||
500 | pinctrl_usdhc2: usdhc2grp { | |
501 | fsl,pins = < | |
502 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
503 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
504 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
505 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
506 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
507 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
508 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ | |
509 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ | |
510 | >; | |
511 | }; | |
512 | ||
513 | pinctrl_usdhc3: usdhc3grp { | |
514 | fsl,pins = < | |
515 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
516 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
517 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
518 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
519 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
520 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
521 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ | |
522 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ | |
523 | >; | |
524 | }; | |
525 | ||
526 | pinctrl_usdhc4: usdhc4grp { | |
527 | fsl,pins = < | |
528 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
529 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
530 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
531 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
532 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
533 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
534 | MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ | |
535 | >; | |
536 | }; | |
537 | }; | |
538 | }; |