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1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
2 | /* | |
3 | * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC | |
4 | * | |
5 | * Copyright (C) 2015 Atmel, | |
6 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/dma/at91.h> | |
10 | #include <dt-bindings/interrupt-controller/irq.h> | |
11 | #include <dt-bindings/clock/at91.h> | |
12 | #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> | |
13 | ||
14 | / { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | model = "Atmel SAMA5D2 family SoC"; | |
18 | compatible = "atmel,sama5d2"; | |
19 | interrupt-parent = <&aic>; | |
20 | ||
21 | aliases { | |
22 | serial0 = &uart1; | |
23 | serial1 = &uart3; | |
24 | tcb0 = &tcb0; | |
25 | tcb1 = &tcb1; | |
26 | i2s0 = &i2s0; | |
27 | i2s1 = &i2s1; | |
28 | }; | |
29 | ||
30 | cpus { | |
31 | #address-cells = <1>; | |
32 | #size-cells = <0>; | |
33 | ||
34 | cpu@0 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a5"; | |
37 | reg = <0>; | |
38 | next-level-cache = <&L2>; | |
39 | }; | |
40 | }; | |
41 | ||
42 | pmu { | |
43 | compatible = "arm,cortex-a5-pmu"; | |
44 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; | |
45 | }; | |
46 | ||
47 | etb { | |
48 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
49 | reg = <0x740000 0x1000>; | |
50 | ||
51 | clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; | |
52 | clock-names = "apb_pclk"; | |
53 | ||
54 | in-ports { | |
55 | port { | |
56 | etb_in: endpoint { | |
57 | remote-endpoint = <&etm_out>; | |
58 | }; | |
59 | }; | |
60 | }; | |
61 | }; | |
62 | ||
63 | etm { | |
64 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
65 | reg = <0x73C000 0x1000>; | |
66 | ||
67 | clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; | |
68 | clock-names = "apb_pclk"; | |
69 | ||
70 | out-ports { | |
71 | port { | |
72 | etm_out: endpoint { | |
73 | remote-endpoint = <&etb_in>; | |
74 | }; | |
75 | }; | |
76 | }; | |
77 | }; | |
78 | ||
79 | memory { | |
80 | device_type = "memory"; | |
81 | reg = <0x20000000 0x20000000>; | |
82 | }; | |
83 | ||
84 | clocks { | |
85 | slow_xtal: slow_xtal { | |
86 | compatible = "fixed-clock"; | |
87 | #clock-cells = <0>; | |
88 | clock-frequency = <0>; | |
89 | }; | |
90 | ||
91 | main_xtal: main_xtal { | |
92 | compatible = "fixed-clock"; | |
93 | #clock-cells = <0>; | |
94 | clock-frequency = <0>; | |
95 | }; | |
96 | }; | |
97 | ||
98 | ns_sram: sram@200000 { | |
99 | compatible = "mmio-sram"; | |
100 | reg = <0x00200000 0x20000>; | |
101 | }; | |
102 | ||
103 | ahb { | |
104 | compatible = "simple-bus"; | |
105 | #address-cells = <1>; | |
106 | #size-cells = <1>; | |
107 | ranges; | |
108 | ||
109 | nfc_sram: sram@100000 { | |
110 | compatible = "mmio-sram"; | |
111 | no-memory-wc; | |
112 | reg = <0x00100000 0x2400>; | |
113 | }; | |
114 | ||
115 | usb0: gadget@300000 { | |
116 | #address-cells = <1>; | |
117 | #size-cells = <0>; | |
118 | compatible = "atmel,sama5d3-udc"; | |
119 | reg = <0x00300000 0x100000 | |
120 | 0xfc02c000 0x400>; | |
121 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; | |
122 | clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; | |
123 | clock-names = "pclk", "hclk"; | |
124 | status = "disabled"; | |
125 | ||
126 | ep@0 { | |
127 | reg = <0>; | |
128 | atmel,fifo-size = <64>; | |
129 | atmel,nb-banks = <1>; | |
130 | }; | |
131 | ||
132 | ep@1 { | |
133 | reg = <1>; | |
134 | atmel,fifo-size = <1024>; | |
135 | atmel,nb-banks = <3>; | |
136 | atmel,can-dma; | |
137 | atmel,can-isoc; | |
138 | }; | |
139 | ||
140 | ep@2 { | |
141 | reg = <2>; | |
142 | atmel,fifo-size = <1024>; | |
143 | atmel,nb-banks = <3>; | |
144 | atmel,can-dma; | |
145 | atmel,can-isoc; | |
146 | }; | |
147 | ||
148 | ep@3 { | |
149 | reg = <3>; | |
150 | atmel,fifo-size = <1024>; | |
151 | atmel,nb-banks = <2>; | |
152 | atmel,can-dma; | |
153 | atmel,can-isoc; | |
154 | }; | |
155 | ||
156 | ep@4 { | |
157 | reg = <4>; | |
158 | atmel,fifo-size = <1024>; | |
159 | atmel,nb-banks = <2>; | |
160 | atmel,can-dma; | |
161 | atmel,can-isoc; | |
162 | }; | |
163 | ||
164 | ep@5 { | |
165 | reg = <5>; | |
166 | atmel,fifo-size = <1024>; | |
167 | atmel,nb-banks = <2>; | |
168 | atmel,can-dma; | |
169 | atmel,can-isoc; | |
170 | }; | |
171 | ||
172 | ep@6 { | |
173 | reg = <6>; | |
174 | atmel,fifo-size = <1024>; | |
175 | atmel,nb-banks = <2>; | |
176 | atmel,can-dma; | |
177 | atmel,can-isoc; | |
178 | }; | |
179 | ||
180 | ep@7 { | |
181 | reg = <7>; | |
182 | atmel,fifo-size = <1024>; | |
183 | atmel,nb-banks = <2>; | |
184 | atmel,can-dma; | |
185 | atmel,can-isoc; | |
186 | }; | |
187 | ||
188 | ep@8 { | |
189 | reg = <8>; | |
190 | atmel,fifo-size = <1024>; | |
191 | atmel,nb-banks = <2>; | |
192 | atmel,can-isoc; | |
193 | }; | |
194 | ||
195 | ep@9 { | |
196 | reg = <9>; | |
197 | atmel,fifo-size = <1024>; | |
198 | atmel,nb-banks = <2>; | |
199 | atmel,can-isoc; | |
200 | }; | |
201 | ||
202 | ep@10 { | |
203 | reg = <10>; | |
204 | atmel,fifo-size = <1024>; | |
205 | atmel,nb-banks = <2>; | |
206 | atmel,can-isoc; | |
207 | }; | |
208 | ||
209 | ep@11 { | |
210 | reg = <11>; | |
211 | atmel,fifo-size = <1024>; | |
212 | atmel,nb-banks = <2>; | |
213 | atmel,can-isoc; | |
214 | }; | |
215 | ||
216 | ep@12 { | |
217 | reg = <12>; | |
218 | atmel,fifo-size = <1024>; | |
219 | atmel,nb-banks = <2>; | |
220 | atmel,can-isoc; | |
221 | }; | |
222 | ||
223 | ep@13 { | |
224 | reg = <13>; | |
225 | atmel,fifo-size = <1024>; | |
226 | atmel,nb-banks = <2>; | |
227 | atmel,can-isoc; | |
228 | }; | |
229 | ||
230 | ep@14 { | |
231 | reg = <14>; | |
232 | atmel,fifo-size = <1024>; | |
233 | atmel,nb-banks = <2>; | |
234 | atmel,can-isoc; | |
235 | }; | |
236 | ||
237 | ep@15 { | |
238 | reg = <15>; | |
239 | atmel,fifo-size = <1024>; | |
240 | atmel,nb-banks = <2>; | |
241 | atmel,can-isoc; | |
242 | }; | |
243 | }; | |
244 | ||
245 | usb1: ohci@400000 { | |
246 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
247 | reg = <0x00400000 0x100000>; | |
248 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
249 | clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; | |
250 | clock-names = "ohci_clk", "hclk", "uhpck"; | |
251 | status = "disabled"; | |
252 | }; | |
253 | ||
254 | usb2: ehci@500000 { | |
255 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
256 | reg = <0x00500000 0x100000>; | |
257 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
258 | clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; | |
259 | clock-names = "usb_clk", "ehci_clk"; | |
260 | status = "disabled"; | |
261 | }; | |
262 | ||
263 | L2: cache-controller@a00000 { | |
264 | compatible = "arm,pl310-cache"; | |
265 | reg = <0x00a00000 0x1000>; | |
266 | interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; | |
267 | cache-unified; | |
268 | cache-level = <2>; | |
269 | }; | |
270 | ||
271 | ebi: ebi@10000000 { | |
272 | compatible = "atmel,sama5d3-ebi"; | |
273 | #address-cells = <2>; | |
274 | #size-cells = <1>; | |
275 | atmel,smc = <&hsmc>; | |
276 | reg = <0x10000000 0x10000000 | |
277 | 0x60000000 0x30000000>; | |
278 | ranges = <0x0 0x0 0x10000000 0x10000000 | |
279 | 0x1 0x0 0x60000000 0x10000000 | |
280 | 0x2 0x0 0x70000000 0x10000000 | |
281 | 0x3 0x0 0x80000000 0x10000000>; | |
282 | clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; | |
283 | status = "disabled"; | |
284 | ||
285 | nand_controller: nand-controller { | |
286 | compatible = "atmel,sama5d3-nand-controller"; | |
287 | atmel,nfc-sram = <&nfc_sram>; | |
288 | atmel,nfc-io = <&nfc_io>; | |
289 | ecc-engine = <&pmecc>; | |
290 | #address-cells = <2>; | |
291 | #size-cells = <1>; | |
292 | ranges; | |
293 | status = "disabled"; | |
294 | }; | |
295 | }; | |
296 | ||
297 | sdmmc0: sdio-host@a0000000 { | |
298 | compatible = "atmel,sama5d2-sdhci"; | |
299 | reg = <0xa0000000 0x300>; | |
300 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; | |
301 | clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; | |
302 | clock-names = "hclock", "multclk", "baseclk"; | |
303 | status = "disabled"; | |
304 | }; | |
305 | ||
306 | sdmmc1: sdio-host@b0000000 { | |
307 | compatible = "atmel,sama5d2-sdhci"; | |
308 | reg = <0xb0000000 0x300>; | |
309 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; | |
310 | clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; | |
311 | clock-names = "hclock", "multclk", "baseclk"; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | nfc_io: nfc-io@c0000000 { | |
316 | compatible = "atmel,sama5d3-nfc-io", "syscon"; | |
317 | reg = <0xc0000000 0x8000000>; | |
318 | }; | |
319 | ||
320 | apb { | |
321 | compatible = "simple-bus"; | |
322 | #address-cells = <1>; | |
323 | #size-cells = <1>; | |
324 | ranges; | |
325 | ||
326 | hlcdc: hlcdc@f0000000 { | |
327 | compatible = "atmel,sama5d2-hlcdc"; | |
328 | reg = <0xf0000000 0x2000>; | |
329 | interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; | |
330 | clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; | |
331 | clock-names = "periph_clk","sys_clk", "slow_clk"; | |
332 | status = "disabled"; | |
333 | ||
334 | hlcdc-display-controller { | |
335 | compatible = "atmel,hlcdc-display-controller"; | |
336 | #address-cells = <1>; | |
337 | #size-cells = <0>; | |
338 | ||
339 | port@0 { | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | reg = <0>; | |
343 | }; | |
344 | }; | |
345 | ||
346 | hlcdc_pwm: hlcdc-pwm { | |
347 | compatible = "atmel,hlcdc-pwm"; | |
348 | #pwm-cells = <3>; | |
349 | }; | |
350 | }; | |
351 | ||
352 | isc: isc@f0008000 { | |
353 | compatible = "atmel,sama5d2-isc"; | |
354 | reg = <0xf0008000 0x4000>; | |
355 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; | |
356 | clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; | |
357 | clock-names = "hclock", "iscck", "gck"; | |
358 | #clock-cells = <0>; | |
359 | clock-output-names = "isc-mck"; | |
360 | status = "disabled"; | |
361 | }; | |
362 | ||
363 | ramc0: ramc@f000c000 { | |
364 | compatible = "atmel,sama5d3-ddramc"; | |
365 | reg = <0xf000c000 0x200>; | |
366 | clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; | |
367 | clock-names = "ddrck", "mpddr"; | |
368 | }; | |
369 | ||
370 | dma0: dma-controller@f0010000 { | |
371 | compatible = "atmel,sama5d4-dma"; | |
372 | reg = <0xf0010000 0x1000>; | |
373 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; | |
374 | #dma-cells = <1>; | |
375 | clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; | |
376 | clock-names = "dma_clk"; | |
377 | }; | |
378 | ||
379 | /* Place dma1 here despite its address */ | |
380 | dma1: dma-controller@f0004000 { | |
381 | compatible = "atmel,sama5d4-dma"; | |
382 | reg = <0xf0004000 0x1000>; | |
383 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; | |
384 | #dma-cells = <1>; | |
385 | clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; | |
386 | clock-names = "dma_clk"; | |
387 | }; | |
388 | ||
389 | pmc: pmc@f0014000 { | |
390 | compatible = "atmel,sama5d2-pmc", "syscon"; | |
391 | reg = <0xf0014000 0x160>; | |
392 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
393 | #clock-cells = <2>; | |
394 | clocks = <&clk32k>, <&main_xtal>; | |
395 | clock-names = "slow_clk", "main_xtal"; | |
396 | }; | |
397 | ||
398 | qspi0: spi@f0020000 { | |
399 | compatible = "atmel,sama5d2-qspi"; | |
400 | reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; | |
401 | reg-names = "qspi_base", "qspi_mmap"; | |
402 | interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; | |
403 | clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; | |
404 | #address-cells = <1>; | |
405 | #size-cells = <0>; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
409 | qspi1: spi@f0024000 { | |
410 | compatible = "atmel,sama5d2-qspi"; | |
411 | reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; | |
412 | reg-names = "qspi_base", "qspi_mmap"; | |
413 | interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; | |
414 | clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; | |
415 | #address-cells = <1>; | |
416 | #size-cells = <0>; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
420 | sha@f0028000 { | |
421 | compatible = "atmel,at91sam9g46-sha"; | |
422 | reg = <0xf0028000 0x100>; | |
423 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | |
424 | dmas = <&dma0 | |
425 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
426 | AT91_XDMAC_DT_PERID(30))>; | |
427 | dma-names = "tx"; | |
428 | clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; | |
429 | clock-names = "sha_clk"; | |
430 | status = "okay"; | |
431 | }; | |
432 | ||
433 | aes@f002c000 { | |
434 | compatible = "atmel,at91sam9g46-aes"; | |
435 | reg = <0xf002c000 0x100>; | |
436 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; | |
437 | dmas = <&dma0 | |
438 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
439 | AT91_XDMAC_DT_PERID(26))>, | |
440 | <&dma0 | |
441 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
442 | AT91_XDMAC_DT_PERID(27))>; | |
443 | dma-names = "tx", "rx"; | |
444 | clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; | |
445 | clock-names = "aes_clk"; | |
446 | status = "okay"; | |
447 | }; | |
448 | ||
449 | spi0: spi@f8000000 { | |
450 | compatible = "atmel,at91rm9200-spi"; | |
451 | reg = <0xf8000000 0x100>; | |
452 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; | |
453 | dmas = <&dma0 | |
454 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
455 | AT91_XDMAC_DT_PERID(6))>, | |
456 | <&dma0 | |
457 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
458 | AT91_XDMAC_DT_PERID(7))>; | |
459 | dma-names = "tx", "rx"; | |
460 | clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; | |
461 | clock-names = "spi_clk"; | |
462 | atmel,fifo-size = <16>; | |
463 | #address-cells = <1>; | |
464 | #size-cells = <0>; | |
465 | status = "disabled"; | |
466 | }; | |
467 | ||
468 | ssc0: ssc@f8004000 { | |
469 | compatible = "atmel,at91sam9g45-ssc"; | |
470 | reg = <0xf8004000 0x4000>; | |
471 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; | |
472 | dmas = <&dma0 | |
473 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
474 | AT91_XDMAC_DT_PERID(21))>, | |
475 | <&dma0 | |
476 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
477 | AT91_XDMAC_DT_PERID(22))>; | |
478 | dma-names = "tx", "rx"; | |
479 | clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; | |
480 | clock-names = "pclk"; | |
481 | status = "disabled"; | |
482 | }; | |
483 | ||
484 | macb0: ethernet@f8008000 { | |
485 | compatible = "atmel,sama5d2-gem"; | |
486 | reg = <0xf8008000 0x1000>; | |
487 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ | |
488 | 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ | |
489 | 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ | |
490 | #address-cells = <1>; | |
491 | #size-cells = <0>; | |
492 | clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; | |
493 | clock-names = "hclk", "pclk"; | |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
497 | tcb0: timer@f800c000 { | |
498 | compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; | |
499 | #address-cells = <1>; | |
500 | #size-cells = <0>; | |
501 | reg = <0xf800c000 0x100>; | |
502 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; | |
503 | clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>; | |
504 | clock-names = "t0_clk", "slow_clk"; | |
505 | }; | |
506 | ||
507 | tcb1: timer@f8010000 { | |
508 | compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; | |
509 | #address-cells = <1>; | |
510 | #size-cells = <0>; | |
511 | reg = <0xf8010000 0x100>; | |
512 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
513 | clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>; | |
514 | clock-names = "t0_clk", "slow_clk"; | |
515 | }; | |
516 | ||
517 | hsmc: hsmc@f8014000 { | |
518 | compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; | |
519 | reg = <0xf8014000 0x1000>; | |
520 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; | |
521 | clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; | |
522 | #address-cells = <1>; | |
523 | #size-cells = <1>; | |
524 | ranges; | |
525 | ||
526 | pmecc: ecc-engine@f8014070 { | |
527 | compatible = "atmel,sama5d2-pmecc"; | |
528 | reg = <0xf8014070 0x490>, | |
529 | <0xf8014500 0x100>; | |
530 | }; | |
531 | }; | |
532 | ||
533 | pdmic: pdmic@f8018000 { | |
534 | compatible = "atmel,sama5d2-pdmic"; | |
535 | reg = <0xf8018000 0x124>; | |
536 | interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; | |
537 | dmas = <&dma0 | |
538 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
539 | | AT91_XDMAC_DT_PERID(50))>; | |
540 | dma-names = "rx"; | |
541 | clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; | |
542 | clock-names = "pclk", "gclk"; | |
543 | status = "disabled"; | |
544 | }; | |
545 | ||
546 | uart0: serial@f801c000 { | |
547 | compatible = "atmel,at91sam9260-usart"; | |
548 | reg = <0xf801c000 0x100>; | |
549 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; | |
550 | dmas = <&dma0 | |
551 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
552 | AT91_XDMAC_DT_PERID(35))>, | |
553 | <&dma0 | |
554 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
555 | AT91_XDMAC_DT_PERID(36))>; | |
556 | dma-names = "tx", "rx"; | |
557 | clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; | |
558 | clock-names = "usart"; | |
559 | status = "disabled"; | |
560 | }; | |
561 | ||
562 | uart1: serial@f8020000 { | |
563 | compatible = "atmel,at91sam9260-usart"; | |
564 | reg = <0xf8020000 0x100>; | |
565 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; | |
566 | dmas = <&dma0 | |
567 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
568 | AT91_XDMAC_DT_PERID(37))>, | |
569 | <&dma0 | |
570 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
571 | AT91_XDMAC_DT_PERID(38))>; | |
572 | dma-names = "tx", "rx"; | |
573 | clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; | |
574 | clock-names = "usart"; | |
575 | status = "disabled"; | |
576 | }; | |
577 | ||
578 | uart2: serial@f8024000 { | |
579 | compatible = "atmel,at91sam9260-usart"; | |
580 | reg = <0xf8024000 0x100>; | |
581 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; | |
582 | dmas = <&dma0 | |
583 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
584 | AT91_XDMAC_DT_PERID(39))>, | |
585 | <&dma0 | |
586 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
587 | AT91_XDMAC_DT_PERID(40))>; | |
588 | dma-names = "tx", "rx"; | |
589 | clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; | |
590 | clock-names = "usart"; | |
591 | status = "disabled"; | |
592 | }; | |
593 | ||
594 | i2c0: i2c@f8028000 { | |
595 | compatible = "atmel,sama5d2-i2c"; | |
596 | reg = <0xf8028000 0x100>; | |
597 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; | |
598 | dmas = <&dma0 | |
599 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
600 | AT91_XDMAC_DT_PERID(0))>, | |
601 | <&dma0 | |
602 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
603 | AT91_XDMAC_DT_PERID(1))>; | |
604 | dma-names = "tx", "rx"; | |
605 | #address-cells = <1>; | |
606 | #size-cells = <0>; | |
607 | clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; | |
608 | atmel,fifo-size = <16>; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
612 | pwm0: pwm@f802c000 { | |
613 | compatible = "atmel,sama5d2-pwm"; | |
614 | reg = <0xf802c000 0x4000>; | |
615 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; | |
616 | #pwm-cells = <3>; | |
617 | clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; | |
618 | }; | |
619 | ||
620 | sfr: sfr@f8030000 { | |
621 | compatible = "atmel,sama5d2-sfr", "syscon"; | |
622 | reg = <0xf8030000 0x98>; | |
623 | }; | |
624 | ||
625 | flx0: flexcom@f8034000 { | |
626 | compatible = "atmel,sama5d2-flexcom"; | |
627 | reg = <0xf8034000 0x200>; | |
628 | clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; | |
629 | #address-cells = <1>; | |
630 | #size-cells = <1>; | |
631 | ranges = <0x0 0xf8034000 0x800>; | |
632 | status = "disabled"; | |
633 | }; | |
634 | ||
635 | flx1: flexcom@f8038000 { | |
636 | compatible = "atmel,sama5d2-flexcom"; | |
637 | reg = <0xf8038000 0x200>; | |
638 | clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; | |
639 | #address-cells = <1>; | |
640 | #size-cells = <1>; | |
641 | ranges = <0x0 0xf8038000 0x800>; | |
642 | status = "disabled"; | |
643 | }; | |
644 | ||
645 | securam: sram@f8044000 { | |
646 | compatible = "atmel,sama5d2-securam", "mmio-sram"; | |
647 | reg = <0xf8044000 0x1420>; | |
648 | clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; | |
649 | #address-cells = <1>; | |
650 | #size-cells = <1>; | |
651 | ranges = <0 0xf8044000 0x1420>; | |
652 | }; | |
653 | ||
654 | reset_controller: rstc@f8048000 { | |
655 | compatible = "atmel,sama5d3-rstc"; | |
656 | reg = <0xf8048000 0x10>; | |
657 | clocks = <&clk32k>; | |
658 | }; | |
659 | ||
660 | shutdown_controller: shdwc@f8048010 { | |
661 | compatible = "atmel,sama5d2-shdwc"; | |
662 | reg = <0xf8048010 0x10>; | |
663 | clocks = <&clk32k>; | |
664 | #address-cells = <1>; | |
665 | #size-cells = <0>; | |
666 | atmel,wakeup-rtc-timer; | |
667 | }; | |
668 | ||
669 | pit: timer@f8048030 { | |
670 | compatible = "atmel,at91sam9260-pit"; | |
671 | reg = <0xf8048030 0x10>; | |
672 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; | |
673 | clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; | |
674 | }; | |
675 | ||
676 | watchdog: watchdog@f8048040 { | |
677 | compatible = "atmel,sama5d4-wdt"; | |
678 | reg = <0xf8048040 0x10>; | |
679 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; | |
680 | clocks = <&clk32k>; | |
681 | status = "disabled"; | |
682 | }; | |
683 | ||
684 | clk32k: sckc@f8048050 { | |
685 | compatible = "atmel,sama5d4-sckc"; | |
686 | reg = <0xf8048050 0x4>; | |
687 | ||
688 | clocks = <&slow_xtal>; | |
689 | #clock-cells = <0>; | |
690 | }; | |
691 | ||
692 | rtc@f80480b0 { | |
693 | compatible = "atmel,at91rm9200-rtc"; | |
694 | reg = <0xf80480b0 0x30>; | |
695 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
696 | clocks = <&clk32k>; | |
697 | }; | |
698 | ||
699 | i2s0: i2s@f8050000 { | |
700 | compatible = "atmel,sama5d2-i2s"; | |
701 | reg = <0xf8050000 0x100>; | |
702 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; | |
703 | dmas = <&dma0 | |
704 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
705 | AT91_XDMAC_DT_PERID(31))>, | |
706 | <&dma0 | |
707 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
708 | AT91_XDMAC_DT_PERID(32))>; | |
709 | dma-names = "tx", "rx"; | |
710 | clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; | |
711 | clock-names = "pclk", "gclk"; | |
712 | assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; | |
713 | assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; | |
714 | status = "disabled"; | |
715 | }; | |
716 | ||
717 | can0: can@f8054000 { | |
718 | compatible = "bosch,m_can"; | |
719 | reg = <0xf8054000 0x4000>, <0x210000 0x4000>; | |
720 | reg-names = "m_can", "message_ram"; | |
721 | interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, | |
722 | <64 IRQ_TYPE_LEVEL_HIGH 7>; | |
723 | interrupt-names = "int0", "int1"; | |
724 | clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; | |
725 | clock-names = "hclk", "cclk"; | |
726 | assigned-clocks = <&pmc PMC_TYPE_GCK 56>; | |
727 | assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; | |
728 | assigned-clock-rates = <40000000>; | |
729 | bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; | |
730 | status = "disabled"; | |
731 | }; | |
732 | ||
733 | spi1: spi@fc000000 { | |
734 | compatible = "atmel,at91rm9200-spi"; | |
735 | reg = <0xfc000000 0x100>; | |
736 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; | |
737 | dmas = <&dma0 | |
738 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
739 | AT91_XDMAC_DT_PERID(8))>, | |
740 | <&dma0 | |
741 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
742 | AT91_XDMAC_DT_PERID(9))>; | |
743 | dma-names = "tx", "rx"; | |
744 | clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; | |
745 | clock-names = "spi_clk"; | |
746 | atmel,fifo-size = <16>; | |
747 | #address-cells = <1>; | |
748 | #size-cells = <0>; | |
749 | status = "disabled"; | |
750 | }; | |
751 | ||
752 | uart3: serial@fc008000 { | |
753 | compatible = "atmel,at91sam9260-usart"; | |
754 | reg = <0xfc008000 0x100>; | |
755 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; | |
756 | dmas = <&dma1 | |
757 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
758 | AT91_XDMAC_DT_PERID(41))>, | |
759 | <&dma1 | |
760 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
761 | AT91_XDMAC_DT_PERID(42))>; | |
762 | dma-names = "tx", "rx"; | |
763 | clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; | |
764 | clock-names = "usart"; | |
765 | status = "disabled"; | |
766 | }; | |
767 | ||
768 | uart4: serial@fc00c000 { | |
769 | compatible = "atmel,at91sam9260-usart"; | |
770 | reg = <0xfc00c000 0x100>; | |
771 | dmas = <&dma0 | |
772 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
773 | AT91_XDMAC_DT_PERID(43))>, | |
774 | <&dma0 | |
775 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
776 | AT91_XDMAC_DT_PERID(44))>; | |
777 | dma-names = "tx", "rx"; | |
778 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; | |
779 | clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; | |
780 | clock-names = "usart"; | |
781 | status = "disabled"; | |
782 | }; | |
783 | ||
784 | flx2: flexcom@fc010000 { | |
785 | compatible = "atmel,sama5d2-flexcom"; | |
786 | reg = <0xfc010000 0x200>; | |
787 | clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; | |
788 | #address-cells = <1>; | |
789 | #size-cells = <1>; | |
790 | ranges = <0x0 0xfc010000 0x800>; | |
791 | status = "disabled"; | |
792 | }; | |
793 | ||
794 | flx3: flexcom@fc014000 { | |
795 | compatible = "atmel,sama5d2-flexcom"; | |
796 | reg = <0xfc014000 0x200>; | |
797 | clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; | |
798 | #address-cells = <1>; | |
799 | #size-cells = <1>; | |
800 | ranges = <0x0 0xfc014000 0x800>; | |
801 | status = "disabled"; | |
802 | }; | |
803 | ||
804 | flx4: flexcom@fc018000 { | |
805 | compatible = "atmel,sama5d2-flexcom"; | |
806 | reg = <0xfc018000 0x200>; | |
807 | clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; | |
808 | #address-cells = <1>; | |
809 | #size-cells = <1>; | |
810 | ranges = <0x0 0xfc018000 0x800>; | |
811 | status = "disabled"; | |
812 | }; | |
813 | ||
814 | trng@fc01c000 { | |
815 | compatible = "atmel,at91sam9g45-trng"; | |
816 | reg = <0xfc01c000 0x100>; | |
817 | interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; | |
818 | clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; | |
819 | }; | |
820 | ||
821 | aic: interrupt-controller@fc020000 { | |
822 | #interrupt-cells = <3>; | |
823 | compatible = "atmel,sama5d2-aic"; | |
824 | interrupt-controller; | |
825 | reg = <0xfc020000 0x200>; | |
826 | atmel,external-irqs = <49>; | |
827 | }; | |
828 | ||
829 | i2c1: i2c@fc028000 { | |
830 | compatible = "atmel,sama5d2-i2c"; | |
831 | reg = <0xfc028000 0x100>; | |
832 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; | |
833 | dmas = <&dma0 | |
834 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
835 | AT91_XDMAC_DT_PERID(2))>, | |
836 | <&dma0 | |
837 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
838 | AT91_XDMAC_DT_PERID(3))>; | |
839 | dma-names = "tx", "rx"; | |
840 | #address-cells = <1>; | |
841 | #size-cells = <0>; | |
842 | clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; | |
843 | atmel,fifo-size = <16>; | |
844 | status = "disabled"; | |
845 | }; | |
846 | ||
847 | adc: adc@fc030000 { | |
848 | compatible = "atmel,sama5d2-adc"; | |
849 | reg = <0xfc030000 0x100>; | |
850 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; | |
851 | clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; | |
852 | clock-names = "adc_clk"; | |
853 | dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; | |
854 | dma-names = "rx"; | |
855 | atmel,min-sample-rate-hz = <200000>; | |
856 | atmel,max-sample-rate-hz = <20000000>; | |
857 | atmel,startup-time-ms = <4>; | |
858 | atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; | |
859 | #io-channel-cells = <1>; | |
860 | status = "disabled"; | |
861 | }; | |
862 | ||
863 | resistive_touch: resistive-touch { | |
864 | compatible = "resistive-adc-touch"; | |
865 | io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, | |
866 | <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, | |
867 | <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; | |
868 | io-channel-names = "x", "y", "pressure"; | |
869 | touchscreen-min-pressure = <50000>; | |
870 | status = "disabled"; | |
871 | }; | |
872 | ||
873 | pioA: pinctrl@fc038000 { | |
874 | compatible = "atmel,sama5d2-pinctrl"; | |
875 | reg = <0xfc038000 0x600>; | |
876 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, | |
877 | <68 IRQ_TYPE_LEVEL_HIGH 7>, | |
878 | <69 IRQ_TYPE_LEVEL_HIGH 7>, | |
879 | <70 IRQ_TYPE_LEVEL_HIGH 7>; | |
880 | interrupt-controller; | |
881 | #interrupt-cells = <2>; | |
882 | gpio-controller; | |
883 | #gpio-cells = <2>; | |
884 | clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; | |
885 | }; | |
886 | ||
887 | secumod@fc040000 { | |
888 | compatible = "atmel,sama5d2-secumod", "syscon"; | |
889 | reg = <0xfc040000 0x100>; | |
890 | }; | |
891 | ||
892 | tdes@fc044000 { | |
893 | compatible = "atmel,at91sam9g46-tdes"; | |
894 | reg = <0xfc044000 0x100>; | |
895 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | |
896 | dmas = <&dma0 | |
897 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
898 | AT91_XDMAC_DT_PERID(28))>, | |
899 | <&dma0 | |
900 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
901 | AT91_XDMAC_DT_PERID(29))>; | |
902 | dma-names = "tx", "rx"; | |
903 | clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; | |
904 | clock-names = "tdes_clk"; | |
905 | status = "okay"; | |
906 | }; | |
907 | ||
908 | classd: classd@fc048000 { | |
909 | compatible = "atmel,sama5d2-classd"; | |
910 | reg = <0xfc048000 0x100>; | |
911 | interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; | |
912 | dmas = <&dma0 | |
913 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
914 | AT91_XDMAC_DT_PERID(47))>; | |
915 | dma-names = "tx"; | |
916 | clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; | |
917 | clock-names = "pclk", "gclk"; | |
918 | status = "disabled"; | |
919 | }; | |
920 | ||
921 | i2s1: i2s@fc04c000 { | |
922 | compatible = "atmel,sama5d2-i2s"; | |
923 | reg = <0xfc04c000 0x100>; | |
924 | interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; | |
925 | dmas = <&dma0 | |
926 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
927 | AT91_XDMAC_DT_PERID(33))>, | |
928 | <&dma0 | |
929 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
930 | AT91_XDMAC_DT_PERID(34))>; | |
931 | dma-names = "tx", "rx"; | |
932 | clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; | |
933 | clock-names = "pclk", "gclk"; | |
934 | assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; | |
935 | assigned-parrents = <&pmc PMC_TYPE_GCK 55>; | |
936 | status = "disabled"; | |
937 | }; | |
938 | ||
939 | can1: can@fc050000 { | |
940 | compatible = "bosch,m_can"; | |
941 | reg = <0xfc050000 0x4000>, <0x210000 0x4000>; | |
942 | reg-names = "m_can", "message_ram"; | |
943 | interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, | |
944 | <65 IRQ_TYPE_LEVEL_HIGH 7>; | |
945 | interrupt-names = "int0", "int1"; | |
946 | clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; | |
947 | clock-names = "hclk", "cclk"; | |
948 | assigned-clocks = <&pmc PMC_TYPE_GCK 57>; | |
949 | assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; | |
950 | assigned-clock-rates = <40000000>; | |
951 | bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; | |
952 | status = "disabled"; | |
953 | }; | |
954 | ||
955 | sfrbu: sfr@fc05c000 { | |
956 | compatible = "atmel,sama5d2-sfrbu", "syscon"; | |
957 | reg = <0xfc05c000 0x20>; | |
958 | }; | |
959 | ||
960 | chipid@fc069000 { | |
961 | compatible = "atmel,sama5d2-chipid"; | |
962 | reg = <0xfc069000 0x8>; | |
963 | }; | |
964 | }; | |
965 | }; | |
966 | }; |