]>
Commit | Line | Data |
---|---|---|
1 | // SPDX-License-Identifier: GPL-2.0-or-later | |
2 | /* | |
3 | * arch/arm/mach-ep93xx/clock.c | |
4 | * Clock control for Cirrus EP93xx chips. | |
5 | * | |
6 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | |
7 | */ | |
8 | ||
9 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/string.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/clkdev.h> | |
19 | #include <linux/soc/cirrus/ep93xx.h> | |
20 | ||
21 | #include "hardware.h" | |
22 | ||
23 | #include <asm/div64.h> | |
24 | ||
25 | #include "soc.h" | |
26 | ||
27 | struct clk { | |
28 | struct clk *parent; | |
29 | unsigned long rate; | |
30 | int users; | |
31 | int sw_locked; | |
32 | void __iomem *enable_reg; | |
33 | u32 enable_mask; | |
34 | ||
35 | unsigned long (*get_rate)(struct clk *clk); | |
36 | int (*set_rate)(struct clk *clk, unsigned long rate); | |
37 | }; | |
38 | ||
39 | ||
40 | static unsigned long get_uart_rate(struct clk *clk); | |
41 | ||
42 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate); | |
43 | static int set_div_rate(struct clk *clk, unsigned long rate); | |
44 | static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate); | |
45 | static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate); | |
46 | ||
47 | static struct clk clk_xtali = { | |
48 | .rate = EP93XX_EXT_CLK_RATE, | |
49 | }; | |
50 | static struct clk clk_uart1 = { | |
51 | .parent = &clk_xtali, | |
52 | .sw_locked = 1, | |
53 | .enable_reg = EP93XX_SYSCON_DEVCFG, | |
54 | .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, | |
55 | .get_rate = get_uart_rate, | |
56 | }; | |
57 | static struct clk clk_uart2 = { | |
58 | .parent = &clk_xtali, | |
59 | .sw_locked = 1, | |
60 | .enable_reg = EP93XX_SYSCON_DEVCFG, | |
61 | .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, | |
62 | .get_rate = get_uart_rate, | |
63 | }; | |
64 | static struct clk clk_uart3 = { | |
65 | .parent = &clk_xtali, | |
66 | .sw_locked = 1, | |
67 | .enable_reg = EP93XX_SYSCON_DEVCFG, | |
68 | .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, | |
69 | .get_rate = get_uart_rate, | |
70 | }; | |
71 | static struct clk clk_pll1 = { | |
72 | .parent = &clk_xtali, | |
73 | }; | |
74 | static struct clk clk_f = { | |
75 | .parent = &clk_pll1, | |
76 | }; | |
77 | static struct clk clk_h = { | |
78 | .parent = &clk_pll1, | |
79 | }; | |
80 | static struct clk clk_p = { | |
81 | .parent = &clk_pll1, | |
82 | }; | |
83 | static struct clk clk_pll2 = { | |
84 | .parent = &clk_xtali, | |
85 | }; | |
86 | static struct clk clk_usb_host = { | |
87 | .parent = &clk_pll2, | |
88 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
89 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, | |
90 | }; | |
91 | static struct clk clk_keypad = { | |
92 | .parent = &clk_xtali, | |
93 | .sw_locked = 1, | |
94 | .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, | |
95 | .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, | |
96 | .set_rate = set_keytchclk_rate, | |
97 | }; | |
98 | static struct clk clk_adc = { | |
99 | .parent = &clk_xtali, | |
100 | .sw_locked = 1, | |
101 | .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, | |
102 | .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, | |
103 | .set_rate = set_keytchclk_rate, | |
104 | }; | |
105 | static struct clk clk_spi = { | |
106 | .parent = &clk_xtali, | |
107 | .rate = EP93XX_EXT_CLK_RATE, | |
108 | }; | |
109 | static struct clk clk_pwm = { | |
110 | .parent = &clk_xtali, | |
111 | .rate = EP93XX_EXT_CLK_RATE, | |
112 | }; | |
113 | ||
114 | static struct clk clk_video = { | |
115 | .sw_locked = 1, | |
116 | .enable_reg = EP93XX_SYSCON_VIDCLKDIV, | |
117 | .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, | |
118 | .set_rate = set_div_rate, | |
119 | }; | |
120 | ||
121 | static struct clk clk_i2s_mclk = { | |
122 | .sw_locked = 1, | |
123 | .enable_reg = EP93XX_SYSCON_I2SCLKDIV, | |
124 | .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, | |
125 | .set_rate = set_div_rate, | |
126 | }; | |
127 | ||
128 | static struct clk clk_i2s_sclk = { | |
129 | .sw_locked = 1, | |
130 | .parent = &clk_i2s_mclk, | |
131 | .enable_reg = EP93XX_SYSCON_I2SCLKDIV, | |
132 | .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, | |
133 | .set_rate = set_i2s_sclk_rate, | |
134 | }; | |
135 | ||
136 | static struct clk clk_i2s_lrclk = { | |
137 | .sw_locked = 1, | |
138 | .parent = &clk_i2s_sclk, | |
139 | .enable_reg = EP93XX_SYSCON_I2SCLKDIV, | |
140 | .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, | |
141 | .set_rate = set_i2s_lrclk_rate, | |
142 | }; | |
143 | ||
144 | /* DMA Clocks */ | |
145 | static struct clk clk_m2p0 = { | |
146 | .parent = &clk_h, | |
147 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
148 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, | |
149 | }; | |
150 | static struct clk clk_m2p1 = { | |
151 | .parent = &clk_h, | |
152 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
153 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, | |
154 | }; | |
155 | static struct clk clk_m2p2 = { | |
156 | .parent = &clk_h, | |
157 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
158 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, | |
159 | }; | |
160 | static struct clk clk_m2p3 = { | |
161 | .parent = &clk_h, | |
162 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
163 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, | |
164 | }; | |
165 | static struct clk clk_m2p4 = { | |
166 | .parent = &clk_h, | |
167 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
168 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, | |
169 | }; | |
170 | static struct clk clk_m2p5 = { | |
171 | .parent = &clk_h, | |
172 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
173 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, | |
174 | }; | |
175 | static struct clk clk_m2p6 = { | |
176 | .parent = &clk_h, | |
177 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
178 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, | |
179 | }; | |
180 | static struct clk clk_m2p7 = { | |
181 | .parent = &clk_h, | |
182 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
183 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, | |
184 | }; | |
185 | static struct clk clk_m2p8 = { | |
186 | .parent = &clk_h, | |
187 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
188 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, | |
189 | }; | |
190 | static struct clk clk_m2p9 = { | |
191 | .parent = &clk_h, | |
192 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
193 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, | |
194 | }; | |
195 | static struct clk clk_m2m0 = { | |
196 | .parent = &clk_h, | |
197 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
198 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, | |
199 | }; | |
200 | static struct clk clk_m2m1 = { | |
201 | .parent = &clk_h, | |
202 | .enable_reg = EP93XX_SYSCON_PWRCNT, | |
203 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, | |
204 | }; | |
205 | ||
206 | #define INIT_CK(dev,con,ck) \ | |
207 | { .dev_id = dev, .con_id = con, .clk = ck } | |
208 | ||
209 | static struct clk_lookup clocks[] = { | |
210 | INIT_CK(NULL, "xtali", &clk_xtali), | |
211 | INIT_CK("apb:uart1", NULL, &clk_uart1), | |
212 | INIT_CK("apb:uart2", NULL, &clk_uart2), | |
213 | INIT_CK("apb:uart3", NULL, &clk_uart3), | |
214 | INIT_CK(NULL, "pll1", &clk_pll1), | |
215 | INIT_CK(NULL, "fclk", &clk_f), | |
216 | INIT_CK(NULL, "hclk", &clk_h), | |
217 | INIT_CK(NULL, "apb_pclk", &clk_p), | |
218 | INIT_CK(NULL, "pll2", &clk_pll2), | |
219 | INIT_CK("ohci-platform", NULL, &clk_usb_host), | |
220 | INIT_CK("ep93xx-keypad", NULL, &clk_keypad), | |
221 | INIT_CK("ep93xx-adc", NULL, &clk_adc), | |
222 | INIT_CK("ep93xx-fb", NULL, &clk_video), | |
223 | INIT_CK("ep93xx-spi.0", NULL, &clk_spi), | |
224 | INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk), | |
225 | INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk), | |
226 | INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk), | |
227 | INIT_CK(NULL, "pwm_clk", &clk_pwm), | |
228 | INIT_CK(NULL, "m2p0", &clk_m2p0), | |
229 | INIT_CK(NULL, "m2p1", &clk_m2p1), | |
230 | INIT_CK(NULL, "m2p2", &clk_m2p2), | |
231 | INIT_CK(NULL, "m2p3", &clk_m2p3), | |
232 | INIT_CK(NULL, "m2p4", &clk_m2p4), | |
233 | INIT_CK(NULL, "m2p5", &clk_m2p5), | |
234 | INIT_CK(NULL, "m2p6", &clk_m2p6), | |
235 | INIT_CK(NULL, "m2p7", &clk_m2p7), | |
236 | INIT_CK(NULL, "m2p8", &clk_m2p8), | |
237 | INIT_CK(NULL, "m2p9", &clk_m2p9), | |
238 | INIT_CK(NULL, "m2m0", &clk_m2m0), | |
239 | INIT_CK(NULL, "m2m1", &clk_m2m1), | |
240 | }; | |
241 | ||
242 | static DEFINE_SPINLOCK(clk_lock); | |
243 | ||
244 | static void __clk_enable(struct clk *clk) | |
245 | { | |
246 | if (!clk->users++) { | |
247 | if (clk->parent) | |
248 | __clk_enable(clk->parent); | |
249 | ||
250 | if (clk->enable_reg) { | |
251 | u32 v; | |
252 | ||
253 | v = __raw_readl(clk->enable_reg); | |
254 | v |= clk->enable_mask; | |
255 | if (clk->sw_locked) | |
256 | ep93xx_syscon_swlocked_write(v, clk->enable_reg); | |
257 | else | |
258 | __raw_writel(v, clk->enable_reg); | |
259 | } | |
260 | } | |
261 | } | |
262 | ||
263 | int clk_enable(struct clk *clk) | |
264 | { | |
265 | unsigned long flags; | |
266 | ||
267 | if (!clk) | |
268 | return -EINVAL; | |
269 | ||
270 | spin_lock_irqsave(&clk_lock, flags); | |
271 | __clk_enable(clk); | |
272 | spin_unlock_irqrestore(&clk_lock, flags); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | EXPORT_SYMBOL(clk_enable); | |
277 | ||
278 | static void __clk_disable(struct clk *clk) | |
279 | { | |
280 | if (!--clk->users) { | |
281 | if (clk->enable_reg) { | |
282 | u32 v; | |
283 | ||
284 | v = __raw_readl(clk->enable_reg); | |
285 | v &= ~clk->enable_mask; | |
286 | if (clk->sw_locked) | |
287 | ep93xx_syscon_swlocked_write(v, clk->enable_reg); | |
288 | else | |
289 | __raw_writel(v, clk->enable_reg); | |
290 | } | |
291 | ||
292 | if (clk->parent) | |
293 | __clk_disable(clk->parent); | |
294 | } | |
295 | } | |
296 | ||
297 | void clk_disable(struct clk *clk) | |
298 | { | |
299 | unsigned long flags; | |
300 | ||
301 | if (!clk) | |
302 | return; | |
303 | ||
304 | spin_lock_irqsave(&clk_lock, flags); | |
305 | __clk_disable(clk); | |
306 | spin_unlock_irqrestore(&clk_lock, flags); | |
307 | } | |
308 | EXPORT_SYMBOL(clk_disable); | |
309 | ||
310 | static unsigned long get_uart_rate(struct clk *clk) | |
311 | { | |
312 | unsigned long rate = clk_get_rate(clk->parent); | |
313 | u32 value; | |
314 | ||
315 | value = __raw_readl(EP93XX_SYSCON_PWRCNT); | |
316 | if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) | |
317 | return rate; | |
318 | else | |
319 | return rate / 2; | |
320 | } | |
321 | ||
322 | unsigned long clk_get_rate(struct clk *clk) | |
323 | { | |
324 | if (clk->get_rate) | |
325 | return clk->get_rate(clk); | |
326 | ||
327 | return clk->rate; | |
328 | } | |
329 | EXPORT_SYMBOL(clk_get_rate); | |
330 | ||
331 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate) | |
332 | { | |
333 | u32 val; | |
334 | u32 div_bit; | |
335 | ||
336 | val = __raw_readl(clk->enable_reg); | |
337 | ||
338 | /* | |
339 | * The Key Matrix and ADC clocks are configured using the same | |
340 | * System Controller register. The clock used will be either | |
341 | * 1/4 or 1/16 the external clock rate depending on the | |
342 | * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV | |
343 | * bit being set or cleared. | |
344 | */ | |
345 | div_bit = clk->enable_mask >> 15; | |
346 | ||
347 | if (rate == EP93XX_KEYTCHCLK_DIV4) | |
348 | val |= div_bit; | |
349 | else if (rate == EP93XX_KEYTCHCLK_DIV16) | |
350 | val &= ~div_bit; | |
351 | else | |
352 | return -EINVAL; | |
353 | ||
354 | ep93xx_syscon_swlocked_write(val, clk->enable_reg); | |
355 | clk->rate = rate; | |
356 | return 0; | |
357 | } | |
358 | ||
359 | static int calc_clk_div(struct clk *clk, unsigned long rate, | |
360 | int *psel, int *esel, int *pdiv, int *div) | |
361 | { | |
362 | struct clk *mclk; | |
363 | unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1; | |
364 | int i, found = 0, __div = 0, __pdiv = 0; | |
365 | ||
366 | /* Don't exceed the maximum rate */ | |
367 | max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); | |
368 | rate = min(rate, max_rate); | |
369 | ||
370 | /* | |
371 | * Try the two pll's and the external clock | |
372 | * Because the valid predividers are 2, 2.5 and 3, we multiply | |
373 | * all the clocks by 2 to avoid floating point math. | |
374 | * | |
375 | * This is based on the algorithm in the ep93xx raster guide: | |
376 | * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf | |
377 | * | |
378 | */ | |
379 | for (i = 0; i < 3; i++) { | |
380 | if (i == 0) | |
381 | mclk = &clk_xtali; | |
382 | else if (i == 1) | |
383 | mclk = &clk_pll1; | |
384 | else | |
385 | mclk = &clk_pll2; | |
386 | mclk_rate = mclk->rate * 2; | |
387 | ||
388 | /* Try each predivider value */ | |
389 | for (__pdiv = 4; __pdiv <= 6; __pdiv++) { | |
390 | __div = mclk_rate / (rate * __pdiv); | |
391 | if (__div < 2 || __div > 127) | |
392 | continue; | |
393 | ||
394 | actual_rate = mclk_rate / (__pdiv * __div); | |
395 | ||
396 | if (!found || abs(actual_rate - rate) < rate_err) { | |
397 | *pdiv = __pdiv - 3; | |
398 | *div = __div; | |
399 | *psel = (i == 2); | |
400 | *esel = (i != 0); | |
401 | clk->parent = mclk; | |
402 | clk->rate = actual_rate; | |
403 | rate_err = abs(actual_rate - rate); | |
404 | found = 1; | |
405 | } | |
406 | } | |
407 | } | |
408 | ||
409 | if (!found) | |
410 | return -EINVAL; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static int set_div_rate(struct clk *clk, unsigned long rate) | |
416 | { | |
417 | int err, psel = 0, esel = 0, pdiv = 0, div = 0; | |
418 | u32 val; | |
419 | ||
420 | err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); | |
421 | if (err) | |
422 | return err; | |
423 | ||
424 | /* Clear the esel, psel, pdiv and div bits */ | |
425 | val = __raw_readl(clk->enable_reg); | |
426 | val &= ~0x7fff; | |
427 | ||
428 | /* Set the new esel, psel, pdiv and div bits for the new clock rate */ | |
429 | val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | | |
430 | (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) | | |
431 | (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; | |
432 | ep93xx_syscon_swlocked_write(val, clk->enable_reg); | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) | |
437 | { | |
438 | unsigned val = __raw_readl(clk->enable_reg); | |
439 | ||
440 | if (rate == clk_i2s_mclk.rate / 2) | |
441 | ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, | |
442 | clk->enable_reg); | |
443 | else if (rate == clk_i2s_mclk.rate / 4) | |
444 | ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, | |
445 | clk->enable_reg); | |
446 | else | |
447 | return -EINVAL; | |
448 | ||
449 | clk_i2s_sclk.rate = rate; | |
450 | return 0; | |
451 | } | |
452 | ||
453 | static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) | |
454 | { | |
455 | unsigned val = __raw_readl(clk->enable_reg) & | |
456 | ~EP93XX_I2SCLKDIV_LRDIV_MASK; | |
457 | ||
458 | if (rate == clk_i2s_sclk.rate / 32) | |
459 | ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32, | |
460 | clk->enable_reg); | |
461 | else if (rate == clk_i2s_sclk.rate / 64) | |
462 | ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64, | |
463 | clk->enable_reg); | |
464 | else if (rate == clk_i2s_sclk.rate / 128) | |
465 | ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128, | |
466 | clk->enable_reg); | |
467 | else | |
468 | return -EINVAL; | |
469 | ||
470 | clk_i2s_lrclk.rate = rate; | |
471 | return 0; | |
472 | } | |
473 | ||
474 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
475 | { | |
476 | if (clk->set_rate) | |
477 | return clk->set_rate(clk, rate); | |
478 | ||
479 | return -EINVAL; | |
480 | } | |
481 | EXPORT_SYMBOL(clk_set_rate); | |
482 | ||
483 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
484 | { | |
485 | WARN_ON(clk); | |
486 | return 0; | |
487 | } | |
488 | EXPORT_SYMBOL(clk_round_rate); | |
489 | ||
490 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
491 | { | |
492 | WARN_ON(clk); | |
493 | return 0; | |
494 | } | |
495 | EXPORT_SYMBOL(clk_set_parent); | |
496 | ||
497 | struct clk *clk_get_parent(struct clk *clk) | |
498 | { | |
499 | return clk->parent; | |
500 | } | |
501 | EXPORT_SYMBOL(clk_get_parent); | |
502 | ||
503 | ||
504 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; | |
505 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; | |
506 | static char pclk_divisors[] = { 1, 2, 4, 8 }; | |
507 | ||
508 | /* | |
509 | * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS | |
510 | */ | |
511 | static unsigned long calc_pll_rate(u32 config_word) | |
512 | { | |
513 | unsigned long long rate; | |
514 | int i; | |
515 | ||
516 | rate = clk_xtali.rate; | |
517 | rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ | |
518 | rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ | |
519 | do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ | |
520 | for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ | |
521 | rate >>= 1; | |
522 | ||
523 | return (unsigned long)rate; | |
524 | } | |
525 | ||
526 | static void __init ep93xx_dma_clock_init(void) | |
527 | { | |
528 | clk_m2p0.rate = clk_h.rate; | |
529 | clk_m2p1.rate = clk_h.rate; | |
530 | clk_m2p2.rate = clk_h.rate; | |
531 | clk_m2p3.rate = clk_h.rate; | |
532 | clk_m2p4.rate = clk_h.rate; | |
533 | clk_m2p5.rate = clk_h.rate; | |
534 | clk_m2p6.rate = clk_h.rate; | |
535 | clk_m2p7.rate = clk_h.rate; | |
536 | clk_m2p8.rate = clk_h.rate; | |
537 | clk_m2p9.rate = clk_h.rate; | |
538 | clk_m2m0.rate = clk_h.rate; | |
539 | clk_m2m1.rate = clk_h.rate; | |
540 | } | |
541 | ||
542 | static int __init ep93xx_clock_init(void) | |
543 | { | |
544 | u32 value; | |
545 | ||
546 | /* Determine the bootloader configured pll1 rate */ | |
547 | value = __raw_readl(EP93XX_SYSCON_CLKSET1); | |
548 | if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) | |
549 | clk_pll1.rate = clk_xtali.rate; | |
550 | else | |
551 | clk_pll1.rate = calc_pll_rate(value); | |
552 | ||
553 | /* Initialize the pll1 derived clocks */ | |
554 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; | |
555 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; | |
556 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; | |
557 | ep93xx_dma_clock_init(); | |
558 | ||
559 | /* Determine the bootloader configured pll2 rate */ | |
560 | value = __raw_readl(EP93XX_SYSCON_CLKSET2); | |
561 | if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) | |
562 | clk_pll2.rate = clk_xtali.rate; | |
563 | else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) | |
564 | clk_pll2.rate = calc_pll_rate(value); | |
565 | else | |
566 | clk_pll2.rate = 0; | |
567 | ||
568 | /* Initialize the pll2 derived clocks */ | |
569 | clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); | |
570 | ||
571 | /* | |
572 | * EP93xx SSP clock rate was doubled in version E2. For more information | |
573 | * see: | |
574 | * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf | |
575 | */ | |
576 | if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) | |
577 | clk_spi.rate /= 2; | |
578 | ||
579 | pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", | |
580 | clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); | |
581 | pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", | |
582 | clk_f.rate / 1000000, clk_h.rate / 1000000, | |
583 | clk_p.rate / 1000000); | |
584 | ||
585 | clkdev_add_table(clocks, ARRAY_SIZE(clocks)); | |
586 | return 0; | |
587 | } | |
588 | postcore_initcall(ep93xx_clock_init); |