]>
Commit | Line | Data |
---|---|---|
1 | /* linux/arch/arm/mach-exynos4/clock.c | |
2 | * | |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * EXYNOS4 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | ||
17 | #include <plat/cpu-freq.h> | |
18 | #include <plat/clock.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/pll.h> | |
21 | #include <plat/s5p-clock.h> | |
22 | #include <plat/clock-clksrc.h> | |
23 | ||
24 | #include <mach/map.h> | |
25 | #include <mach/regs-clock.h> | |
26 | #include <mach/sysmmu.h> | |
27 | ||
28 | static struct clk clk_sclk_hdmi27m = { | |
29 | .name = "sclk_hdmi27m", | |
30 | .rate = 27000000, | |
31 | }; | |
32 | ||
33 | static struct clk clk_sclk_hdmiphy = { | |
34 | .name = "sclk_hdmiphy", | |
35 | }; | |
36 | ||
37 | static struct clk clk_sclk_usbphy0 = { | |
38 | .name = "sclk_usbphy0", | |
39 | .rate = 27000000, | |
40 | }; | |
41 | ||
42 | static struct clk clk_sclk_usbphy1 = { | |
43 | .name = "sclk_usbphy1", | |
44 | }; | |
45 | ||
46 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) | |
47 | { | |
48 | return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); | |
49 | } | |
50 | ||
51 | static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) | |
52 | { | |
53 | return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); | |
54 | } | |
55 | ||
56 | static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) | |
57 | { | |
58 | return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); | |
59 | } | |
60 | ||
61 | static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) | |
62 | { | |
63 | return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); | |
64 | } | |
65 | ||
66 | static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) | |
67 | { | |
68 | return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); | |
69 | } | |
70 | ||
71 | static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) | |
72 | { | |
73 | return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); | |
74 | } | |
75 | ||
76 | static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) | |
77 | { | |
78 | return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); | |
79 | } | |
80 | ||
81 | static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) | |
82 | { | |
83 | return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); | |
84 | } | |
85 | ||
86 | static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) | |
87 | { | |
88 | return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); | |
89 | } | |
90 | ||
91 | static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) | |
92 | { | |
93 | return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable); | |
94 | } | |
95 | ||
96 | static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) | |
97 | { | |
98 | return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); | |
99 | } | |
100 | ||
101 | static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) | |
102 | { | |
103 | return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); | |
104 | } | |
105 | ||
106 | static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) | |
107 | { | |
108 | return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); | |
109 | } | |
110 | ||
111 | static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) | |
112 | { | |
113 | return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); | |
114 | } | |
115 | ||
116 | static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) | |
117 | { | |
118 | return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); | |
119 | } | |
120 | ||
121 | static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) | |
122 | { | |
123 | return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); | |
124 | } | |
125 | ||
126 | /* Core list of CMU_CPU side */ | |
127 | ||
128 | static struct clksrc_clk clk_mout_apll = { | |
129 | .clk = { | |
130 | .name = "mout_apll", | |
131 | }, | |
132 | .sources = &clk_src_apll, | |
133 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, | |
134 | }; | |
135 | ||
136 | static struct clksrc_clk clk_sclk_apll = { | |
137 | .clk = { | |
138 | .name = "sclk_apll", | |
139 | .parent = &clk_mout_apll.clk, | |
140 | }, | |
141 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, | |
142 | }; | |
143 | ||
144 | static struct clksrc_clk clk_mout_epll = { | |
145 | .clk = { | |
146 | .name = "mout_epll", | |
147 | }, | |
148 | .sources = &clk_src_epll, | |
149 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, | |
150 | }; | |
151 | ||
152 | static struct clksrc_clk clk_mout_mpll = { | |
153 | .clk = { | |
154 | .name = "mout_mpll", | |
155 | }, | |
156 | .sources = &clk_src_mpll, | |
157 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, | |
158 | }; | |
159 | ||
160 | static struct clk *clkset_moutcore_list[] = { | |
161 | [0] = &clk_mout_apll.clk, | |
162 | [1] = &clk_mout_mpll.clk, | |
163 | }; | |
164 | ||
165 | static struct clksrc_sources clkset_moutcore = { | |
166 | .sources = clkset_moutcore_list, | |
167 | .nr_sources = ARRAY_SIZE(clkset_moutcore_list), | |
168 | }; | |
169 | ||
170 | static struct clksrc_clk clk_moutcore = { | |
171 | .clk = { | |
172 | .name = "moutcore", | |
173 | }, | |
174 | .sources = &clkset_moutcore, | |
175 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, | |
176 | }; | |
177 | ||
178 | static struct clksrc_clk clk_coreclk = { | |
179 | .clk = { | |
180 | .name = "core_clk", | |
181 | .parent = &clk_moutcore.clk, | |
182 | }, | |
183 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, | |
184 | }; | |
185 | ||
186 | static struct clksrc_clk clk_armclk = { | |
187 | .clk = { | |
188 | .name = "armclk", | |
189 | .parent = &clk_coreclk.clk, | |
190 | }, | |
191 | }; | |
192 | ||
193 | static struct clksrc_clk clk_aclk_corem0 = { | |
194 | .clk = { | |
195 | .name = "aclk_corem0", | |
196 | .parent = &clk_coreclk.clk, | |
197 | }, | |
198 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | |
199 | }; | |
200 | ||
201 | static struct clksrc_clk clk_aclk_cores = { | |
202 | .clk = { | |
203 | .name = "aclk_cores", | |
204 | .parent = &clk_coreclk.clk, | |
205 | }, | |
206 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | |
207 | }; | |
208 | ||
209 | static struct clksrc_clk clk_aclk_corem1 = { | |
210 | .clk = { | |
211 | .name = "aclk_corem1", | |
212 | .parent = &clk_coreclk.clk, | |
213 | }, | |
214 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, | |
215 | }; | |
216 | ||
217 | static struct clksrc_clk clk_periphclk = { | |
218 | .clk = { | |
219 | .name = "periphclk", | |
220 | .parent = &clk_coreclk.clk, | |
221 | }, | |
222 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, | |
223 | }; | |
224 | ||
225 | /* Core list of CMU_CORE side */ | |
226 | ||
227 | static struct clk *clkset_corebus_list[] = { | |
228 | [0] = &clk_mout_mpll.clk, | |
229 | [1] = &clk_sclk_apll.clk, | |
230 | }; | |
231 | ||
232 | static struct clksrc_sources clkset_mout_corebus = { | |
233 | .sources = clkset_corebus_list, | |
234 | .nr_sources = ARRAY_SIZE(clkset_corebus_list), | |
235 | }; | |
236 | ||
237 | static struct clksrc_clk clk_mout_corebus = { | |
238 | .clk = { | |
239 | .name = "mout_corebus", | |
240 | }, | |
241 | .sources = &clkset_mout_corebus, | |
242 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, | |
243 | }; | |
244 | ||
245 | static struct clksrc_clk clk_sclk_dmc = { | |
246 | .clk = { | |
247 | .name = "sclk_dmc", | |
248 | .parent = &clk_mout_corebus.clk, | |
249 | }, | |
250 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, | |
251 | }; | |
252 | ||
253 | static struct clksrc_clk clk_aclk_cored = { | |
254 | .clk = { | |
255 | .name = "aclk_cored", | |
256 | .parent = &clk_sclk_dmc.clk, | |
257 | }, | |
258 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, | |
259 | }; | |
260 | ||
261 | static struct clksrc_clk clk_aclk_corep = { | |
262 | .clk = { | |
263 | .name = "aclk_corep", | |
264 | .parent = &clk_aclk_cored.clk, | |
265 | }, | |
266 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, | |
267 | }; | |
268 | ||
269 | static struct clksrc_clk clk_aclk_acp = { | |
270 | .clk = { | |
271 | .name = "aclk_acp", | |
272 | .parent = &clk_mout_corebus.clk, | |
273 | }, | |
274 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, | |
275 | }; | |
276 | ||
277 | static struct clksrc_clk clk_pclk_acp = { | |
278 | .clk = { | |
279 | .name = "pclk_acp", | |
280 | .parent = &clk_aclk_acp.clk, | |
281 | }, | |
282 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, | |
283 | }; | |
284 | ||
285 | /* Core list of CMU_TOP side */ | |
286 | ||
287 | static struct clk *clkset_aclk_top_list[] = { | |
288 | [0] = &clk_mout_mpll.clk, | |
289 | [1] = &clk_sclk_apll.clk, | |
290 | }; | |
291 | ||
292 | static struct clksrc_sources clkset_aclk = { | |
293 | .sources = clkset_aclk_top_list, | |
294 | .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), | |
295 | }; | |
296 | ||
297 | static struct clksrc_clk clk_aclk_200 = { | |
298 | .clk = { | |
299 | .name = "aclk_200", | |
300 | }, | |
301 | .sources = &clkset_aclk, | |
302 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, | |
303 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, | |
304 | }; | |
305 | ||
306 | static struct clksrc_clk clk_aclk_100 = { | |
307 | .clk = { | |
308 | .name = "aclk_100", | |
309 | }, | |
310 | .sources = &clkset_aclk, | |
311 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, | |
312 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, | |
313 | }; | |
314 | ||
315 | static struct clksrc_clk clk_aclk_160 = { | |
316 | .clk = { | |
317 | .name = "aclk_160", | |
318 | }, | |
319 | .sources = &clkset_aclk, | |
320 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, | |
321 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, | |
322 | }; | |
323 | ||
324 | static struct clksrc_clk clk_aclk_133 = { | |
325 | .clk = { | |
326 | .name = "aclk_133", | |
327 | }, | |
328 | .sources = &clkset_aclk, | |
329 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, | |
330 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, | |
331 | }; | |
332 | ||
333 | static struct clk *clkset_vpllsrc_list[] = { | |
334 | [0] = &clk_fin_vpll, | |
335 | [1] = &clk_sclk_hdmi27m, | |
336 | }; | |
337 | ||
338 | static struct clksrc_sources clkset_vpllsrc = { | |
339 | .sources = clkset_vpllsrc_list, | |
340 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | |
341 | }; | |
342 | ||
343 | static struct clksrc_clk clk_vpllsrc = { | |
344 | .clk = { | |
345 | .name = "vpll_src", | |
346 | .enable = exynos4_clksrc_mask_top_ctrl, | |
347 | .ctrlbit = (1 << 0), | |
348 | }, | |
349 | .sources = &clkset_vpllsrc, | |
350 | .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, | |
351 | }; | |
352 | ||
353 | static struct clk *clkset_sclk_vpll_list[] = { | |
354 | [0] = &clk_vpllsrc.clk, | |
355 | [1] = &clk_fout_vpll, | |
356 | }; | |
357 | ||
358 | static struct clksrc_sources clkset_sclk_vpll = { | |
359 | .sources = clkset_sclk_vpll_list, | |
360 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | |
361 | }; | |
362 | ||
363 | static struct clksrc_clk clk_sclk_vpll = { | |
364 | .clk = { | |
365 | .name = "sclk_vpll", | |
366 | }, | |
367 | .sources = &clkset_sclk_vpll, | |
368 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, | |
369 | }; | |
370 | ||
371 | static struct clk init_clocks_off[] = { | |
372 | { | |
373 | .name = "timers", | |
374 | .parent = &clk_aclk_100.clk, | |
375 | .enable = exynos4_clk_ip_peril_ctrl, | |
376 | .ctrlbit = (1<<24), | |
377 | }, { | |
378 | .name = "csis", | |
379 | .devname = "s5p-mipi-csis.0", | |
380 | .enable = exynos4_clk_ip_cam_ctrl, | |
381 | .ctrlbit = (1 << 4), | |
382 | }, { | |
383 | .name = "csis", | |
384 | .devname = "s5p-mipi-csis.1", | |
385 | .enable = exynos4_clk_ip_cam_ctrl, | |
386 | .ctrlbit = (1 << 5), | |
387 | }, { | |
388 | .name = "fimc", | |
389 | .devname = "exynos4-fimc.0", | |
390 | .enable = exynos4_clk_ip_cam_ctrl, | |
391 | .ctrlbit = (1 << 0), | |
392 | }, { | |
393 | .name = "fimc", | |
394 | .devname = "exynos4-fimc.1", | |
395 | .enable = exynos4_clk_ip_cam_ctrl, | |
396 | .ctrlbit = (1 << 1), | |
397 | }, { | |
398 | .name = "fimc", | |
399 | .devname = "exynos4-fimc.2", | |
400 | .enable = exynos4_clk_ip_cam_ctrl, | |
401 | .ctrlbit = (1 << 2), | |
402 | }, { | |
403 | .name = "fimc", | |
404 | .devname = "exynos4-fimc.3", | |
405 | .enable = exynos4_clk_ip_cam_ctrl, | |
406 | .ctrlbit = (1 << 3), | |
407 | }, { | |
408 | .name = "fimd", | |
409 | .devname = "exynos4-fb.0", | |
410 | .enable = exynos4_clk_ip_lcd0_ctrl, | |
411 | .ctrlbit = (1 << 0), | |
412 | }, { | |
413 | .name = "fimd", | |
414 | .devname = "exynos4-fb.1", | |
415 | .enable = exynos4_clk_ip_lcd1_ctrl, | |
416 | .ctrlbit = (1 << 0), | |
417 | }, { | |
418 | .name = "sataphy", | |
419 | .parent = &clk_aclk_133.clk, | |
420 | .enable = exynos4_clk_ip_fsys_ctrl, | |
421 | .ctrlbit = (1 << 3), | |
422 | }, { | |
423 | .name = "hsmmc", | |
424 | .devname = "s3c-sdhci.0", | |
425 | .parent = &clk_aclk_133.clk, | |
426 | .enable = exynos4_clk_ip_fsys_ctrl, | |
427 | .ctrlbit = (1 << 5), | |
428 | }, { | |
429 | .name = "hsmmc", | |
430 | .devname = "s3c-sdhci.1", | |
431 | .parent = &clk_aclk_133.clk, | |
432 | .enable = exynos4_clk_ip_fsys_ctrl, | |
433 | .ctrlbit = (1 << 6), | |
434 | }, { | |
435 | .name = "hsmmc", | |
436 | .devname = "s3c-sdhci.2", | |
437 | .parent = &clk_aclk_133.clk, | |
438 | .enable = exynos4_clk_ip_fsys_ctrl, | |
439 | .ctrlbit = (1 << 7), | |
440 | }, { | |
441 | .name = "hsmmc", | |
442 | .devname = "s3c-sdhci.3", | |
443 | .parent = &clk_aclk_133.clk, | |
444 | .enable = exynos4_clk_ip_fsys_ctrl, | |
445 | .ctrlbit = (1 << 8), | |
446 | }, { | |
447 | .name = "dwmmc", | |
448 | .parent = &clk_aclk_133.clk, | |
449 | .enable = exynos4_clk_ip_fsys_ctrl, | |
450 | .ctrlbit = (1 << 9), | |
451 | }, { | |
452 | .name = "sata", | |
453 | .parent = &clk_aclk_133.clk, | |
454 | .enable = exynos4_clk_ip_fsys_ctrl, | |
455 | .ctrlbit = (1 << 10), | |
456 | }, { | |
457 | .name = "pdma", | |
458 | .devname = "s3c-pl330.0", | |
459 | .enable = exynos4_clk_ip_fsys_ctrl, | |
460 | .ctrlbit = (1 << 0), | |
461 | }, { | |
462 | .name = "pdma", | |
463 | .devname = "s3c-pl330.1", | |
464 | .enable = exynos4_clk_ip_fsys_ctrl, | |
465 | .ctrlbit = (1 << 1), | |
466 | }, { | |
467 | .name = "adc", | |
468 | .enable = exynos4_clk_ip_peril_ctrl, | |
469 | .ctrlbit = (1 << 15), | |
470 | }, { | |
471 | .name = "keypad", | |
472 | .enable = exynos4_clk_ip_perir_ctrl, | |
473 | .ctrlbit = (1 << 16), | |
474 | }, { | |
475 | .name = "rtc", | |
476 | .enable = exynos4_clk_ip_perir_ctrl, | |
477 | .ctrlbit = (1 << 15), | |
478 | }, { | |
479 | .name = "watchdog", | |
480 | .parent = &clk_aclk_100.clk, | |
481 | .enable = exynos4_clk_ip_perir_ctrl, | |
482 | .ctrlbit = (1 << 14), | |
483 | }, { | |
484 | .name = "usbhost", | |
485 | .enable = exynos4_clk_ip_fsys_ctrl , | |
486 | .ctrlbit = (1 << 12), | |
487 | }, { | |
488 | .name = "otg", | |
489 | .enable = exynos4_clk_ip_fsys_ctrl, | |
490 | .ctrlbit = (1 << 13), | |
491 | }, { | |
492 | .name = "spi", | |
493 | .devname = "s3c64xx-spi.0", | |
494 | .enable = exynos4_clk_ip_peril_ctrl, | |
495 | .ctrlbit = (1 << 16), | |
496 | }, { | |
497 | .name = "spi", | |
498 | .devname = "s3c64xx-spi.1", | |
499 | .enable = exynos4_clk_ip_peril_ctrl, | |
500 | .ctrlbit = (1 << 17), | |
501 | }, { | |
502 | .name = "spi", | |
503 | .devname = "s3c64xx-spi.2", | |
504 | .enable = exynos4_clk_ip_peril_ctrl, | |
505 | .ctrlbit = (1 << 18), | |
506 | }, { | |
507 | .name = "iis", | |
508 | .devname = "samsung-i2s.0", | |
509 | .enable = exynos4_clk_ip_peril_ctrl, | |
510 | .ctrlbit = (1 << 19), | |
511 | }, { | |
512 | .name = "iis", | |
513 | .devname = "samsung-i2s.1", | |
514 | .enable = exynos4_clk_ip_peril_ctrl, | |
515 | .ctrlbit = (1 << 20), | |
516 | }, { | |
517 | .name = "iis", | |
518 | .devname = "samsung-i2s.2", | |
519 | .enable = exynos4_clk_ip_peril_ctrl, | |
520 | .ctrlbit = (1 << 21), | |
521 | }, { | |
522 | .name = "ac97", | |
523 | .devname = "samsung-ac97", | |
524 | .enable = exynos4_clk_ip_peril_ctrl, | |
525 | .ctrlbit = (1 << 27), | |
526 | }, { | |
527 | .name = "fimg2d", | |
528 | .enable = exynos4_clk_ip_image_ctrl, | |
529 | .ctrlbit = (1 << 0), | |
530 | }, { | |
531 | .name = "mfc", | |
532 | .devname = "s5p-mfc", | |
533 | .enable = exynos4_clk_ip_mfc_ctrl, | |
534 | .ctrlbit = (1 << 0), | |
535 | }, { | |
536 | .name = "i2c", | |
537 | .devname = "s3c2440-i2c.0", | |
538 | .parent = &clk_aclk_100.clk, | |
539 | .enable = exynos4_clk_ip_peril_ctrl, | |
540 | .ctrlbit = (1 << 6), | |
541 | }, { | |
542 | .name = "i2c", | |
543 | .devname = "s3c2440-i2c.1", | |
544 | .parent = &clk_aclk_100.clk, | |
545 | .enable = exynos4_clk_ip_peril_ctrl, | |
546 | .ctrlbit = (1 << 7), | |
547 | }, { | |
548 | .name = "i2c", | |
549 | .devname = "s3c2440-i2c.2", | |
550 | .parent = &clk_aclk_100.clk, | |
551 | .enable = exynos4_clk_ip_peril_ctrl, | |
552 | .ctrlbit = (1 << 8), | |
553 | }, { | |
554 | .name = "i2c", | |
555 | .devname = "s3c2440-i2c.3", | |
556 | .parent = &clk_aclk_100.clk, | |
557 | .enable = exynos4_clk_ip_peril_ctrl, | |
558 | .ctrlbit = (1 << 9), | |
559 | }, { | |
560 | .name = "i2c", | |
561 | .devname = "s3c2440-i2c.4", | |
562 | .parent = &clk_aclk_100.clk, | |
563 | .enable = exynos4_clk_ip_peril_ctrl, | |
564 | .ctrlbit = (1 << 10), | |
565 | }, { | |
566 | .name = "i2c", | |
567 | .devname = "s3c2440-i2c.5", | |
568 | .parent = &clk_aclk_100.clk, | |
569 | .enable = exynos4_clk_ip_peril_ctrl, | |
570 | .ctrlbit = (1 << 11), | |
571 | }, { | |
572 | .name = "i2c", | |
573 | .devname = "s3c2440-i2c.6", | |
574 | .parent = &clk_aclk_100.clk, | |
575 | .enable = exynos4_clk_ip_peril_ctrl, | |
576 | .ctrlbit = (1 << 12), | |
577 | }, { | |
578 | .name = "i2c", | |
579 | .devname = "s3c2440-i2c.7", | |
580 | .parent = &clk_aclk_100.clk, | |
581 | .enable = exynos4_clk_ip_peril_ctrl, | |
582 | .ctrlbit = (1 << 13), | |
583 | }, { | |
584 | .name = "SYSMMU_MDMA", | |
585 | .enable = exynos4_clk_ip_image_ctrl, | |
586 | .ctrlbit = (1 << 5), | |
587 | }, { | |
588 | .name = "SYSMMU_FIMC0", | |
589 | .enable = exynos4_clk_ip_cam_ctrl, | |
590 | .ctrlbit = (1 << 7), | |
591 | }, { | |
592 | .name = "SYSMMU_FIMC1", | |
593 | .enable = exynos4_clk_ip_cam_ctrl, | |
594 | .ctrlbit = (1 << 8), | |
595 | }, { | |
596 | .name = "SYSMMU_FIMC2", | |
597 | .enable = exynos4_clk_ip_cam_ctrl, | |
598 | .ctrlbit = (1 << 9), | |
599 | }, { | |
600 | .name = "SYSMMU_FIMC3", | |
601 | .enable = exynos4_clk_ip_cam_ctrl, | |
602 | .ctrlbit = (1 << 10), | |
603 | }, { | |
604 | .name = "SYSMMU_JPEG", | |
605 | .enable = exynos4_clk_ip_cam_ctrl, | |
606 | .ctrlbit = (1 << 11), | |
607 | }, { | |
608 | .name = "SYSMMU_FIMD0", | |
609 | .enable = exynos4_clk_ip_lcd0_ctrl, | |
610 | .ctrlbit = (1 << 4), | |
611 | }, { | |
612 | .name = "SYSMMU_FIMD1", | |
613 | .enable = exynos4_clk_ip_lcd1_ctrl, | |
614 | .ctrlbit = (1 << 4), | |
615 | }, { | |
616 | .name = "SYSMMU_PCIe", | |
617 | .enable = exynos4_clk_ip_fsys_ctrl, | |
618 | .ctrlbit = (1 << 18), | |
619 | }, { | |
620 | .name = "SYSMMU_G2D", | |
621 | .enable = exynos4_clk_ip_image_ctrl, | |
622 | .ctrlbit = (1 << 3), | |
623 | }, { | |
624 | .name = "SYSMMU_ROTATOR", | |
625 | .enable = exynos4_clk_ip_image_ctrl, | |
626 | .ctrlbit = (1 << 4), | |
627 | }, { | |
628 | .name = "SYSMMU_TV", | |
629 | .enable = exynos4_clk_ip_tv_ctrl, | |
630 | .ctrlbit = (1 << 4), | |
631 | }, { | |
632 | .name = "SYSMMU_MFC_L", | |
633 | .enable = exynos4_clk_ip_mfc_ctrl, | |
634 | .ctrlbit = (1 << 1), | |
635 | }, { | |
636 | .name = "SYSMMU_MFC_R", | |
637 | .enable = exynos4_clk_ip_mfc_ctrl, | |
638 | .ctrlbit = (1 << 2), | |
639 | } | |
640 | }; | |
641 | ||
642 | static struct clk init_clocks[] = { | |
643 | { | |
644 | .name = "uart", | |
645 | .devname = "s5pv210-uart.0", | |
646 | .enable = exynos4_clk_ip_peril_ctrl, | |
647 | .ctrlbit = (1 << 0), | |
648 | }, { | |
649 | .name = "uart", | |
650 | .devname = "s5pv210-uart.1", | |
651 | .enable = exynos4_clk_ip_peril_ctrl, | |
652 | .ctrlbit = (1 << 1), | |
653 | }, { | |
654 | .name = "uart", | |
655 | .devname = "s5pv210-uart.2", | |
656 | .enable = exynos4_clk_ip_peril_ctrl, | |
657 | .ctrlbit = (1 << 2), | |
658 | }, { | |
659 | .name = "uart", | |
660 | .devname = "s5pv210-uart.3", | |
661 | .enable = exynos4_clk_ip_peril_ctrl, | |
662 | .ctrlbit = (1 << 3), | |
663 | }, { | |
664 | .name = "uart", | |
665 | .devname = "s5pv210-uart.4", | |
666 | .enable = exynos4_clk_ip_peril_ctrl, | |
667 | .ctrlbit = (1 << 4), | |
668 | }, { | |
669 | .name = "uart", | |
670 | .devname = "s5pv210-uart.5", | |
671 | .enable = exynos4_clk_ip_peril_ctrl, | |
672 | .ctrlbit = (1 << 5), | |
673 | } | |
674 | }; | |
675 | ||
676 | static struct clk *clkset_group_list[] = { | |
677 | [0] = &clk_ext_xtal_mux, | |
678 | [1] = &clk_xusbxti, | |
679 | [2] = &clk_sclk_hdmi27m, | |
680 | [3] = &clk_sclk_usbphy0, | |
681 | [4] = &clk_sclk_usbphy1, | |
682 | [5] = &clk_sclk_hdmiphy, | |
683 | [6] = &clk_mout_mpll.clk, | |
684 | [7] = &clk_mout_epll.clk, | |
685 | [8] = &clk_sclk_vpll.clk, | |
686 | }; | |
687 | ||
688 | static struct clksrc_sources clkset_group = { | |
689 | .sources = clkset_group_list, | |
690 | .nr_sources = ARRAY_SIZE(clkset_group_list), | |
691 | }; | |
692 | ||
693 | static struct clk *clkset_mout_g2d0_list[] = { | |
694 | [0] = &clk_mout_mpll.clk, | |
695 | [1] = &clk_sclk_apll.clk, | |
696 | }; | |
697 | ||
698 | static struct clksrc_sources clkset_mout_g2d0 = { | |
699 | .sources = clkset_mout_g2d0_list, | |
700 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list), | |
701 | }; | |
702 | ||
703 | static struct clksrc_clk clk_mout_g2d0 = { | |
704 | .clk = { | |
705 | .name = "mout_g2d0", | |
706 | }, | |
707 | .sources = &clkset_mout_g2d0, | |
708 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | |
709 | }; | |
710 | ||
711 | static struct clk *clkset_mout_g2d1_list[] = { | |
712 | [0] = &clk_mout_epll.clk, | |
713 | [1] = &clk_sclk_vpll.clk, | |
714 | }; | |
715 | ||
716 | static struct clksrc_sources clkset_mout_g2d1 = { | |
717 | .sources = clkset_mout_g2d1_list, | |
718 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list), | |
719 | }; | |
720 | ||
721 | static struct clksrc_clk clk_mout_g2d1 = { | |
722 | .clk = { | |
723 | .name = "mout_g2d1", | |
724 | }, | |
725 | .sources = &clkset_mout_g2d1, | |
726 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | |
727 | }; | |
728 | ||
729 | static struct clk *clkset_mout_g2d_list[] = { | |
730 | [0] = &clk_mout_g2d0.clk, | |
731 | [1] = &clk_mout_g2d1.clk, | |
732 | }; | |
733 | ||
734 | static struct clksrc_sources clkset_mout_g2d = { | |
735 | .sources = clkset_mout_g2d_list, | |
736 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), | |
737 | }; | |
738 | ||
739 | static struct clk *clkset_mout_mfc0_list[] = { | |
740 | [0] = &clk_mout_mpll.clk, | |
741 | [1] = &clk_sclk_apll.clk, | |
742 | }; | |
743 | ||
744 | static struct clksrc_sources clkset_mout_mfc0 = { | |
745 | .sources = clkset_mout_mfc0_list, | |
746 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), | |
747 | }; | |
748 | ||
749 | static struct clksrc_clk clk_mout_mfc0 = { | |
750 | .clk = { | |
751 | .name = "mout_mfc0", | |
752 | }, | |
753 | .sources = &clkset_mout_mfc0, | |
754 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, | |
755 | }; | |
756 | ||
757 | static struct clk *clkset_mout_mfc1_list[] = { | |
758 | [0] = &clk_mout_epll.clk, | |
759 | [1] = &clk_sclk_vpll.clk, | |
760 | }; | |
761 | ||
762 | static struct clksrc_sources clkset_mout_mfc1 = { | |
763 | .sources = clkset_mout_mfc1_list, | |
764 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), | |
765 | }; | |
766 | ||
767 | static struct clksrc_clk clk_mout_mfc1 = { | |
768 | .clk = { | |
769 | .name = "mout_mfc1", | |
770 | }, | |
771 | .sources = &clkset_mout_mfc1, | |
772 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, | |
773 | }; | |
774 | ||
775 | static struct clk *clkset_mout_mfc_list[] = { | |
776 | [0] = &clk_mout_mfc0.clk, | |
777 | [1] = &clk_mout_mfc1.clk, | |
778 | }; | |
779 | ||
780 | static struct clksrc_sources clkset_mout_mfc = { | |
781 | .sources = clkset_mout_mfc_list, | |
782 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), | |
783 | }; | |
784 | ||
785 | static struct clksrc_clk clk_dout_mmc0 = { | |
786 | .clk = { | |
787 | .name = "dout_mmc0", | |
788 | }, | |
789 | .sources = &clkset_group, | |
790 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, | |
791 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 }, | |
792 | }; | |
793 | ||
794 | static struct clksrc_clk clk_dout_mmc1 = { | |
795 | .clk = { | |
796 | .name = "dout_mmc1", | |
797 | }, | |
798 | .sources = &clkset_group, | |
799 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, | |
800 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 }, | |
801 | }; | |
802 | ||
803 | static struct clksrc_clk clk_dout_mmc2 = { | |
804 | .clk = { | |
805 | .name = "dout_mmc2", | |
806 | }, | |
807 | .sources = &clkset_group, | |
808 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, | |
809 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 }, | |
810 | }; | |
811 | ||
812 | static struct clksrc_clk clk_dout_mmc3 = { | |
813 | .clk = { | |
814 | .name = "dout_mmc3", | |
815 | }, | |
816 | .sources = &clkset_group, | |
817 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, | |
818 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 }, | |
819 | }; | |
820 | ||
821 | static struct clksrc_clk clk_dout_mmc4 = { | |
822 | .clk = { | |
823 | .name = "dout_mmc4", | |
824 | }, | |
825 | .sources = &clkset_group, | |
826 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, | |
827 | .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 }, | |
828 | }; | |
829 | ||
830 | static struct clksrc_clk clksrcs[] = { | |
831 | { | |
832 | .clk = { | |
833 | .name = "uclk1", | |
834 | .devname = "s5pv210-uart.0", | |
835 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
836 | .ctrlbit = (1 << 0), | |
837 | }, | |
838 | .sources = &clkset_group, | |
839 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, | |
840 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, | |
841 | }, { | |
842 | .clk = { | |
843 | .name = "uclk1", | |
844 | .devname = "s5pv210-uart.1", | |
845 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
846 | .ctrlbit = (1 << 4), | |
847 | }, | |
848 | .sources = &clkset_group, | |
849 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, | |
850 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, | |
851 | }, { | |
852 | .clk = { | |
853 | .name = "uclk1", | |
854 | .devname = "s5pv210-uart.2", | |
855 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
856 | .ctrlbit = (1 << 8), | |
857 | }, | |
858 | .sources = &clkset_group, | |
859 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, | |
860 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, | |
861 | }, { | |
862 | .clk = { | |
863 | .name = "uclk1", | |
864 | .devname = "s5pv210-uart.3", | |
865 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
866 | .ctrlbit = (1 << 12), | |
867 | }, | |
868 | .sources = &clkset_group, | |
869 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, | |
870 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, | |
871 | }, { | |
872 | .clk = { | |
873 | .name = "sclk_pwm", | |
874 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
875 | .ctrlbit = (1 << 24), | |
876 | }, | |
877 | .sources = &clkset_group, | |
878 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, | |
879 | .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, | |
880 | }, { | |
881 | .clk = { | |
882 | .name = "sclk_csis", | |
883 | .devname = "s5p-mipi-csis.0", | |
884 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
885 | .ctrlbit = (1 << 24), | |
886 | }, | |
887 | .sources = &clkset_group, | |
888 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, | |
889 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, | |
890 | }, { | |
891 | .clk = { | |
892 | .name = "sclk_csis", | |
893 | .devname = "s5p-mipi-csis.1", | |
894 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
895 | .ctrlbit = (1 << 28), | |
896 | }, | |
897 | .sources = &clkset_group, | |
898 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, | |
899 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, | |
900 | }, { | |
901 | .clk = { | |
902 | .name = "sclk_cam", | |
903 | .devname = "exynos4-fimc.0", | |
904 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
905 | .ctrlbit = (1 << 16), | |
906 | }, | |
907 | .sources = &clkset_group, | |
908 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, | |
909 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, | |
910 | }, { | |
911 | .clk = { | |
912 | .name = "sclk_cam", | |
913 | .devname = "exynos4-fimc.1", | |
914 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
915 | .ctrlbit = (1 << 20), | |
916 | }, | |
917 | .sources = &clkset_group, | |
918 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, | |
919 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, | |
920 | }, { | |
921 | .clk = { | |
922 | .name = "sclk_fimc", | |
923 | .devname = "exynos4-fimc.0", | |
924 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
925 | .ctrlbit = (1 << 0), | |
926 | }, | |
927 | .sources = &clkset_group, | |
928 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, | |
929 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, | |
930 | }, { | |
931 | .clk = { | |
932 | .name = "sclk_fimc", | |
933 | .devname = "exynos4-fimc.1", | |
934 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
935 | .ctrlbit = (1 << 4), | |
936 | }, | |
937 | .sources = &clkset_group, | |
938 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, | |
939 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, | |
940 | }, { | |
941 | .clk = { | |
942 | .name = "sclk_fimc", | |
943 | .devname = "exynos4-fimc.2", | |
944 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
945 | .ctrlbit = (1 << 8), | |
946 | }, | |
947 | .sources = &clkset_group, | |
948 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, | |
949 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, | |
950 | }, { | |
951 | .clk = { | |
952 | .name = "sclk_fimc", | |
953 | .devname = "exynos4-fimc.3", | |
954 | .enable = exynos4_clksrc_mask_cam_ctrl, | |
955 | .ctrlbit = (1 << 12), | |
956 | }, | |
957 | .sources = &clkset_group, | |
958 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, | |
959 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, | |
960 | }, { | |
961 | .clk = { | |
962 | .name = "sclk_fimd", | |
963 | .devname = "exynos4-fb.0", | |
964 | .enable = exynos4_clksrc_mask_lcd0_ctrl, | |
965 | .ctrlbit = (1 << 0), | |
966 | }, | |
967 | .sources = &clkset_group, | |
968 | .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, | |
969 | .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, | |
970 | }, { | |
971 | .clk = { | |
972 | .name = "sclk_fimd", | |
973 | .devname = "exynos4-fb.1", | |
974 | .enable = exynos4_clksrc_mask_lcd1_ctrl, | |
975 | .ctrlbit = (1 << 0), | |
976 | }, | |
977 | .sources = &clkset_group, | |
978 | .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, | |
979 | .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, | |
980 | }, { | |
981 | .clk = { | |
982 | .name = "sclk_sata", | |
983 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
984 | .ctrlbit = (1 << 24), | |
985 | }, | |
986 | .sources = &clkset_mout_corebus, | |
987 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, | |
988 | .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, | |
989 | }, { | |
990 | .clk = { | |
991 | .name = "sclk_spi", | |
992 | .devname = "s3c64xx-spi.0", | |
993 | .enable = exynos4_clksrc_mask_peril1_ctrl, | |
994 | .ctrlbit = (1 << 16), | |
995 | }, | |
996 | .sources = &clkset_group, | |
997 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | |
998 | .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | |
999 | }, { | |
1000 | .clk = { | |
1001 | .name = "sclk_spi", | |
1002 | .devname = "s3c64xx-spi.1", | |
1003 | .enable = exynos4_clksrc_mask_peril1_ctrl, | |
1004 | .ctrlbit = (1 << 20), | |
1005 | }, | |
1006 | .sources = &clkset_group, | |
1007 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | |
1008 | .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | |
1009 | }, { | |
1010 | .clk = { | |
1011 | .name = "sclk_spi", | |
1012 | .devname = "s3c64xx-spi.2", | |
1013 | .enable = exynos4_clksrc_mask_peril1_ctrl, | |
1014 | .ctrlbit = (1 << 24), | |
1015 | }, | |
1016 | .sources = &clkset_group, | |
1017 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | |
1018 | .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | |
1019 | }, { | |
1020 | .clk = { | |
1021 | .name = "sclk_fimg2d", | |
1022 | }, | |
1023 | .sources = &clkset_mout_g2d, | |
1024 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | |
1025 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | |
1026 | }, { | |
1027 | .clk = { | |
1028 | .name = "sclk_mfc", | |
1029 | .devname = "s5p-mfc", | |
1030 | }, | |
1031 | .sources = &clkset_mout_mfc, | |
1032 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, | |
1033 | .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, | |
1034 | }, { | |
1035 | .clk = { | |
1036 | .name = "sclk_mmc", | |
1037 | .devname = "s3c-sdhci.0", | |
1038 | .parent = &clk_dout_mmc0.clk, | |
1039 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
1040 | .ctrlbit = (1 << 0), | |
1041 | }, | |
1042 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, | |
1043 | }, { | |
1044 | .clk = { | |
1045 | .name = "sclk_mmc", | |
1046 | .devname = "s3c-sdhci.1", | |
1047 | .parent = &clk_dout_mmc1.clk, | |
1048 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
1049 | .ctrlbit = (1 << 4), | |
1050 | }, | |
1051 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, | |
1052 | }, { | |
1053 | .clk = { | |
1054 | .name = "sclk_mmc", | |
1055 | .devname = "s3c-sdhci.2", | |
1056 | .parent = &clk_dout_mmc2.clk, | |
1057 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
1058 | .ctrlbit = (1 << 8), | |
1059 | }, | |
1060 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, | |
1061 | }, { | |
1062 | .clk = { | |
1063 | .name = "sclk_mmc", | |
1064 | .devname = "s3c-sdhci.3", | |
1065 | .parent = &clk_dout_mmc3.clk, | |
1066 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
1067 | .ctrlbit = (1 << 12), | |
1068 | }, | |
1069 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | |
1070 | }, { | |
1071 | .clk = { | |
1072 | .name = "sclk_dwmmc", | |
1073 | .parent = &clk_dout_mmc4.clk, | |
1074 | .enable = exynos4_clksrc_mask_fsys_ctrl, | |
1075 | .ctrlbit = (1 << 16), | |
1076 | }, | |
1077 | .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, | |
1078 | } | |
1079 | }; | |
1080 | ||
1081 | /* Clock initialization code */ | |
1082 | static struct clksrc_clk *sysclks[] = { | |
1083 | &clk_mout_apll, | |
1084 | &clk_sclk_apll, | |
1085 | &clk_mout_epll, | |
1086 | &clk_mout_mpll, | |
1087 | &clk_moutcore, | |
1088 | &clk_coreclk, | |
1089 | &clk_armclk, | |
1090 | &clk_aclk_corem0, | |
1091 | &clk_aclk_cores, | |
1092 | &clk_aclk_corem1, | |
1093 | &clk_periphclk, | |
1094 | &clk_mout_corebus, | |
1095 | &clk_sclk_dmc, | |
1096 | &clk_aclk_cored, | |
1097 | &clk_aclk_corep, | |
1098 | &clk_aclk_acp, | |
1099 | &clk_pclk_acp, | |
1100 | &clk_vpllsrc, | |
1101 | &clk_sclk_vpll, | |
1102 | &clk_aclk_200, | |
1103 | &clk_aclk_100, | |
1104 | &clk_aclk_160, | |
1105 | &clk_aclk_133, | |
1106 | &clk_dout_mmc0, | |
1107 | &clk_dout_mmc1, | |
1108 | &clk_dout_mmc2, | |
1109 | &clk_dout_mmc3, | |
1110 | &clk_dout_mmc4, | |
1111 | &clk_mout_mfc0, | |
1112 | &clk_mout_mfc1, | |
1113 | }; | |
1114 | ||
1115 | static int xtal_rate; | |
1116 | ||
1117 | static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) | |
1118 | { | |
1119 | return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); | |
1120 | } | |
1121 | ||
1122 | static struct clk_ops exynos4_fout_apll_ops = { | |
1123 | .get_rate = exynos4_fout_apll_get_rate, | |
1124 | }; | |
1125 | ||
1126 | void __init_or_cpufreq exynos4_setup_clocks(void) | |
1127 | { | |
1128 | struct clk *xtal_clk; | |
1129 | unsigned long apll; | |
1130 | unsigned long mpll; | |
1131 | unsigned long epll; | |
1132 | unsigned long vpll; | |
1133 | unsigned long vpllsrc; | |
1134 | unsigned long xtal; | |
1135 | unsigned long armclk; | |
1136 | unsigned long sclk_dmc; | |
1137 | unsigned long aclk_200; | |
1138 | unsigned long aclk_100; | |
1139 | unsigned long aclk_160; | |
1140 | unsigned long aclk_133; | |
1141 | unsigned int ptr; | |
1142 | ||
1143 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1144 | ||
1145 | xtal_clk = clk_get(NULL, "xtal"); | |
1146 | BUG_ON(IS_ERR(xtal_clk)); | |
1147 | ||
1148 | xtal = clk_get_rate(xtal_clk); | |
1149 | ||
1150 | xtal_rate = xtal; | |
1151 | ||
1152 | clk_put(xtal_clk); | |
1153 | ||
1154 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1155 | ||
1156 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); | |
1157 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); | |
1158 | epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), | |
1159 | __raw_readl(S5P_EPLL_CON1), pll_4600); | |
1160 | ||
1161 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); | |
1162 | vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), | |
1163 | __raw_readl(S5P_VPLL_CON1), pll_4650c); | |
1164 | ||
1165 | clk_fout_apll.ops = &exynos4_fout_apll_ops; | |
1166 | clk_fout_mpll.rate = mpll; | |
1167 | clk_fout_epll.rate = epll; | |
1168 | clk_fout_vpll.rate = vpll; | |
1169 | ||
1170 | printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", | |
1171 | apll, mpll, epll, vpll); | |
1172 | ||
1173 | armclk = clk_get_rate(&clk_armclk.clk); | |
1174 | sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); | |
1175 | ||
1176 | aclk_200 = clk_get_rate(&clk_aclk_200.clk); | |
1177 | aclk_100 = clk_get_rate(&clk_aclk_100.clk); | |
1178 | aclk_160 = clk_get_rate(&clk_aclk_160.clk); | |
1179 | aclk_133 = clk_get_rate(&clk_aclk_133.clk); | |
1180 | ||
1181 | printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" | |
1182 | "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", | |
1183 | armclk, sclk_dmc, aclk_200, | |
1184 | aclk_100, aclk_160, aclk_133); | |
1185 | ||
1186 | clk_f.rate = armclk; | |
1187 | clk_h.rate = sclk_dmc; | |
1188 | clk_p.rate = aclk_100; | |
1189 | ||
1190 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
1191 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1192 | } | |
1193 | ||
1194 | static struct clk *clks[] __initdata = { | |
1195 | /* Nothing here yet */ | |
1196 | }; | |
1197 | ||
1198 | void __init exynos4_register_clocks(void) | |
1199 | { | |
1200 | int ptr; | |
1201 | ||
1202 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | |
1203 | ||
1204 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
1205 | s3c_register_clksrc(sysclks[ptr], 1); | |
1206 | ||
1207 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
1208 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1209 | ||
1210 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
1211 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
1212 | ||
1213 | s3c_pwmclk_init(); | |
1214 | } |