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1 | # SPDX-License-Identifier: GPL-2.0 | |
2 | comment "Processor Type" | |
3 | ||
4 | # Select CPU types depending on the architecture selected. This selects | |
5 | # which CPUs we support in the kernel image, and the compiler instruction | |
6 | # optimiser behaviour. | |
7 | ||
8 | # ARM7TDMI | |
9 | config CPU_ARM7TDMI | |
10 | bool | |
11 | depends on !MMU | |
12 | select CPU_32v4T | |
13 | select CPU_ABRT_LV4T | |
14 | select CPU_CACHE_V4 | |
15 | select CPU_PABRT_LEGACY | |
16 | help | |
17 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
18 | which has no memory control unit and cache. | |
19 | ||
20 | Say Y if you want support for the ARM7TDMI processor. | |
21 | Otherwise, say N. | |
22 | ||
23 | # ARM720T | |
24 | config CPU_ARM720T | |
25 | bool | |
26 | select CPU_32v4T | |
27 | select CPU_ABRT_LV4T | |
28 | select CPU_CACHE_V4 | |
29 | select CPU_CACHE_VIVT | |
30 | select CPU_COPY_V4WT if MMU | |
31 | select CPU_CP15_MMU | |
32 | select CPU_PABRT_LEGACY | |
33 | select CPU_THUMB_CAPABLE | |
34 | select CPU_TLB_V4WT if MMU | |
35 | help | |
36 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
37 | MMU built around an ARM7TDMI core. | |
38 | ||
39 | Say Y if you want support for the ARM720T processor. | |
40 | Otherwise, say N. | |
41 | ||
42 | # ARM740T | |
43 | config CPU_ARM740T | |
44 | bool | |
45 | depends on !MMU | |
46 | select CPU_32v4T | |
47 | select CPU_ABRT_LV4T | |
48 | select CPU_CACHE_V4 | |
49 | select CPU_CP15_MPU | |
50 | select CPU_PABRT_LEGACY | |
51 | select CPU_THUMB_CAPABLE | |
52 | help | |
53 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
54 | write buffer and MPU(Protection Unit) built around | |
55 | an ARM7TDMI core. | |
56 | ||
57 | Say Y if you want support for the ARM740T processor. | |
58 | Otherwise, say N. | |
59 | ||
60 | # ARM9TDMI | |
61 | config CPU_ARM9TDMI | |
62 | bool | |
63 | depends on !MMU | |
64 | select CPU_32v4T | |
65 | select CPU_ABRT_NOMMU | |
66 | select CPU_CACHE_V4 | |
67 | select CPU_PABRT_LEGACY | |
68 | help | |
69 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
70 | which has no memory control unit and cache. | |
71 | ||
72 | Say Y if you want support for the ARM9TDMI processor. | |
73 | Otherwise, say N. | |
74 | ||
75 | # ARM920T | |
76 | config CPU_ARM920T | |
77 | bool | |
78 | select CPU_32v4T | |
79 | select CPU_ABRT_EV4T | |
80 | select CPU_CACHE_V4WT | |
81 | select CPU_CACHE_VIVT | |
82 | select CPU_COPY_V4WB if MMU | |
83 | select CPU_CP15_MMU | |
84 | select CPU_PABRT_LEGACY | |
85 | select CPU_THUMB_CAPABLE | |
86 | select CPU_TLB_V4WBI if MMU | |
87 | help | |
88 | The ARM920T is licensed to be produced by numerous vendors, | |
89 | and is used in the Cirrus EP93xx and the Samsung S3C2410. | |
90 | ||
91 | Say Y if you want support for the ARM920T processor. | |
92 | Otherwise, say N. | |
93 | ||
94 | # ARM922T | |
95 | config CPU_ARM922T | |
96 | bool | |
97 | select CPU_32v4T | |
98 | select CPU_ABRT_EV4T | |
99 | select CPU_CACHE_V4WT | |
100 | select CPU_CACHE_VIVT | |
101 | select CPU_COPY_V4WB if MMU | |
102 | select CPU_CP15_MMU | |
103 | select CPU_PABRT_LEGACY | |
104 | select CPU_THUMB_CAPABLE | |
105 | select CPU_TLB_V4WBI if MMU | |
106 | help | |
107 | The ARM922T is a version of the ARM920T, but with smaller | |
108 | instruction and data caches. It is used in Altera's | |
109 | Excalibur XA device family and Micrel's KS8695 Centaur. | |
110 | ||
111 | Say Y if you want support for the ARM922T processor. | |
112 | Otherwise, say N. | |
113 | ||
114 | # ARM925T | |
115 | config CPU_ARM925T | |
116 | bool | |
117 | select CPU_32v4T | |
118 | select CPU_ABRT_EV4T | |
119 | select CPU_CACHE_V4WT | |
120 | select CPU_CACHE_VIVT | |
121 | select CPU_COPY_V4WB if MMU | |
122 | select CPU_CP15_MMU | |
123 | select CPU_PABRT_LEGACY | |
124 | select CPU_THUMB_CAPABLE | |
125 | select CPU_TLB_V4WBI if MMU | |
126 | help | |
127 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
128 | different instruction and data caches. It is used in TI's OMAP | |
129 | device family. | |
130 | ||
131 | Say Y if you want support for the ARM925T processor. | |
132 | Otherwise, say N. | |
133 | ||
134 | # ARM926T | |
135 | config CPU_ARM926T | |
136 | bool | |
137 | select CPU_32v5 | |
138 | select CPU_ABRT_EV5TJ | |
139 | select CPU_CACHE_VIVT | |
140 | select CPU_COPY_V4WB if MMU | |
141 | select CPU_CP15_MMU | |
142 | select CPU_PABRT_LEGACY | |
143 | select CPU_THUMB_CAPABLE | |
144 | select CPU_TLB_V4WBI if MMU | |
145 | help | |
146 | This is a variant of the ARM920. It has slightly different | |
147 | instruction sequences for cache and TLB operations. Curiously, | |
148 | there is no documentation on it at the ARM corporate website. | |
149 | ||
150 | Say Y if you want support for the ARM926T processor. | |
151 | Otherwise, say N. | |
152 | ||
153 | # FA526 | |
154 | config CPU_FA526 | |
155 | bool | |
156 | select CPU_32v4 | |
157 | select CPU_ABRT_EV4 | |
158 | select CPU_CACHE_FA | |
159 | select CPU_CACHE_VIVT | |
160 | select CPU_COPY_FA if MMU | |
161 | select CPU_CP15_MMU | |
162 | select CPU_PABRT_LEGACY | |
163 | select CPU_TLB_FA if MMU | |
164 | help | |
165 | The FA526 is a version of the ARMv4 compatible processor with | |
166 | Branch Target Buffer, Unified TLB and cache line size 16. | |
167 | ||
168 | Say Y if you want support for the FA526 processor. | |
169 | Otherwise, say N. | |
170 | ||
171 | # ARM940T | |
172 | config CPU_ARM940T | |
173 | bool | |
174 | depends on !MMU | |
175 | select CPU_32v4T | |
176 | select CPU_ABRT_NOMMU | |
177 | select CPU_CACHE_VIVT | |
178 | select CPU_CP15_MPU | |
179 | select CPU_PABRT_LEGACY | |
180 | select CPU_THUMB_CAPABLE | |
181 | help | |
182 | ARM940T is a member of the ARM9TDMI family of general- | |
183 | purpose microprocessors with MPU and separate 4KB | |
184 | instruction and 4KB data cases, each with a 4-word line | |
185 | length. | |
186 | ||
187 | Say Y if you want support for the ARM940T processor. | |
188 | Otherwise, say N. | |
189 | ||
190 | # ARM946E-S | |
191 | config CPU_ARM946E | |
192 | bool | |
193 | depends on !MMU | |
194 | select CPU_32v5 | |
195 | select CPU_ABRT_NOMMU | |
196 | select CPU_CACHE_VIVT | |
197 | select CPU_CP15_MPU | |
198 | select CPU_PABRT_LEGACY | |
199 | select CPU_THUMB_CAPABLE | |
200 | help | |
201 | ARM946E-S is a member of the ARM9E-S family of high- | |
202 | performance, 32-bit system-on-chip processor solutions. | |
203 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
204 | ||
205 | Say Y if you want support for the ARM946E-S processor. | |
206 | Otherwise, say N. | |
207 | ||
208 | # ARM1020 - needs validating | |
209 | config CPU_ARM1020 | |
210 | bool | |
211 | select CPU_32v5 | |
212 | select CPU_ABRT_EV4T | |
213 | select CPU_CACHE_V4WT | |
214 | select CPU_CACHE_VIVT | |
215 | select CPU_COPY_V4WB if MMU | |
216 | select CPU_CP15_MMU | |
217 | select CPU_PABRT_LEGACY | |
218 | select CPU_THUMB_CAPABLE | |
219 | select CPU_TLB_V4WBI if MMU | |
220 | help | |
221 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
222 | with an addition of a floating-point unit. | |
223 | ||
224 | Say Y if you want support for the ARM1020 processor. | |
225 | Otherwise, say N. | |
226 | ||
227 | # ARM1020E - needs validating | |
228 | config CPU_ARM1020E | |
229 | bool | |
230 | depends on n | |
231 | select CPU_32v5 | |
232 | select CPU_ABRT_EV4T | |
233 | select CPU_CACHE_V4WT | |
234 | select CPU_CACHE_VIVT | |
235 | select CPU_COPY_V4WB if MMU | |
236 | select CPU_CP15_MMU | |
237 | select CPU_PABRT_LEGACY | |
238 | select CPU_THUMB_CAPABLE | |
239 | select CPU_TLB_V4WBI if MMU | |
240 | ||
241 | # ARM1022E | |
242 | config CPU_ARM1022 | |
243 | bool | |
244 | select CPU_32v5 | |
245 | select CPU_ABRT_EV4T | |
246 | select CPU_CACHE_VIVT | |
247 | select CPU_COPY_V4WB if MMU # can probably do better | |
248 | select CPU_CP15_MMU | |
249 | select CPU_PABRT_LEGACY | |
250 | select CPU_THUMB_CAPABLE | |
251 | select CPU_TLB_V4WBI if MMU | |
252 | help | |
253 | The ARM1022E is an implementation of the ARMv5TE architecture | |
254 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
255 | embedded trace macrocell, and a floating-point unit. | |
256 | ||
257 | Say Y if you want support for the ARM1022E processor. | |
258 | Otherwise, say N. | |
259 | ||
260 | # ARM1026EJ-S | |
261 | config CPU_ARM1026 | |
262 | bool | |
263 | select CPU_32v5 | |
264 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
265 | select CPU_CACHE_VIVT | |
266 | select CPU_COPY_V4WB if MMU # can probably do better | |
267 | select CPU_CP15_MMU | |
268 | select CPU_PABRT_LEGACY | |
269 | select CPU_THUMB_CAPABLE | |
270 | select CPU_TLB_V4WBI if MMU | |
271 | help | |
272 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
273 | based upon the ARM10 integer core. | |
274 | ||
275 | Say Y if you want support for the ARM1026EJ-S processor. | |
276 | Otherwise, say N. | |
277 | ||
278 | # SA110 | |
279 | config CPU_SA110 | |
280 | bool | |
281 | select CPU_32v3 if ARCH_RPC | |
282 | select CPU_32v4 if !ARCH_RPC | |
283 | select CPU_ABRT_EV4 | |
284 | select CPU_CACHE_V4WB | |
285 | select CPU_CACHE_VIVT | |
286 | select CPU_COPY_V4WB if MMU | |
287 | select CPU_CP15_MMU | |
288 | select CPU_PABRT_LEGACY | |
289 | select CPU_TLB_V4WB if MMU | |
290 | help | |
291 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
292 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
293 | More information is available at | |
294 | <http://developer.intel.com/design/strong/sa110.htm>. | |
295 | ||
296 | Say Y if you want support for the SA-110 processor. | |
297 | Otherwise, say N. | |
298 | ||
299 | # SA1100 | |
300 | config CPU_SA1100 | |
301 | bool | |
302 | select CPU_32v4 | |
303 | select CPU_ABRT_EV4 | |
304 | select CPU_CACHE_V4WB | |
305 | select CPU_CACHE_VIVT | |
306 | select CPU_CP15_MMU | |
307 | select CPU_PABRT_LEGACY | |
308 | select CPU_TLB_V4WB if MMU | |
309 | ||
310 | # XScale | |
311 | config CPU_XSCALE | |
312 | bool | |
313 | select CPU_32v5 | |
314 | select CPU_ABRT_EV5T | |
315 | select CPU_CACHE_VIVT | |
316 | select CPU_CP15_MMU | |
317 | select CPU_PABRT_LEGACY | |
318 | select CPU_THUMB_CAPABLE | |
319 | select CPU_TLB_V4WBI if MMU | |
320 | ||
321 | # XScale Core Version 3 | |
322 | config CPU_XSC3 | |
323 | bool | |
324 | select CPU_32v5 | |
325 | select CPU_ABRT_EV5T | |
326 | select CPU_CACHE_VIVT | |
327 | select CPU_CP15_MMU | |
328 | select CPU_PABRT_LEGACY | |
329 | select CPU_THUMB_CAPABLE | |
330 | select CPU_TLB_V4WBI if MMU | |
331 | select IO_36 | |
332 | ||
333 | # Marvell PJ1 (Mohawk) | |
334 | config CPU_MOHAWK | |
335 | bool | |
336 | select CPU_32v5 | |
337 | select CPU_ABRT_EV5T | |
338 | select CPU_CACHE_VIVT | |
339 | select CPU_COPY_V4WB if MMU | |
340 | select CPU_CP15_MMU | |
341 | select CPU_PABRT_LEGACY | |
342 | select CPU_THUMB_CAPABLE | |
343 | select CPU_TLB_V4WBI if MMU | |
344 | ||
345 | # Feroceon | |
346 | config CPU_FEROCEON | |
347 | bool | |
348 | select CPU_32v5 | |
349 | select CPU_ABRT_EV5T | |
350 | select CPU_CACHE_VIVT | |
351 | select CPU_COPY_FEROCEON if MMU | |
352 | select CPU_CP15_MMU | |
353 | select CPU_PABRT_LEGACY | |
354 | select CPU_THUMB_CAPABLE | |
355 | select CPU_TLB_FEROCEON if MMU | |
356 | ||
357 | config CPU_FEROCEON_OLD_ID | |
358 | bool "Accept early Feroceon cores with an ARM926 ID" | |
359 | depends on CPU_FEROCEON && !CPU_ARM926T | |
360 | default y | |
361 | help | |
362 | This enables the usage of some old Feroceon cores | |
363 | for which the CPU ID is equal to the ARM926 ID. | |
364 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
365 | ||
366 | # Marvell PJ4 | |
367 | config CPU_PJ4 | |
368 | bool | |
369 | select ARM_THUMBEE | |
370 | select CPU_V7 | |
371 | ||
372 | config CPU_PJ4B | |
373 | bool | |
374 | select CPU_V7 | |
375 | ||
376 | # ARMv6 | |
377 | config CPU_V6 | |
378 | bool | |
379 | select CPU_32v6 | |
380 | select CPU_ABRT_EV6 | |
381 | select CPU_CACHE_V6 | |
382 | select CPU_CACHE_VIPT | |
383 | select CPU_COPY_V6 if MMU | |
384 | select CPU_CP15_MMU | |
385 | select CPU_HAS_ASID if MMU | |
386 | select CPU_PABRT_V6 | |
387 | select CPU_THUMB_CAPABLE | |
388 | select CPU_TLB_V6 if MMU | |
389 | ||
390 | # ARMv6k | |
391 | config CPU_V6K | |
392 | bool | |
393 | select CPU_32v6 | |
394 | select CPU_32v6K | |
395 | select CPU_ABRT_EV6 | |
396 | select CPU_CACHE_V6 | |
397 | select CPU_CACHE_VIPT | |
398 | select CPU_COPY_V6 if MMU | |
399 | select CPU_CP15_MMU | |
400 | select CPU_HAS_ASID if MMU | |
401 | select CPU_PABRT_V6 | |
402 | select CPU_THUMB_CAPABLE | |
403 | select CPU_TLB_V6 if MMU | |
404 | ||
405 | # ARMv7 | |
406 | config CPU_V7 | |
407 | bool | |
408 | select CPU_32v6K | |
409 | select CPU_32v7 | |
410 | select CPU_ABRT_EV7 | |
411 | select CPU_CACHE_V7 | |
412 | select CPU_CACHE_VIPT | |
413 | select CPU_COPY_V6 if MMU | |
414 | select CPU_CP15_MMU if MMU | |
415 | select CPU_CP15_MPU if !MMU | |
416 | select CPU_HAS_ASID if MMU | |
417 | select CPU_PABRT_V7 | |
418 | select CPU_SPECTRE if MMU | |
419 | select CPU_THUMB_CAPABLE | |
420 | select CPU_TLB_V7 if MMU | |
421 | ||
422 | # ARMv7M | |
423 | config CPU_V7M | |
424 | bool | |
425 | select CPU_32v7M | |
426 | select CPU_ABRT_NOMMU | |
427 | select CPU_CACHE_V7M | |
428 | select CPU_CACHE_NOP | |
429 | select CPU_PABRT_LEGACY | |
430 | select CPU_THUMBONLY | |
431 | ||
432 | config CPU_THUMBONLY | |
433 | bool | |
434 | select CPU_THUMB_CAPABLE | |
435 | # There are no CPUs available with MMU that don't implement an ARM ISA: | |
436 | depends on !MMU | |
437 | help | |
438 | Select this if your CPU doesn't support the 32 bit ARM instructions. | |
439 | ||
440 | config CPU_THUMB_CAPABLE | |
441 | bool | |
442 | help | |
443 | Select this if your CPU can support Thumb mode. | |
444 | ||
445 | # Figure out what processor architecture version we should be using. | |
446 | # This defines the compiler instruction set which depends on the machine type. | |
447 | config CPU_32v3 | |
448 | bool | |
449 | select CPU_USE_DOMAINS if MMU | |
450 | select NEED_KUSER_HELPERS | |
451 | select TLS_REG_EMUL if SMP || !MMU | |
452 | select CPU_NO_EFFICIENT_FFS | |
453 | ||
454 | config CPU_32v4 | |
455 | bool | |
456 | select CPU_USE_DOMAINS if MMU | |
457 | select NEED_KUSER_HELPERS | |
458 | select TLS_REG_EMUL if SMP || !MMU | |
459 | select CPU_NO_EFFICIENT_FFS | |
460 | ||
461 | config CPU_32v4T | |
462 | bool | |
463 | select CPU_USE_DOMAINS if MMU | |
464 | select NEED_KUSER_HELPERS | |
465 | select TLS_REG_EMUL if SMP || !MMU | |
466 | select CPU_NO_EFFICIENT_FFS | |
467 | ||
468 | config CPU_32v5 | |
469 | bool | |
470 | select CPU_USE_DOMAINS if MMU | |
471 | select NEED_KUSER_HELPERS | |
472 | select TLS_REG_EMUL if SMP || !MMU | |
473 | ||
474 | config CPU_32v6 | |
475 | bool | |
476 | select TLS_REG_EMUL if !CPU_32v6K && !MMU | |
477 | ||
478 | config CPU_32v6K | |
479 | bool | |
480 | ||
481 | config CPU_32v7 | |
482 | bool | |
483 | ||
484 | config CPU_32v7M | |
485 | bool | |
486 | ||
487 | # The abort model | |
488 | config CPU_ABRT_NOMMU | |
489 | bool | |
490 | ||
491 | config CPU_ABRT_EV4 | |
492 | bool | |
493 | ||
494 | config CPU_ABRT_EV4T | |
495 | bool | |
496 | ||
497 | config CPU_ABRT_LV4T | |
498 | bool | |
499 | ||
500 | config CPU_ABRT_EV5T | |
501 | bool | |
502 | ||
503 | config CPU_ABRT_EV5TJ | |
504 | bool | |
505 | ||
506 | config CPU_ABRT_EV6 | |
507 | bool | |
508 | ||
509 | config CPU_ABRT_EV7 | |
510 | bool | |
511 | ||
512 | config CPU_PABRT_LEGACY | |
513 | bool | |
514 | ||
515 | config CPU_PABRT_V6 | |
516 | bool | |
517 | ||
518 | config CPU_PABRT_V7 | |
519 | bool | |
520 | ||
521 | # The cache model | |
522 | config CPU_CACHE_V4 | |
523 | bool | |
524 | ||
525 | config CPU_CACHE_V4WT | |
526 | bool | |
527 | ||
528 | config CPU_CACHE_V4WB | |
529 | bool | |
530 | ||
531 | config CPU_CACHE_V6 | |
532 | bool | |
533 | ||
534 | config CPU_CACHE_V7 | |
535 | bool | |
536 | ||
537 | config CPU_CACHE_NOP | |
538 | bool | |
539 | ||
540 | config CPU_CACHE_VIVT | |
541 | bool | |
542 | ||
543 | config CPU_CACHE_VIPT | |
544 | bool | |
545 | ||
546 | config CPU_CACHE_FA | |
547 | bool | |
548 | ||
549 | config CPU_CACHE_V7M | |
550 | bool | |
551 | ||
552 | if MMU | |
553 | # The copy-page model | |
554 | config CPU_COPY_V4WT | |
555 | bool | |
556 | ||
557 | config CPU_COPY_V4WB | |
558 | bool | |
559 | ||
560 | config CPU_COPY_FEROCEON | |
561 | bool | |
562 | ||
563 | config CPU_COPY_FA | |
564 | bool | |
565 | ||
566 | config CPU_COPY_V6 | |
567 | bool | |
568 | ||
569 | # This selects the TLB model | |
570 | config CPU_TLB_V4WT | |
571 | bool | |
572 | help | |
573 | ARM Architecture Version 4 TLB with writethrough cache. | |
574 | ||
575 | config CPU_TLB_V4WB | |
576 | bool | |
577 | help | |
578 | ARM Architecture Version 4 TLB with writeback cache. | |
579 | ||
580 | config CPU_TLB_V4WBI | |
581 | bool | |
582 | help | |
583 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
584 | instruction cache entry. | |
585 | ||
586 | config CPU_TLB_FEROCEON | |
587 | bool | |
588 | help | |
589 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
590 | ||
591 | config CPU_TLB_FA | |
592 | bool | |
593 | help | |
594 | Faraday ARM FA526 architecture, unified TLB with writeback cache | |
595 | and invalidate instruction cache entry. Branch target buffer is | |
596 | also supported. | |
597 | ||
598 | config CPU_TLB_V6 | |
599 | bool | |
600 | ||
601 | config CPU_TLB_V7 | |
602 | bool | |
603 | ||
604 | config VERIFY_PERMISSION_FAULT | |
605 | bool | |
606 | endif | |
607 | ||
608 | config CPU_HAS_ASID | |
609 | bool | |
610 | help | |
611 | This indicates whether the CPU has the ASID register; used to | |
612 | tag TLB and possibly cache entries. | |
613 | ||
614 | config CPU_CP15 | |
615 | bool | |
616 | help | |
617 | Processor has the CP15 register. | |
618 | ||
619 | config CPU_CP15_MMU | |
620 | bool | |
621 | select CPU_CP15 | |
622 | help | |
623 | Processor has the CP15 register, which has MMU related registers. | |
624 | ||
625 | config CPU_CP15_MPU | |
626 | bool | |
627 | select CPU_CP15 | |
628 | help | |
629 | Processor has the CP15 register, which has MPU related registers. | |
630 | ||
631 | config CPU_USE_DOMAINS | |
632 | bool | |
633 | help | |
634 | This option enables or disables the use of domain switching | |
635 | via the set_fs() function. | |
636 | ||
637 | config CPU_V7M_NUM_IRQ | |
638 | int "Number of external interrupts connected to the NVIC" | |
639 | depends on CPU_V7M | |
640 | default 90 if ARCH_STM32 | |
641 | default 38 if ARCH_EFM32 | |
642 | default 112 if SOC_VF610 | |
643 | default 240 | |
644 | help | |
645 | This option indicates the number of interrupts connected to the NVIC. | |
646 | The value can be larger than the real number of interrupts supported | |
647 | by the system, but must not be lower. | |
648 | The default value is 240, corresponding to the maximum number of | |
649 | interrupts supported by the NVIC on Cortex-M family. | |
650 | ||
651 | If unsure, keep default value. | |
652 | ||
653 | # | |
654 | # CPU supports 36-bit I/O | |
655 | # | |
656 | config IO_36 | |
657 | bool | |
658 | ||
659 | comment "Processor Features" | |
660 | ||
661 | config ARM_LPAE | |
662 | bool "Support for the Large Physical Address Extension" | |
663 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ | |
664 | !CPU_32v4 && !CPU_32v3 | |
665 | help | |
666 | Say Y if you have an ARMv7 processor supporting the LPAE page | |
667 | table format and you would like to access memory beyond the | |
668 | 4GB limit. The resulting kernel image will not run on | |
669 | processors without the LPA extension. | |
670 | ||
671 | If unsure, say N. | |
672 | ||
673 | config ARM_PV_FIXUP | |
674 | def_bool y | |
675 | depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE | |
676 | ||
677 | config ARCH_PHYS_ADDR_T_64BIT | |
678 | def_bool ARM_LPAE | |
679 | ||
680 | config ARCH_DMA_ADDR_T_64BIT | |
681 | bool | |
682 | ||
683 | config ARM_THUMB | |
684 | bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT | |
685 | depends on CPU_THUMB_CAPABLE | |
686 | default y | |
687 | help | |
688 | Say Y if you want to include kernel support for running user space | |
689 | Thumb binaries. | |
690 | ||
691 | The Thumb instruction set is a compressed form of the standard ARM | |
692 | instruction set resulting in smaller binaries at the expense of | |
693 | slightly less efficient code. | |
694 | ||
695 | If this option is disabled, and you run userspace that switches to | |
696 | Thumb mode, signal handling will not work correctly, resulting in | |
697 | segmentation faults or illegal instruction aborts. | |
698 | ||
699 | If you don't know what this all is, saying Y is a safe choice. | |
700 | ||
701 | config ARM_THUMBEE | |
702 | bool "Enable ThumbEE CPU extension" | |
703 | depends on CPU_V7 | |
704 | help | |
705 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
706 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
707 | ||
708 | config ARM_VIRT_EXT | |
709 | bool | |
710 | depends on MMU | |
711 | default y if CPU_V7 | |
712 | help | |
713 | Enable the kernel to make use of the ARM Virtualization | |
714 | Extensions to install hypervisors without run-time firmware | |
715 | assistance. | |
716 | ||
717 | A compliant bootloader is required in order to make maximum | |
718 | use of this feature. Refer to Documentation/arm/Booting for | |
719 | details. | |
720 | ||
721 | config SWP_EMULATE | |
722 | bool "Emulate SWP/SWPB instructions" if !SMP | |
723 | depends on CPU_V7 | |
724 | default y if SMP | |
725 | select HAVE_PROC_CPU if PROC_FS | |
726 | help | |
727 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | |
728 | ARMv7 multiprocessing extensions introduce the ability to disable | |
729 | these instructions, triggering an undefined instruction exception | |
730 | when executed. Say Y here to enable software emulation of these | |
731 | instructions for userspace (not kernel) using LDREX/STREX. | |
732 | Also creates /proc/cpu/swp_emulation for statistics. | |
733 | ||
734 | In some older versions of glibc [<=2.8] SWP is used during futex | |
735 | trylock() operations with the assumption that the code will not | |
736 | be preempted. This invalid assumption may be more likely to fail | |
737 | with SWP emulation enabled, leading to deadlock of the user | |
738 | application. | |
739 | ||
740 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | |
741 | on an external transaction monitoring block called a global | |
742 | monitor to maintain update atomicity. If your system does not | |
743 | implement a global monitor, this option can cause programs that | |
744 | perform SWP operations to uncached memory to deadlock. | |
745 | ||
746 | If unsure, say Y. | |
747 | ||
748 | config CPU_BIG_ENDIAN | |
749 | bool "Build big-endian kernel" | |
750 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
751 | help | |
752 | Say Y if you plan on running a kernel in big-endian mode. | |
753 | Note that your board must be properly built and your board | |
754 | port must properly enable any big-endian related features | |
755 | of your chipset/board/processor. | |
756 | ||
757 | config CPU_ENDIAN_BE8 | |
758 | bool | |
759 | depends on CPU_BIG_ENDIAN | |
760 | default CPU_V6 || CPU_V6K || CPU_V7 | |
761 | help | |
762 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. | |
763 | ||
764 | config CPU_ENDIAN_BE32 | |
765 | bool | |
766 | depends on CPU_BIG_ENDIAN | |
767 | default !CPU_ENDIAN_BE8 | |
768 | help | |
769 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. | |
770 | ||
771 | config CPU_HIGH_VECTOR | |
772 | depends on !MMU && CPU_CP15 && !CPU_ARM740T | |
773 | bool "Select the High exception vector" | |
774 | help | |
775 | Say Y here to select high exception vector(0xFFFF0000~). | |
776 | The exception vector can vary depending on the platform | |
777 | design in nommu mode. If your platform needs to select | |
778 | high exception vector, say Y. | |
779 | Otherwise or if you are unsure, say N, and the low exception | |
780 | vector (0x00000000~) will be used. | |
781 | ||
782 | config CPU_ICACHE_DISABLE | |
783 | bool "Disable I-Cache (I-bit)" | |
784 | depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M | |
785 | help | |
786 | Say Y here to disable the processor instruction cache. Unless | |
787 | you have a reason not to or are unsure, say N. | |
788 | ||
789 | config CPU_DCACHE_DISABLE | |
790 | bool "Disable D-Cache (C-bit)" | |
791 | depends on (CPU_CP15 && !SMP) || CPU_V7M | |
792 | help | |
793 | Say Y here to disable the processor data cache. Unless | |
794 | you have a reason not to or are unsure, say N. | |
795 | ||
796 | config CPU_DCACHE_SIZE | |
797 | hex | |
798 | depends on CPU_ARM740T || CPU_ARM946E | |
799 | default 0x00001000 if CPU_ARM740T | |
800 | default 0x00002000 # default size for ARM946E-S | |
801 | help | |
802 | Some cores are synthesizable to have various sized cache. For | |
803 | ARM946E-S case, it can vary from 0KB to 1MB. | |
804 | To support such cache operations, it is efficient to know the size | |
805 | before compile time. | |
806 | If your SoC is configured to have a different size, define the value | |
807 | here with proper conditions. | |
808 | ||
809 | config CPU_DCACHE_WRITETHROUGH | |
810 | bool "Force write through D-cache" | |
811 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE | |
812 | default y if CPU_ARM925T | |
813 | help | |
814 | Say Y here to use the data cache in writethrough mode. Unless you | |
815 | specifically require this or are unsure, say N. | |
816 | ||
817 | config CPU_CACHE_ROUND_ROBIN | |
818 | bool "Round robin I and D cache replacement algorithm" | |
819 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) | |
820 | help | |
821 | Say Y here to use the predictable round-robin cache replacement | |
822 | policy. Unless you specifically require this or are unsure, say N. | |
823 | ||
824 | config CPU_BPREDICT_DISABLE | |
825 | bool "Disable branch prediction" | |
826 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M | |
827 | help | |
828 | Say Y here to disable branch prediction. If unsure, say N. | |
829 | ||
830 | config CPU_SPECTRE | |
831 | bool | |
832 | ||
833 | config HARDEN_BRANCH_PREDICTOR | |
834 | bool "Harden the branch predictor against aliasing attacks" if EXPERT | |
835 | depends on CPU_SPECTRE | |
836 | default y | |
837 | help | |
838 | Speculation attacks against some high-performance processors rely | |
839 | on being able to manipulate the branch predictor for a victim | |
840 | context by executing aliasing branches in the attacker context. | |
841 | Such attacks can be partially mitigated against by clearing | |
842 | internal branch predictor state and limiting the prediction | |
843 | logic in some situations. | |
844 | ||
845 | This config option will take CPU-specific actions to harden | |
846 | the branch predictor against aliasing attacks and may rely on | |
847 | specific instruction sequences or control bits being set by | |
848 | the system firmware. | |
849 | ||
850 | If unsure, say Y. | |
851 | ||
852 | config TLS_REG_EMUL | |
853 | bool | |
854 | select NEED_KUSER_HELPERS | |
855 | help | |
856 | An SMP system using a pre-ARMv6 processor (there are apparently | |
857 | a few prototypes like that in existence) and therefore access to | |
858 | that required register must be emulated. | |
859 | ||
860 | config NEED_KUSER_HELPERS | |
861 | bool | |
862 | ||
863 | config KUSER_HELPERS | |
864 | bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS | |
865 | depends on MMU | |
866 | default y | |
867 | help | |
868 | Warning: disabling this option may break user programs. | |
869 | ||
870 | Provide kuser helpers in the vector page. The kernel provides | |
871 | helper code to userspace in read only form at a fixed location | |
872 | in the high vector page to allow userspace to be independent of | |
873 | the CPU type fitted to the system. This permits binaries to be | |
874 | run on ARMv4 through to ARMv7 without modification. | |
875 | ||
876 | See Documentation/arm/kernel_user_helpers.txt for details. | |
877 | ||
878 | However, the fixed address nature of these helpers can be used | |
879 | by ROP (return orientated programming) authors when creating | |
880 | exploits. | |
881 | ||
882 | If all of the binaries and libraries which run on your platform | |
883 | are built specifically for your platform, and make no use of | |
884 | these helpers, then you can turn this option off to hinder | |
885 | such exploits. However, in that case, if a binary or library | |
886 | relying on those helpers is run, it will receive a SIGILL signal, | |
887 | which will terminate the program. | |
888 | ||
889 | Say N here only if you are absolutely certain that you do not | |
890 | need these helpers; otherwise, the safe option is to say Y. | |
891 | ||
892 | config VDSO | |
893 | bool "Enable VDSO for acceleration of some system calls" | |
894 | depends on AEABI && MMU && CPU_V7 | |
895 | default y if ARM_ARCH_TIMER | |
896 | select GENERIC_TIME_VSYSCALL | |
897 | help | |
898 | Place in the process address space an ELF shared object | |
899 | providing fast implementations of gettimeofday and | |
900 | clock_gettime. Systems that implement the ARM architected | |
901 | timer will receive maximum benefit. | |
902 | ||
903 | You must have glibc 2.22 or later for programs to seamlessly | |
904 | take advantage of this. | |
905 | ||
906 | config DMA_CACHE_RWFO | |
907 | bool "Enable read/write for ownership DMA cache maintenance" | |
908 | depends on CPU_V6K && SMP | |
909 | default y | |
910 | help | |
911 | The Snoop Control Unit on ARM11MPCore does not detect the | |
912 | cache maintenance operations and the dma_{map,unmap}_area() | |
913 | functions may leave stale cache entries on other CPUs. By | |
914 | enabling this option, Read or Write For Ownership in the ARMv6 | |
915 | DMA cache maintenance functions is performed. These LDR/STR | |
916 | instructions change the cache line state to shared or modified | |
917 | so that the cache operation has the desired effect. | |
918 | ||
919 | Note that the workaround is only valid on processors that do | |
920 | not perform speculative loads into the D-cache. For such | |
921 | processors, if cache maintenance operations are not broadcast | |
922 | in hardware, other workarounds are needed (e.g. cache | |
923 | maintenance broadcasting in software via FIQ). | |
924 | ||
925 | config OUTER_CACHE | |
926 | bool | |
927 | ||
928 | config OUTER_CACHE_SYNC | |
929 | bool | |
930 | select ARM_HEAVY_MB | |
931 | help | |
932 | The outer cache has a outer_cache_fns.sync function pointer | |
933 | that can be used to drain the write buffer of the outer cache. | |
934 | ||
935 | config CACHE_FEROCEON_L2 | |
936 | bool "Enable the Feroceon L2 cache controller" | |
937 | depends on ARCH_MV78XX0 || ARCH_MVEBU | |
938 | default y | |
939 | select OUTER_CACHE | |
940 | help | |
941 | This option enables the Feroceon L2 cache controller. | |
942 | ||
943 | config CACHE_FEROCEON_L2_WRITETHROUGH | |
944 | bool "Force Feroceon L2 cache write through" | |
945 | depends on CACHE_FEROCEON_L2 | |
946 | help | |
947 | Say Y here to use the Feroceon L2 cache in writethrough mode. | |
948 | Unless you specifically require this, say N for writeback mode. | |
949 | ||
950 | config MIGHT_HAVE_CACHE_L2X0 | |
951 | bool | |
952 | help | |
953 | This option should be selected by machines which have a L2x0 | |
954 | or PL310 cache controller, but where its use is optional. | |
955 | ||
956 | The only effect of this option is to make CACHE_L2X0 and | |
957 | related options available to the user for configuration. | |
958 | ||
959 | Boards or SoCs which always require the cache controller | |
960 | support to be present should select CACHE_L2X0 directly | |
961 | instead of this option, thus preventing the user from | |
962 | inadvertently configuring a broken kernel. | |
963 | ||
964 | config CACHE_L2X0 | |
965 | bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 | |
966 | default MIGHT_HAVE_CACHE_L2X0 | |
967 | select OUTER_CACHE | |
968 | select OUTER_CACHE_SYNC | |
969 | help | |
970 | This option enables the L2x0 PrimeCell. | |
971 | ||
972 | config CACHE_L2X0_PMU | |
973 | bool "L2x0 performance monitor support" if CACHE_L2X0 | |
974 | depends on PERF_EVENTS | |
975 | help | |
976 | This option enables support for the performance monitoring features | |
977 | of the L220 and PL310 outer cache controllers. | |
978 | ||
979 | if CACHE_L2X0 | |
980 | ||
981 | config PL310_ERRATA_588369 | |
982 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" | |
983 | help | |
984 | The PL310 L2 cache controller implements three types of Clean & | |
985 | Invalidate maintenance operations: by Physical Address | |
986 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
987 | They are architecturally defined to behave as the execution of a | |
988 | clean operation followed immediately by an invalidate operation, | |
989 | both performing to the same memory location. This functionality | |
990 | is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) | |
991 | as clean lines are not invalidated as a result of these operations. | |
992 | ||
993 | config PL310_ERRATA_727915 | |
994 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" | |
995 | help | |
996 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
997 | operation (offset 0x7FC). This operation runs in background so that | |
998 | PL310 can handle normal accesses while it is in progress. Under very | |
999 | rare circumstances, due to this erratum, write data can be lost when | |
1000 | PL310 treats a cacheable write transaction during a Clean & | |
1001 | Invalidate by Way operation. Revisions prior to r3p1 are affected by | |
1002 | this errata (fixed in r3p1). | |
1003 | ||
1004 | config PL310_ERRATA_753970 | |
1005 | bool "PL310 errata: cache sync operation may be faulty" | |
1006 | help | |
1007 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1008 | ||
1009 | Under some condition the effect of cache sync operation on | |
1010 | the store buffer still remains when the operation completes. | |
1011 | This means that the store buffer is always asked to drain and | |
1012 | this prevents it from merging any further writes. The workaround | |
1013 | is to replace the normal offset of cache sync operation (0x730) | |
1014 | by another offset targeting an unmapped PL310 register 0x740. | |
1015 | This has the same effect as the cache sync operation: store buffer | |
1016 | drain and waiting for all buffers empty. | |
1017 | ||
1018 | config PL310_ERRATA_769419 | |
1019 | bool "PL310 errata: no automatic Store Buffer drain" | |
1020 | help | |
1021 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1022 | not automatically drain. This can cause normal, non-cacheable | |
1023 | writes to be retained when the memory system is idle, leading | |
1024 | to suboptimal I/O performance for drivers using coherent DMA. | |
1025 | This option adds a write barrier to the cpu_idle loop so that, | |
1026 | on systems with an outer cache, the store buffer is drained | |
1027 | explicitly. | |
1028 | ||
1029 | endif | |
1030 | ||
1031 | config CACHE_TAUROS2 | |
1032 | bool "Enable the Tauros2 L2 cache controller" | |
1033 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) | |
1034 | default y | |
1035 | select OUTER_CACHE | |
1036 | help | |
1037 | This option enables the Tauros2 L2 cache controller (as | |
1038 | found on PJ1/PJ4). | |
1039 | ||
1040 | config CACHE_UNIPHIER | |
1041 | bool "Enable the UniPhier outer cache controller" | |
1042 | depends on ARCH_UNIPHIER | |
1043 | select ARM_L1_CACHE_SHIFT_7 | |
1044 | select OUTER_CACHE | |
1045 | select OUTER_CACHE_SYNC | |
1046 | help | |
1047 | This option enables the UniPhier outer cache (system cache) | |
1048 | controller. | |
1049 | ||
1050 | config CACHE_XSC3L2 | |
1051 | bool "Enable the L2 cache on XScale3" | |
1052 | depends on CPU_XSC3 | |
1053 | default y | |
1054 | select OUTER_CACHE | |
1055 | help | |
1056 | This option enables the L2 cache on XScale3. | |
1057 | ||
1058 | config ARM_L1_CACHE_SHIFT_6 | |
1059 | bool | |
1060 | default y if CPU_V7 | |
1061 | help | |
1062 | Setting ARM L1 cache line size to 64 Bytes. | |
1063 | ||
1064 | config ARM_L1_CACHE_SHIFT_7 | |
1065 | bool | |
1066 | help | |
1067 | Setting ARM L1 cache line size to 128 Bytes. | |
1068 | ||
1069 | config ARM_L1_CACHE_SHIFT | |
1070 | int | |
1071 | default 7 if ARM_L1_CACHE_SHIFT_7 | |
1072 | default 6 if ARM_L1_CACHE_SHIFT_6 | |
1073 | default 5 | |
1074 | ||
1075 | config ARM_DMA_MEM_BUFFERABLE | |
1076 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7 | |
1077 | default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M | |
1078 | help | |
1079 | Historically, the kernel has used strongly ordered mappings to | |
1080 | provide DMA coherent memory. With the advent of ARMv7, mapping | |
1081 | memory with differing types results in unpredictable behaviour, | |
1082 | so on these CPUs, this option is forced on. | |
1083 | ||
1084 | Multiple mappings with differing attributes is also unpredictable | |
1085 | on ARMv6 CPUs, but since they do not have aggressive speculative | |
1086 | prefetch, no harm appears to occur. | |
1087 | ||
1088 | However, drivers may be missing the necessary barriers for ARMv6, | |
1089 | and therefore turning this on may result in unpredictable driver | |
1090 | behaviour. Therefore, we offer this as an option. | |
1091 | ||
1092 | On some of the beefier ARMv7-M machines (with DMA and write | |
1093 | buffers) you likely want this enabled, while those that | |
1094 | didn't need it until now also won't need it in the future. | |
1095 | ||
1096 | You are recommended say 'Y' here and debug any affected drivers. | |
1097 | ||
1098 | config ARM_HEAVY_MB | |
1099 | bool | |
1100 | ||
1101 | config ARCH_SUPPORTS_BIG_ENDIAN | |
1102 | bool | |
1103 | help | |
1104 | This option specifies the architecture can support big endian | |
1105 | operation. | |
1106 | ||
1107 | config DEBUG_ALIGN_RODATA | |
1108 | bool "Make rodata strictly non-executable" | |
1109 | depends on STRICT_KERNEL_RWX | |
1110 | default y | |
1111 | help | |
1112 | If this is set, rodata will be made explicitly non-executable. This | |
1113 | provides protection on the rare chance that attackers might find and | |
1114 | use ROP gadgets that exist in the rodata section. This adds an | |
1115 | additional section-aligned split of rodata from kernel text so it | |
1116 | can be made explicitly non-executable. This padding may waste memory | |
1117 | space to gain the additional protection. |