]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * linux/arch/arm/mm/dma-mapping.c | |
3 | * | |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/bootmem.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/genalloc.h> | |
16 | #include <linux/gfp.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/dma-contiguous.h> | |
23 | #include <linux/highmem.h> | |
24 | #include <linux/memblock.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/iommu.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/vmalloc.h> | |
29 | #include <linux/sizes.h> | |
30 | #include <linux/cma.h> | |
31 | ||
32 | #include <asm/memory.h> | |
33 | #include <asm/highmem.h> | |
34 | #include <asm/cacheflush.h> | |
35 | #include <asm/tlbflush.h> | |
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/dma-iommu.h> | |
38 | #include <asm/mach/map.h> | |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
41 | ||
42 | #include "dma.h" | |
43 | #include "mm.h" | |
44 | ||
45 | /* | |
46 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
47 | * is either exclusively owned by the CPU (and therefore may be accessed | |
48 | * by it) or exclusively owned by the DMA device. These helper functions | |
49 | * represent the transitions between these two ownership states. | |
50 | * | |
51 | * Note, however, that on later ARMs, this notion does not work due to | |
52 | * speculative prefetches. We model our approach on the assumption that | |
53 | * the CPU does do speculative prefetches, which means we clean caches | |
54 | * before transfers and delay cache invalidation until transfer completion. | |
55 | * | |
56 | */ | |
57 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, | |
58 | size_t, enum dma_data_direction); | |
59 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, | |
60 | size_t, enum dma_data_direction); | |
61 | ||
62 | /** | |
63 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
64 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
65 | * @page: page that buffer resides in | |
66 | * @offset: offset into page for start of buffer | |
67 | * @size: size of buffer to map | |
68 | * @dir: DMA transfer direction | |
69 | * | |
70 | * Ensure that any data held in the cache is appropriately discarded | |
71 | * or written back. | |
72 | * | |
73 | * The device owns this memory once this call has completed. The CPU | |
74 | * can regain ownership by calling dma_unmap_page(). | |
75 | */ | |
76 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, | |
77 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
78 | struct dma_attrs *attrs) | |
79 | { | |
80 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
81 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
82 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
83 | } | |
84 | ||
85 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, | |
86 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
87 | struct dma_attrs *attrs) | |
88 | { | |
89 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
90 | } | |
91 | ||
92 | /** | |
93 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
94 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
95 | * @handle: DMA address of buffer | |
96 | * @size: size of buffer (same as passed to dma_map_page) | |
97 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
98 | * | |
99 | * Unmap a page streaming mode DMA translation. The handle and size | |
100 | * must match what was provided in the previous dma_map_page() call. | |
101 | * All other usages are undefined. | |
102 | * | |
103 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
104 | * whatever the device wrote there. | |
105 | */ | |
106 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, | |
107 | size_t size, enum dma_data_direction dir, | |
108 | struct dma_attrs *attrs) | |
109 | { | |
110 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
111 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), | |
112 | handle & ~PAGE_MASK, size, dir); | |
113 | } | |
114 | ||
115 | static void arm_dma_sync_single_for_cpu(struct device *dev, | |
116 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
117 | { | |
118 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
119 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
120 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
121 | } | |
122 | ||
123 | static void arm_dma_sync_single_for_device(struct device *dev, | |
124 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
125 | { | |
126 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
127 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
128 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
129 | } | |
130 | ||
131 | struct dma_map_ops arm_dma_ops = { | |
132 | .alloc = arm_dma_alloc, | |
133 | .free = arm_dma_free, | |
134 | .mmap = arm_dma_mmap, | |
135 | .get_sgtable = arm_dma_get_sgtable, | |
136 | .map_page = arm_dma_map_page, | |
137 | .unmap_page = arm_dma_unmap_page, | |
138 | .map_sg = arm_dma_map_sg, | |
139 | .unmap_sg = arm_dma_unmap_sg, | |
140 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
141 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
142 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
143 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
144 | .set_dma_mask = arm_dma_set_mask, | |
145 | }; | |
146 | EXPORT_SYMBOL(arm_dma_ops); | |
147 | ||
148 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
149 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
150 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
151 | dma_addr_t handle, struct dma_attrs *attrs); | |
152 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
153 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
154 | struct dma_attrs *attrs); | |
155 | ||
156 | struct dma_map_ops arm_coherent_dma_ops = { | |
157 | .alloc = arm_coherent_dma_alloc, | |
158 | .free = arm_coherent_dma_free, | |
159 | .mmap = arm_coherent_dma_mmap, | |
160 | .get_sgtable = arm_dma_get_sgtable, | |
161 | .map_page = arm_coherent_dma_map_page, | |
162 | .map_sg = arm_dma_map_sg, | |
163 | .set_dma_mask = arm_dma_set_mask, | |
164 | }; | |
165 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
166 | ||
167 | static int __dma_supported(struct device *dev, u64 mask, bool warn) | |
168 | { | |
169 | unsigned long max_dma_pfn; | |
170 | ||
171 | /* | |
172 | * If the mask allows for more memory than we can address, | |
173 | * and we actually have that much memory, then we must | |
174 | * indicate that DMA to this device is not supported. | |
175 | */ | |
176 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
177 | mask > (dma_addr_t)~0 && | |
178 | dma_to_pfn(dev, ~0) < max_pfn - 1) { | |
179 | if (warn) { | |
180 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
181 | mask); | |
182 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
183 | } | |
184 | return 0; | |
185 | } | |
186 | ||
187 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
188 | ||
189 | /* | |
190 | * Translate the device's DMA mask to a PFN limit. This | |
191 | * PFN number includes the page which we can DMA to. | |
192 | */ | |
193 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
194 | if (warn) | |
195 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
196 | mask, | |
197 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
198 | max_dma_pfn + 1); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | return 1; | |
203 | } | |
204 | ||
205 | static u64 get_coherent_dma_mask(struct device *dev) | |
206 | { | |
207 | u64 mask = (u64)DMA_BIT_MASK(32); | |
208 | ||
209 | if (dev) { | |
210 | mask = dev->coherent_dma_mask; | |
211 | ||
212 | /* | |
213 | * Sanity check the DMA mask - it must be non-zero, and | |
214 | * must be able to be satisfied by a DMA allocation. | |
215 | */ | |
216 | if (mask == 0) { | |
217 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
218 | return 0; | |
219 | } | |
220 | ||
221 | if (!__dma_supported(dev, mask, true)) | |
222 | return 0; | |
223 | } | |
224 | ||
225 | return mask; | |
226 | } | |
227 | ||
228 | static void __dma_clear_buffer(struct page *page, size_t size) | |
229 | { | |
230 | /* | |
231 | * Ensure that the allocated pages are zeroed, and that any data | |
232 | * lurking in the kernel direct-mapped region is invalidated. | |
233 | */ | |
234 | if (PageHighMem(page)) { | |
235 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
236 | phys_addr_t end = base + size; | |
237 | while (size > 0) { | |
238 | void *ptr = kmap_atomic(page); | |
239 | memset(ptr, 0, PAGE_SIZE); | |
240 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
241 | kunmap_atomic(ptr); | |
242 | page++; | |
243 | size -= PAGE_SIZE; | |
244 | } | |
245 | outer_flush_range(base, end); | |
246 | } else { | |
247 | void *ptr = page_address(page); | |
248 | memset(ptr, 0, size); | |
249 | dmac_flush_range(ptr, ptr + size); | |
250 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
251 | } | |
252 | } | |
253 | ||
254 | /* | |
255 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
256 | * specified gfp mask. Note that 'size' must be page aligned. | |
257 | */ | |
258 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
259 | { | |
260 | unsigned long order = get_order(size); | |
261 | struct page *page, *p, *e; | |
262 | ||
263 | page = alloc_pages(gfp, order); | |
264 | if (!page) | |
265 | return NULL; | |
266 | ||
267 | /* | |
268 | * Now split the huge page and free the excess pages | |
269 | */ | |
270 | split_page(page, order); | |
271 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
272 | __free_page(p); | |
273 | ||
274 | __dma_clear_buffer(page, size); | |
275 | ||
276 | return page; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Free a DMA buffer. 'size' must be page aligned. | |
281 | */ | |
282 | static void __dma_free_buffer(struct page *page, size_t size) | |
283 | { | |
284 | struct page *e = page + (size >> PAGE_SHIFT); | |
285 | ||
286 | while (page < e) { | |
287 | __free_page(page); | |
288 | page++; | |
289 | } | |
290 | } | |
291 | ||
292 | #ifdef CONFIG_MMU | |
293 | ||
294 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
295 | pgprot_t prot, struct page **ret_page, | |
296 | const void *caller, bool want_vaddr); | |
297 | ||
298 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
299 | pgprot_t prot, struct page **ret_page, | |
300 | const void *caller, bool want_vaddr); | |
301 | ||
302 | static void * | |
303 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
304 | const void *caller) | |
305 | { | |
306 | /* | |
307 | * DMA allocation can be mapped to user space, so lets | |
308 | * set VM_USERMAP flags too. | |
309 | */ | |
310 | return dma_common_contiguous_remap(page, size, | |
311 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
312 | prot, caller); | |
313 | } | |
314 | ||
315 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
316 | { | |
317 | dma_common_free_remap(cpu_addr, size, | |
318 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
319 | } | |
320 | ||
321 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K | |
322 | static struct gen_pool *atomic_pool; | |
323 | ||
324 | static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; | |
325 | ||
326 | static int __init early_coherent_pool(char *p) | |
327 | { | |
328 | atomic_pool_size = memparse(p, &p); | |
329 | return 0; | |
330 | } | |
331 | early_param("coherent_pool", early_coherent_pool); | |
332 | ||
333 | void __init init_dma_coherent_pool_size(unsigned long size) | |
334 | { | |
335 | /* | |
336 | * Catch any attempt to set the pool size too late. | |
337 | */ | |
338 | BUG_ON(atomic_pool); | |
339 | ||
340 | /* | |
341 | * Set architecture specific coherent pool size only if | |
342 | * it has not been changed by kernel command line parameter. | |
343 | */ | |
344 | if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
345 | atomic_pool_size = size; | |
346 | } | |
347 | ||
348 | /* | |
349 | * Initialise the coherent pool for atomic allocations. | |
350 | */ | |
351 | static int __init atomic_pool_init(void) | |
352 | { | |
353 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); | |
354 | gfp_t gfp = GFP_KERNEL | GFP_DMA; | |
355 | struct page *page; | |
356 | void *ptr; | |
357 | ||
358 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); | |
359 | if (!atomic_pool) | |
360 | goto out; | |
361 | ||
362 | if (dev_get_cma_area(NULL)) | |
363 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, | |
364 | &page, atomic_pool_init, true); | |
365 | else | |
366 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, | |
367 | &page, atomic_pool_init, true); | |
368 | if (ptr) { | |
369 | int ret; | |
370 | ||
371 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
372 | page_to_phys(page), | |
373 | atomic_pool_size, -1); | |
374 | if (ret) | |
375 | goto destroy_genpool; | |
376 | ||
377 | gen_pool_set_algo(atomic_pool, | |
378 | gen_pool_first_fit_order_align, | |
379 | (void *)PAGE_SHIFT); | |
380 | pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n", | |
381 | atomic_pool_size / 1024); | |
382 | return 0; | |
383 | } | |
384 | ||
385 | destroy_genpool: | |
386 | gen_pool_destroy(atomic_pool); | |
387 | atomic_pool = NULL; | |
388 | out: | |
389 | pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n", | |
390 | atomic_pool_size / 1024); | |
391 | return -ENOMEM; | |
392 | } | |
393 | /* | |
394 | * CMA is activated by core_initcall, so we must be called after it. | |
395 | */ | |
396 | postcore_initcall(atomic_pool_init); | |
397 | ||
398 | struct dma_contig_early_reserve { | |
399 | phys_addr_t base; | |
400 | unsigned long size; | |
401 | }; | |
402 | ||
403 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
404 | ||
405 | static int dma_mmu_remap_num __initdata; | |
406 | ||
407 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
408 | { | |
409 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
410 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
411 | dma_mmu_remap_num++; | |
412 | } | |
413 | ||
414 | void __init dma_contiguous_remap(void) | |
415 | { | |
416 | int i; | |
417 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
418 | phys_addr_t start = dma_mmu_remap[i].base; | |
419 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
420 | struct map_desc map; | |
421 | unsigned long addr; | |
422 | ||
423 | if (end > arm_lowmem_limit) | |
424 | end = arm_lowmem_limit; | |
425 | if (start >= end) | |
426 | continue; | |
427 | ||
428 | map.pfn = __phys_to_pfn(start); | |
429 | map.virtual = __phys_to_virt(start); | |
430 | map.length = end - start; | |
431 | map.type = MT_MEMORY_DMA_READY; | |
432 | ||
433 | /* | |
434 | * Clear previous low-memory mapping to ensure that the | |
435 | * TLB does not see any conflicting entries, then flush | |
436 | * the TLB of the old entries before creating new mappings. | |
437 | * | |
438 | * This ensures that any speculatively loaded TLB entries | |
439 | * (even though they may be rare) can not cause any problems, | |
440 | * and ensures that this code is architecturally compliant. | |
441 | */ | |
442 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
443 | addr += PMD_SIZE) | |
444 | pmd_clear(pmd_off_k(addr)); | |
445 | ||
446 | flush_tlb_kernel_range(__phys_to_virt(start), | |
447 | __phys_to_virt(end)); | |
448 | ||
449 | iotable_init(&map, 1); | |
450 | } | |
451 | } | |
452 | ||
453 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, | |
454 | void *data) | |
455 | { | |
456 | struct page *page = virt_to_page(addr); | |
457 | pgprot_t prot = *(pgprot_t *)data; | |
458 | ||
459 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
460 | return 0; | |
461 | } | |
462 | ||
463 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
464 | { | |
465 | unsigned long start = (unsigned long) page_address(page); | |
466 | unsigned end = start + size; | |
467 | ||
468 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
469 | flush_tlb_kernel_range(start, end); | |
470 | } | |
471 | ||
472 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
473 | pgprot_t prot, struct page **ret_page, | |
474 | const void *caller, bool want_vaddr) | |
475 | { | |
476 | struct page *page; | |
477 | void *ptr = NULL; | |
478 | page = __dma_alloc_buffer(dev, size, gfp); | |
479 | if (!page) | |
480 | return NULL; | |
481 | if (!want_vaddr) | |
482 | goto out; | |
483 | ||
484 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
485 | if (!ptr) { | |
486 | __dma_free_buffer(page, size); | |
487 | return NULL; | |
488 | } | |
489 | ||
490 | out: | |
491 | *ret_page = page; | |
492 | return ptr; | |
493 | } | |
494 | ||
495 | static void *__alloc_from_pool(size_t size, struct page **ret_page) | |
496 | { | |
497 | unsigned long val; | |
498 | void *ptr = NULL; | |
499 | ||
500 | if (!atomic_pool) { | |
501 | WARN(1, "coherent pool not initialised!\n"); | |
502 | return NULL; | |
503 | } | |
504 | ||
505 | val = gen_pool_alloc(atomic_pool, size); | |
506 | if (val) { | |
507 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
508 | ||
509 | *ret_page = phys_to_page(phys); | |
510 | ptr = (void *)val; | |
511 | } | |
512 | ||
513 | return ptr; | |
514 | } | |
515 | ||
516 | static bool __in_atomic_pool(void *start, size_t size) | |
517 | { | |
518 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); | |
519 | } | |
520 | ||
521 | static int __free_from_pool(void *start, size_t size) | |
522 | { | |
523 | if (!__in_atomic_pool(start, size)) | |
524 | return 0; | |
525 | ||
526 | gen_pool_free(atomic_pool, (unsigned long)start, size); | |
527 | ||
528 | return 1; | |
529 | } | |
530 | ||
531 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
532 | pgprot_t prot, struct page **ret_page, | |
533 | const void *caller, bool want_vaddr) | |
534 | { | |
535 | unsigned long order = get_order(size); | |
536 | size_t count = size >> PAGE_SHIFT; | |
537 | struct page *page; | |
538 | void *ptr = NULL; | |
539 | ||
540 | page = dma_alloc_from_contiguous(dev, count, order); | |
541 | if (!page) | |
542 | return NULL; | |
543 | ||
544 | __dma_clear_buffer(page, size); | |
545 | ||
546 | if (!want_vaddr) | |
547 | goto out; | |
548 | ||
549 | if (PageHighMem(page)) { | |
550 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
551 | if (!ptr) { | |
552 | dma_release_from_contiguous(dev, page, count); | |
553 | return NULL; | |
554 | } | |
555 | } else { | |
556 | __dma_remap(page, size, prot); | |
557 | ptr = page_address(page); | |
558 | } | |
559 | ||
560 | out: | |
561 | *ret_page = page; | |
562 | return ptr; | |
563 | } | |
564 | ||
565 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
566 | void *cpu_addr, size_t size, bool want_vaddr) | |
567 | { | |
568 | if (want_vaddr) { | |
569 | if (PageHighMem(page)) | |
570 | __dma_free_remap(cpu_addr, size); | |
571 | else | |
572 | __dma_remap(page, size, PAGE_KERNEL); | |
573 | } | |
574 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
575 | } | |
576 | ||
577 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) | |
578 | { | |
579 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
580 | pgprot_writecombine(prot) : | |
581 | pgprot_dmacoherent(prot); | |
582 | return prot; | |
583 | } | |
584 | ||
585 | #define nommu() 0 | |
586 | ||
587 | #else /* !CONFIG_MMU */ | |
588 | ||
589 | #define nommu() 1 | |
590 | ||
591 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) | |
592 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL | |
593 | #define __alloc_from_pool(size, ret_page) NULL | |
594 | #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL | |
595 | #define __free_from_pool(cpu_addr, size) 0 | |
596 | #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) | |
597 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
598 | ||
599 | #endif /* CONFIG_MMU */ | |
600 | ||
601 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, | |
602 | struct page **ret_page) | |
603 | { | |
604 | struct page *page; | |
605 | page = __dma_alloc_buffer(dev, size, gfp); | |
606 | if (!page) | |
607 | return NULL; | |
608 | ||
609 | *ret_page = page; | |
610 | return page_address(page); | |
611 | } | |
612 | ||
613 | ||
614 | ||
615 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
616 | gfp_t gfp, pgprot_t prot, bool is_coherent, | |
617 | struct dma_attrs *attrs, const void *caller) | |
618 | { | |
619 | u64 mask = get_coherent_dma_mask(dev); | |
620 | struct page *page = NULL; | |
621 | void *addr; | |
622 | bool want_vaddr; | |
623 | ||
624 | #ifdef CONFIG_DMA_API_DEBUG | |
625 | u64 limit = (mask + 1) & ~mask; | |
626 | if (limit && size >= limit) { | |
627 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
628 | size, mask); | |
629 | return NULL; | |
630 | } | |
631 | #endif | |
632 | ||
633 | if (!mask) | |
634 | return NULL; | |
635 | ||
636 | if (mask < 0xffffffffULL) | |
637 | gfp |= GFP_DMA; | |
638 | ||
639 | /* | |
640 | * Following is a work-around (a.k.a. hack) to prevent pages | |
641 | * with __GFP_COMP being passed to split_page() which cannot | |
642 | * handle them. The real problem is that this flag probably | |
643 | * should be 0 on ARM as it is not supported on this | |
644 | * platform; see CONFIG_HUGETLBFS. | |
645 | */ | |
646 | gfp &= ~(__GFP_COMP); | |
647 | ||
648 | *handle = DMA_ERROR_CODE; | |
649 | size = PAGE_ALIGN(size); | |
650 | want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); | |
651 | ||
652 | if (nommu()) | |
653 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
654 | else if (dev_get_cma_area(dev) && (gfp & __GFP_DIRECT_RECLAIM)) | |
655 | addr = __alloc_from_contiguous(dev, size, prot, &page, | |
656 | caller, want_vaddr); | |
657 | else if (is_coherent) | |
658 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
659 | else if (!gfpflags_allow_blocking(gfp)) | |
660 | addr = __alloc_from_pool(size, &page); | |
661 | else | |
662 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, | |
663 | caller, want_vaddr); | |
664 | ||
665 | if (page) | |
666 | *handle = pfn_to_dma(dev, page_to_pfn(page)); | |
667 | ||
668 | return want_vaddr ? addr : page; | |
669 | } | |
670 | ||
671 | /* | |
672 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
673 | * virtual and bus address for that space. | |
674 | */ | |
675 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
676 | gfp_t gfp, struct dma_attrs *attrs) | |
677 | { | |
678 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); | |
679 | ||
680 | return __dma_alloc(dev, size, handle, gfp, prot, false, | |
681 | attrs, __builtin_return_address(0)); | |
682 | } | |
683 | ||
684 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
685 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
686 | { | |
687 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, | |
688 | attrs, __builtin_return_address(0)); | |
689 | } | |
690 | ||
691 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
692 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
693 | struct dma_attrs *attrs) | |
694 | { | |
695 | int ret = -ENXIO; | |
696 | #ifdef CONFIG_MMU | |
697 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
698 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
699 | unsigned long pfn = dma_to_pfn(dev, dma_addr); | |
700 | unsigned long off = vma->vm_pgoff; | |
701 | ||
702 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) | |
703 | return ret; | |
704 | ||
705 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { | |
706 | ret = remap_pfn_range(vma, vma->vm_start, | |
707 | pfn + off, | |
708 | vma->vm_end - vma->vm_start, | |
709 | vma->vm_page_prot); | |
710 | } | |
711 | #endif /* CONFIG_MMU */ | |
712 | ||
713 | return ret; | |
714 | } | |
715 | ||
716 | /* | |
717 | * Create userspace mapping for the DMA-coherent memory. | |
718 | */ | |
719 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
720 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
721 | struct dma_attrs *attrs) | |
722 | { | |
723 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
724 | } | |
725 | ||
726 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
727 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
728 | struct dma_attrs *attrs) | |
729 | { | |
730 | #ifdef CONFIG_MMU | |
731 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
732 | #endif /* CONFIG_MMU */ | |
733 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
734 | } | |
735 | ||
736 | /* | |
737 | * Free a buffer as defined by the above mapping. | |
738 | */ | |
739 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
740 | dma_addr_t handle, struct dma_attrs *attrs, | |
741 | bool is_coherent) | |
742 | { | |
743 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
744 | bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); | |
745 | ||
746 | size = PAGE_ALIGN(size); | |
747 | ||
748 | if (nommu()) { | |
749 | __dma_free_buffer(page, size); | |
750 | } else if (!is_coherent && __free_from_pool(cpu_addr, size)) { | |
751 | return; | |
752 | } else if (!dev_get_cma_area(dev)) { | |
753 | if (want_vaddr && !is_coherent) | |
754 | __dma_free_remap(cpu_addr, size); | |
755 | __dma_free_buffer(page, size); | |
756 | } else { | |
757 | /* | |
758 | * Non-atomic allocations cannot be freed with IRQs disabled | |
759 | */ | |
760 | WARN_ON(irqs_disabled()); | |
761 | __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr); | |
762 | } | |
763 | } | |
764 | ||
765 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
766 | dma_addr_t handle, struct dma_attrs *attrs) | |
767 | { | |
768 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
769 | } | |
770 | ||
771 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
772 | dma_addr_t handle, struct dma_attrs *attrs) | |
773 | { | |
774 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
775 | } | |
776 | ||
777 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, | |
778 | void *cpu_addr, dma_addr_t handle, size_t size, | |
779 | struct dma_attrs *attrs) | |
780 | { | |
781 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
782 | int ret; | |
783 | ||
784 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
785 | if (unlikely(ret)) | |
786 | return ret; | |
787 | ||
788 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
789 | return 0; | |
790 | } | |
791 | ||
792 | static void dma_cache_maint_page(struct page *page, unsigned long offset, | |
793 | size_t size, enum dma_data_direction dir, | |
794 | void (*op)(const void *, size_t, int)) | |
795 | { | |
796 | unsigned long pfn; | |
797 | size_t left = size; | |
798 | ||
799 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
800 | offset %= PAGE_SIZE; | |
801 | ||
802 | /* | |
803 | * A single sg entry may refer to multiple physically contiguous | |
804 | * pages. But we still need to process highmem pages individually. | |
805 | * If highmem is not configured then the bulk of this loop gets | |
806 | * optimized out. | |
807 | */ | |
808 | do { | |
809 | size_t len = left; | |
810 | void *vaddr; | |
811 | ||
812 | page = pfn_to_page(pfn); | |
813 | ||
814 | if (PageHighMem(page)) { | |
815 | if (len + offset > PAGE_SIZE) | |
816 | len = PAGE_SIZE - offset; | |
817 | ||
818 | if (cache_is_vipt_nonaliasing()) { | |
819 | vaddr = kmap_atomic(page); | |
820 | op(vaddr + offset, len, dir); | |
821 | kunmap_atomic(vaddr); | |
822 | } else { | |
823 | vaddr = kmap_high_get(page); | |
824 | if (vaddr) { | |
825 | op(vaddr + offset, len, dir); | |
826 | kunmap_high(page); | |
827 | } | |
828 | } | |
829 | } else { | |
830 | vaddr = page_address(page) + offset; | |
831 | op(vaddr, len, dir); | |
832 | } | |
833 | offset = 0; | |
834 | pfn++; | |
835 | left -= len; | |
836 | } while (left); | |
837 | } | |
838 | ||
839 | /* | |
840 | * Make an area consistent for devices. | |
841 | * Note: Drivers should NOT use this function directly, as it will break | |
842 | * platforms with CONFIG_DMABOUNCE. | |
843 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
844 | */ | |
845 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
846 | size_t size, enum dma_data_direction dir) | |
847 | { | |
848 | phys_addr_t paddr; | |
849 | ||
850 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); | |
851 | ||
852 | paddr = page_to_phys(page) + off; | |
853 | if (dir == DMA_FROM_DEVICE) { | |
854 | outer_inv_range(paddr, paddr + size); | |
855 | } else { | |
856 | outer_clean_range(paddr, paddr + size); | |
857 | } | |
858 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
859 | } | |
860 | ||
861 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, | |
862 | size_t size, enum dma_data_direction dir) | |
863 | { | |
864 | phys_addr_t paddr = page_to_phys(page) + off; | |
865 | ||
866 | /* FIXME: non-speculating: not required */ | |
867 | /* in any case, don't bother invalidating if DMA to device */ | |
868 | if (dir != DMA_TO_DEVICE) { | |
869 | outer_inv_range(paddr, paddr + size); | |
870 | ||
871 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); | |
872 | } | |
873 | ||
874 | /* | |
875 | * Mark the D-cache clean for these pages to avoid extra flushing. | |
876 | */ | |
877 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { | |
878 | unsigned long pfn; | |
879 | size_t left = size; | |
880 | ||
881 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
882 | off %= PAGE_SIZE; | |
883 | if (off) { | |
884 | pfn++; | |
885 | left -= PAGE_SIZE - off; | |
886 | } | |
887 | while (left >= PAGE_SIZE) { | |
888 | page = pfn_to_page(pfn++); | |
889 | set_bit(PG_dcache_clean, &page->flags); | |
890 | left -= PAGE_SIZE; | |
891 | } | |
892 | } | |
893 | } | |
894 | ||
895 | /** | |
896 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA | |
897 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
898 | * @sg: list of buffers | |
899 | * @nents: number of buffers to map | |
900 | * @dir: DMA transfer direction | |
901 | * | |
902 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
903 | * This is the scatter-gather version of the dma_map_single interface. | |
904 | * Here the scatter gather list elements are each tagged with the | |
905 | * appropriate dma address and length. They are obtained via | |
906 | * sg_dma_{address,length}. | |
907 | * | |
908 | * Device ownership issues as mentioned for dma_map_single are the same | |
909 | * here. | |
910 | */ | |
911 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
912 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
913 | { | |
914 | struct dma_map_ops *ops = get_dma_ops(dev); | |
915 | struct scatterlist *s; | |
916 | int i, j; | |
917 | ||
918 | for_each_sg(sg, s, nents, i) { | |
919 | #ifdef CONFIG_NEED_SG_DMA_LENGTH | |
920 | s->dma_length = s->length; | |
921 | #endif | |
922 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, | |
923 | s->length, dir, attrs); | |
924 | if (dma_mapping_error(dev, s->dma_address)) | |
925 | goto bad_mapping; | |
926 | } | |
927 | return nents; | |
928 | ||
929 | bad_mapping: | |
930 | for_each_sg(sg, s, i, j) | |
931 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); | |
932 | return 0; | |
933 | } | |
934 | ||
935 | /** | |
936 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
937 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
938 | * @sg: list of buffers | |
939 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
940 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
941 | * | |
942 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
943 | * rules concerning calls here are the same as for dma_unmap_single(). | |
944 | */ | |
945 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
946 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
947 | { | |
948 | struct dma_map_ops *ops = get_dma_ops(dev); | |
949 | struct scatterlist *s; | |
950 | ||
951 | int i; | |
952 | ||
953 | for_each_sg(sg, s, nents, i) | |
954 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); | |
955 | } | |
956 | ||
957 | /** | |
958 | * arm_dma_sync_sg_for_cpu | |
959 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
960 | * @sg: list of buffers | |
961 | * @nents: number of buffers to map (returned from dma_map_sg) | |
962 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
963 | */ | |
964 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
965 | int nents, enum dma_data_direction dir) | |
966 | { | |
967 | struct dma_map_ops *ops = get_dma_ops(dev); | |
968 | struct scatterlist *s; | |
969 | int i; | |
970 | ||
971 | for_each_sg(sg, s, nents, i) | |
972 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
973 | dir); | |
974 | } | |
975 | ||
976 | /** | |
977 | * arm_dma_sync_sg_for_device | |
978 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
979 | * @sg: list of buffers | |
980 | * @nents: number of buffers to map (returned from dma_map_sg) | |
981 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
982 | */ | |
983 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
984 | int nents, enum dma_data_direction dir) | |
985 | { | |
986 | struct dma_map_ops *ops = get_dma_ops(dev); | |
987 | struct scatterlist *s; | |
988 | int i; | |
989 | ||
990 | for_each_sg(sg, s, nents, i) | |
991 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
992 | dir); | |
993 | } | |
994 | ||
995 | /* | |
996 | * Return whether the given device DMA address mask can be supported | |
997 | * properly. For example, if your device can only drive the low 24-bits | |
998 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
999 | * to this function. | |
1000 | */ | |
1001 | int dma_supported(struct device *dev, u64 mask) | |
1002 | { | |
1003 | return __dma_supported(dev, mask, false); | |
1004 | } | |
1005 | EXPORT_SYMBOL(dma_supported); | |
1006 | ||
1007 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) | |
1008 | { | |
1009 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1010 | return -EIO; | |
1011 | ||
1012 | *dev->dma_mask = dma_mask; | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 | |
1018 | ||
1019 | static int __init dma_debug_do_init(void) | |
1020 | { | |
1021 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1022 | return 0; | |
1023 | } | |
1024 | fs_initcall(dma_debug_do_init); | |
1025 | ||
1026 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1027 | ||
1028 | /* IOMMU */ | |
1029 | ||
1030 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); | |
1031 | ||
1032 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
1033 | size_t size) | |
1034 | { | |
1035 | unsigned int order = get_order(size); | |
1036 | unsigned int align = 0; | |
1037 | unsigned int count, start; | |
1038 | size_t mapping_size = mapping->bits << PAGE_SHIFT; | |
1039 | unsigned long flags; | |
1040 | dma_addr_t iova; | |
1041 | int i; | |
1042 | ||
1043 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) | |
1044 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1045 | ||
1046 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1047 | align = (1 << order) - 1; | |
1048 | ||
1049 | spin_lock_irqsave(&mapping->lock, flags); | |
1050 | for (i = 0; i < mapping->nr_bitmaps; i++) { | |
1051 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1052 | mapping->bits, 0, count, align); | |
1053 | ||
1054 | if (start > mapping->bits) | |
1055 | continue; | |
1056 | ||
1057 | bitmap_set(mapping->bitmaps[i], start, count); | |
1058 | break; | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * No unused range found. Try to extend the existing mapping | |
1063 | * and perform a second attempt to reserve an IO virtual | |
1064 | * address range of size bytes. | |
1065 | */ | |
1066 | if (i == mapping->nr_bitmaps) { | |
1067 | if (extend_iommu_mapping(mapping)) { | |
1068 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1069 | return DMA_ERROR_CODE; | |
1070 | } | |
1071 | ||
1072 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1073 | mapping->bits, 0, count, align); | |
1074 | ||
1075 | if (start > mapping->bits) { | |
1076 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1077 | return DMA_ERROR_CODE; | |
1078 | } | |
1079 | ||
1080 | bitmap_set(mapping->bitmaps[i], start, count); | |
1081 | } | |
1082 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1083 | ||
1084 | iova = mapping->base + (mapping_size * i); | |
1085 | iova += start << PAGE_SHIFT; | |
1086 | ||
1087 | return iova; | |
1088 | } | |
1089 | ||
1090 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1091 | dma_addr_t addr, size_t size) | |
1092 | { | |
1093 | unsigned int start, count; | |
1094 | size_t mapping_size = mapping->bits << PAGE_SHIFT; | |
1095 | unsigned long flags; | |
1096 | dma_addr_t bitmap_base; | |
1097 | u32 bitmap_index; | |
1098 | ||
1099 | if (!size) | |
1100 | return; | |
1101 | ||
1102 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; | |
1103 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); | |
1104 | ||
1105 | bitmap_base = mapping->base + mapping_size * bitmap_index; | |
1106 | ||
1107 | start = (addr - bitmap_base) >> PAGE_SHIFT; | |
1108 | ||
1109 | if (addr + size > bitmap_base + mapping_size) { | |
1110 | /* | |
1111 | * The address range to be freed reaches into the iova | |
1112 | * range of the next bitmap. This should not happen as | |
1113 | * we don't allow this in __alloc_iova (at the | |
1114 | * moment). | |
1115 | */ | |
1116 | BUG(); | |
1117 | } else | |
1118 | count = size >> PAGE_SHIFT; | |
1119 | ||
1120 | spin_lock_irqsave(&mapping->lock, flags); | |
1121 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); | |
1122 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1123 | } | |
1124 | ||
1125 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, | |
1126 | gfp_t gfp, struct dma_attrs *attrs) | |
1127 | { | |
1128 | struct page **pages; | |
1129 | int count = size >> PAGE_SHIFT; | |
1130 | int array_size = count * sizeof(struct page *); | |
1131 | int i = 0; | |
1132 | ||
1133 | if (array_size <= PAGE_SIZE) | |
1134 | pages = kzalloc(array_size, GFP_KERNEL); | |
1135 | else | |
1136 | pages = vzalloc(array_size); | |
1137 | if (!pages) | |
1138 | return NULL; | |
1139 | ||
1140 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) | |
1141 | { | |
1142 | unsigned long order = get_order(size); | |
1143 | struct page *page; | |
1144 | ||
1145 | page = dma_alloc_from_contiguous(dev, count, order); | |
1146 | if (!page) | |
1147 | goto error; | |
1148 | ||
1149 | __dma_clear_buffer(page, size); | |
1150 | ||
1151 | for (i = 0; i < count; i++) | |
1152 | pages[i] = page + i; | |
1153 | ||
1154 | return pages; | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * IOMMU can map any pages, so himem can also be used here | |
1159 | */ | |
1160 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1161 | ||
1162 | while (count) { | |
1163 | int j, order; | |
1164 | ||
1165 | for (order = __fls(count); order > 0; --order) { | |
1166 | /* | |
1167 | * We do not want OOM killer to be invoked as long | |
1168 | * as we can fall back to single pages, so we force | |
1169 | * __GFP_NORETRY for orders higher than zero. | |
1170 | */ | |
1171 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1172 | if (pages[i]) | |
1173 | break; | |
1174 | } | |
1175 | ||
1176 | if (!pages[i]) { | |
1177 | /* | |
1178 | * Fall back to single page allocation. | |
1179 | * Might invoke OOM killer as last resort. | |
1180 | */ | |
1181 | pages[i] = alloc_pages(gfp, 0); | |
1182 | if (!pages[i]) | |
1183 | goto error; | |
1184 | } | |
1185 | ||
1186 | if (order) { | |
1187 | split_page(pages[i], order); | |
1188 | j = 1 << order; | |
1189 | while (--j) | |
1190 | pages[i + j] = pages[i] + j; | |
1191 | } | |
1192 | ||
1193 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1194 | i += 1 << order; | |
1195 | count -= 1 << order; | |
1196 | } | |
1197 | ||
1198 | return pages; | |
1199 | error: | |
1200 | while (i--) | |
1201 | if (pages[i]) | |
1202 | __free_pages(pages[i], 0); | |
1203 | if (array_size <= PAGE_SIZE) | |
1204 | kfree(pages); | |
1205 | else | |
1206 | vfree(pages); | |
1207 | return NULL; | |
1208 | } | |
1209 | ||
1210 | static int __iommu_free_buffer(struct device *dev, struct page **pages, | |
1211 | size_t size, struct dma_attrs *attrs) | |
1212 | { | |
1213 | int count = size >> PAGE_SHIFT; | |
1214 | int array_size = count * sizeof(struct page *); | |
1215 | int i; | |
1216 | ||
1217 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1218 | dma_release_from_contiguous(dev, pages[0], count); | |
1219 | } else { | |
1220 | for (i = 0; i < count; i++) | |
1221 | if (pages[i]) | |
1222 | __free_pages(pages[i], 0); | |
1223 | } | |
1224 | ||
1225 | if (array_size <= PAGE_SIZE) | |
1226 | kfree(pages); | |
1227 | else | |
1228 | vfree(pages); | |
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * Create a CPU mapping for a specified pages | |
1234 | */ | |
1235 | static void * | |
1236 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, | |
1237 | const void *caller) | |
1238 | { | |
1239 | return dma_common_pages_remap(pages, size, | |
1240 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
1241 | } | |
1242 | ||
1243 | /* | |
1244 | * Create a mapping in device IO address space for specified pages | |
1245 | */ | |
1246 | static dma_addr_t | |
1247 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1248 | { | |
1249 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1250 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1251 | dma_addr_t dma_addr, iova; | |
1252 | int i; | |
1253 | ||
1254 | dma_addr = __alloc_iova(mapping, size); | |
1255 | if (dma_addr == DMA_ERROR_CODE) | |
1256 | return dma_addr; | |
1257 | ||
1258 | iova = dma_addr; | |
1259 | for (i = 0; i < count; ) { | |
1260 | int ret; | |
1261 | ||
1262 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1263 | phys_addr_t phys = page_to_phys(pages[i]); | |
1264 | unsigned int len, j; | |
1265 | ||
1266 | for (j = i + 1; j < count; j++, next_pfn++) | |
1267 | if (page_to_pfn(pages[j]) != next_pfn) | |
1268 | break; | |
1269 | ||
1270 | len = (j - i) << PAGE_SHIFT; | |
1271 | ret = iommu_map(mapping->domain, iova, phys, len, | |
1272 | IOMMU_READ|IOMMU_WRITE); | |
1273 | if (ret < 0) | |
1274 | goto fail; | |
1275 | iova += len; | |
1276 | i = j; | |
1277 | } | |
1278 | return dma_addr; | |
1279 | fail: | |
1280 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1281 | __free_iova(mapping, dma_addr, size); | |
1282 | return DMA_ERROR_CODE; | |
1283 | } | |
1284 | ||
1285 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1286 | { | |
1287 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1288 | ||
1289 | /* | |
1290 | * add optional in-page offset from iova to size and align | |
1291 | * result to page size | |
1292 | */ | |
1293 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1294 | iova &= PAGE_MASK; | |
1295 | ||
1296 | iommu_unmap(mapping->domain, iova, size); | |
1297 | __free_iova(mapping, iova, size); | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static struct page **__atomic_get_pages(void *addr) | |
1302 | { | |
1303 | struct page *page; | |
1304 | phys_addr_t phys; | |
1305 | ||
1306 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1307 | page = phys_to_page(phys); | |
1308 | ||
1309 | return (struct page **)page; | |
1310 | } | |
1311 | ||
1312 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) | |
1313 | { | |
1314 | struct vm_struct *area; | |
1315 | ||
1316 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) | |
1317 | return __atomic_get_pages(cpu_addr); | |
1318 | ||
1319 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) | |
1320 | return cpu_addr; | |
1321 | ||
1322 | area = find_vm_area(cpu_addr); | |
1323 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1324 | return area->pages; | |
1325 | return NULL; | |
1326 | } | |
1327 | ||
1328 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, | |
1329 | dma_addr_t *handle) | |
1330 | { | |
1331 | struct page *page; | |
1332 | void *addr; | |
1333 | ||
1334 | addr = __alloc_from_pool(size, &page); | |
1335 | if (!addr) | |
1336 | return NULL; | |
1337 | ||
1338 | *handle = __iommu_create_mapping(dev, &page, size); | |
1339 | if (*handle == DMA_ERROR_CODE) | |
1340 | goto err_mapping; | |
1341 | ||
1342 | return addr; | |
1343 | ||
1344 | err_mapping: | |
1345 | __free_from_pool(addr, size); | |
1346 | return NULL; | |
1347 | } | |
1348 | ||
1349 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, | |
1350 | dma_addr_t handle, size_t size) | |
1351 | { | |
1352 | __iommu_remove_mapping(dev, handle, size); | |
1353 | __free_from_pool(cpu_addr, size); | |
1354 | } | |
1355 | ||
1356 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, | |
1357 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1358 | { | |
1359 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); | |
1360 | struct page **pages; | |
1361 | void *addr = NULL; | |
1362 | ||
1363 | *handle = DMA_ERROR_CODE; | |
1364 | size = PAGE_ALIGN(size); | |
1365 | ||
1366 | if (!gfpflags_allow_blocking(gfp)) | |
1367 | return __iommu_alloc_atomic(dev, size, handle); | |
1368 | ||
1369 | /* | |
1370 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1371 | * with __GFP_COMP being passed to split_page() which cannot | |
1372 | * handle them. The real problem is that this flag probably | |
1373 | * should be 0 on ARM as it is not supported on this | |
1374 | * platform; see CONFIG_HUGETLBFS. | |
1375 | */ | |
1376 | gfp &= ~(__GFP_COMP); | |
1377 | ||
1378 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); | |
1379 | if (!pages) | |
1380 | return NULL; | |
1381 | ||
1382 | *handle = __iommu_create_mapping(dev, pages, size); | |
1383 | if (*handle == DMA_ERROR_CODE) | |
1384 | goto err_buffer; | |
1385 | ||
1386 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) | |
1387 | return pages; | |
1388 | ||
1389 | addr = __iommu_alloc_remap(pages, size, gfp, prot, | |
1390 | __builtin_return_address(0)); | |
1391 | if (!addr) | |
1392 | goto err_mapping; | |
1393 | ||
1394 | return addr; | |
1395 | ||
1396 | err_mapping: | |
1397 | __iommu_remove_mapping(dev, *handle, size); | |
1398 | err_buffer: | |
1399 | __iommu_free_buffer(dev, pages, size, attrs); | |
1400 | return NULL; | |
1401 | } | |
1402 | ||
1403 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1404 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1405 | struct dma_attrs *attrs) | |
1406 | { | |
1407 | unsigned long uaddr = vma->vm_start; | |
1408 | unsigned long usize = vma->vm_end - vma->vm_start; | |
1409 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1410 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1411 | unsigned long off = vma->vm_pgoff; | |
1412 | ||
1413 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
1414 | ||
1415 | if (!pages) | |
1416 | return -ENXIO; | |
1417 | ||
1418 | if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off) | |
1419 | return -ENXIO; | |
1420 | ||
1421 | pages += off; | |
1422 | ||
1423 | do { | |
1424 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1425 | if (ret) { | |
1426 | pr_err("Remapping memory failed: %d\n", ret); | |
1427 | return ret; | |
1428 | } | |
1429 | uaddr += PAGE_SIZE; | |
1430 | usize -= PAGE_SIZE; | |
1431 | } while (usize > 0); | |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | /* | |
1437 | * free a page as defined by the above mapping. | |
1438 | * Must not be called with IRQs disabled. | |
1439 | */ | |
1440 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1441 | dma_addr_t handle, struct dma_attrs *attrs) | |
1442 | { | |
1443 | struct page **pages; | |
1444 | size = PAGE_ALIGN(size); | |
1445 | ||
1446 | if (__in_atomic_pool(cpu_addr, size)) { | |
1447 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
1448 | return; | |
1449 | } | |
1450 | ||
1451 | pages = __iommu_get_pages(cpu_addr, attrs); | |
1452 | if (!pages) { | |
1453 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1454 | return; | |
1455 | } | |
1456 | ||
1457 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { | |
1458 | dma_common_free_remap(cpu_addr, size, | |
1459 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
1460 | } | |
1461 | ||
1462 | __iommu_remove_mapping(dev, handle, size); | |
1463 | __iommu_free_buffer(dev, pages, size, attrs); | |
1464 | } | |
1465 | ||
1466 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, | |
1467 | void *cpu_addr, dma_addr_t dma_addr, | |
1468 | size_t size, struct dma_attrs *attrs) | |
1469 | { | |
1470 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1471 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1472 | ||
1473 | if (!pages) | |
1474 | return -ENXIO; | |
1475 | ||
1476 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1477 | GFP_KERNEL); | |
1478 | } | |
1479 | ||
1480 | static int __dma_direction_to_prot(enum dma_data_direction dir) | |
1481 | { | |
1482 | int prot; | |
1483 | ||
1484 | switch (dir) { | |
1485 | case DMA_BIDIRECTIONAL: | |
1486 | prot = IOMMU_READ | IOMMU_WRITE; | |
1487 | break; | |
1488 | case DMA_TO_DEVICE: | |
1489 | prot = IOMMU_READ; | |
1490 | break; | |
1491 | case DMA_FROM_DEVICE: | |
1492 | prot = IOMMU_WRITE; | |
1493 | break; | |
1494 | default: | |
1495 | prot = 0; | |
1496 | } | |
1497 | ||
1498 | return prot; | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * Map a part of the scatter-gather list into contiguous io address space | |
1503 | */ | |
1504 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1505 | size_t size, dma_addr_t *handle, | |
1506 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1507 | bool is_coherent) | |
1508 | { | |
1509 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1510 | dma_addr_t iova, iova_base; | |
1511 | int ret = 0; | |
1512 | unsigned int count; | |
1513 | struct scatterlist *s; | |
1514 | int prot; | |
1515 | ||
1516 | size = PAGE_ALIGN(size); | |
1517 | *handle = DMA_ERROR_CODE; | |
1518 | ||
1519 | iova_base = iova = __alloc_iova(mapping, size); | |
1520 | if (iova == DMA_ERROR_CODE) | |
1521 | return -ENOMEM; | |
1522 | ||
1523 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1524 | phys_addr_t phys = sg_phys(s) & PAGE_MASK; | |
1525 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1526 | ||
1527 | if (!is_coherent && | |
1528 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1529 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1530 | ||
1531 | prot = __dma_direction_to_prot(dir); | |
1532 | ||
1533 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
1534 | if (ret < 0) | |
1535 | goto fail; | |
1536 | count += len >> PAGE_SHIFT; | |
1537 | iova += len; | |
1538 | } | |
1539 | *handle = iova_base; | |
1540 | ||
1541 | return 0; | |
1542 | fail: | |
1543 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1544 | __free_iova(mapping, iova_base, size); | |
1545 | return ret; | |
1546 | } | |
1547 | ||
1548 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1549 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1550 | bool is_coherent) | |
1551 | { | |
1552 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1553 | int i, count = 0; | |
1554 | unsigned int offset = s->offset; | |
1555 | unsigned int size = s->offset + s->length; | |
1556 | unsigned int max = dma_get_max_seg_size(dev); | |
1557 | ||
1558 | for (i = 1; i < nents; i++) { | |
1559 | s = sg_next(s); | |
1560 | ||
1561 | s->dma_address = DMA_ERROR_CODE; | |
1562 | s->dma_length = 0; | |
1563 | ||
1564 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1565 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
1566 | dir, attrs, is_coherent) < 0) | |
1567 | goto bad_mapping; | |
1568 | ||
1569 | dma->dma_address += offset; | |
1570 | dma->dma_length = size - offset; | |
1571 | ||
1572 | size = offset = s->offset; | |
1573 | start = s; | |
1574 | dma = sg_next(dma); | |
1575 | count += 1; | |
1576 | } | |
1577 | size += s->length; | |
1578 | } | |
1579 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, | |
1580 | is_coherent) < 0) | |
1581 | goto bad_mapping; | |
1582 | ||
1583 | dma->dma_address += offset; | |
1584 | dma->dma_length = size - offset; | |
1585 | ||
1586 | return count+1; | |
1587 | ||
1588 | bad_mapping: | |
1589 | for_each_sg(sg, s, count, i) | |
1590 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1591 | return 0; | |
1592 | } | |
1593 | ||
1594 | /** | |
1595 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1596 | * @dev: valid struct device pointer | |
1597 | * @sg: list of buffers | |
1598 | * @nents: number of buffers to map | |
1599 | * @dir: DMA transfer direction | |
1600 | * | |
1601 | * Map a set of i/o coherent buffers described by scatterlist in streaming | |
1602 | * mode for DMA. The scatter gather list elements are merged together (if | |
1603 | * possible) and tagged with the appropriate dma address and length. They are | |
1604 | * obtained via sg_dma_{address,length}. | |
1605 | */ | |
1606 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1607 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1608 | { | |
1609 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1614 | * @dev: valid struct device pointer | |
1615 | * @sg: list of buffers | |
1616 | * @nents: number of buffers to map | |
1617 | * @dir: DMA transfer direction | |
1618 | * | |
1619 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1620 | * The scatter gather list elements are merged together (if possible) and | |
1621 | * tagged with the appropriate dma address and length. They are obtained via | |
1622 | * sg_dma_{address,length}. | |
1623 | */ | |
1624 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1625 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1626 | { | |
1627 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1628 | } | |
1629 | ||
1630 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1631 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1632 | bool is_coherent) | |
1633 | { | |
1634 | struct scatterlist *s; | |
1635 | int i; | |
1636 | ||
1637 | for_each_sg(sg, s, nents, i) { | |
1638 | if (sg_dma_len(s)) | |
1639 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1640 | sg_dma_len(s)); | |
1641 | if (!is_coherent && | |
1642 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1643 | __dma_page_dev_to_cpu(sg_page(s), s->offset, | |
1644 | s->length, dir); | |
1645 | } | |
1646 | } | |
1647 | ||
1648 | /** | |
1649 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1650 | * @dev: valid struct device pointer | |
1651 | * @sg: list of buffers | |
1652 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1653 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1654 | * | |
1655 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1656 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1657 | */ | |
1658 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1659 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1660 | { | |
1661 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1662 | } | |
1663 | ||
1664 | /** | |
1665 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1666 | * @dev: valid struct device pointer | |
1667 | * @sg: list of buffers | |
1668 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1669 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1670 | * | |
1671 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1672 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1673 | */ | |
1674 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1675 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1676 | { | |
1677 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1678 | } | |
1679 | ||
1680 | /** | |
1681 | * arm_iommu_sync_sg_for_cpu | |
1682 | * @dev: valid struct device pointer | |
1683 | * @sg: list of buffers | |
1684 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1685 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1686 | */ | |
1687 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1688 | int nents, enum dma_data_direction dir) | |
1689 | { | |
1690 | struct scatterlist *s; | |
1691 | int i; | |
1692 | ||
1693 | for_each_sg(sg, s, nents, i) | |
1694 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1695 | ||
1696 | } | |
1697 | ||
1698 | /** | |
1699 | * arm_iommu_sync_sg_for_device | |
1700 | * @dev: valid struct device pointer | |
1701 | * @sg: list of buffers | |
1702 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1703 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1704 | */ | |
1705 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1706 | int nents, enum dma_data_direction dir) | |
1707 | { | |
1708 | struct scatterlist *s; | |
1709 | int i; | |
1710 | ||
1711 | for_each_sg(sg, s, nents, i) | |
1712 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1713 | } | |
1714 | ||
1715 | ||
1716 | /** | |
1717 | * arm_coherent_iommu_map_page | |
1718 | * @dev: valid struct device pointer | |
1719 | * @page: page that buffer resides in | |
1720 | * @offset: offset into page for start of buffer | |
1721 | * @size: size of buffer to map | |
1722 | * @dir: DMA transfer direction | |
1723 | * | |
1724 | * Coherent IOMMU aware version of arm_dma_map_page() | |
1725 | */ | |
1726 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, | |
1727 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1728 | struct dma_attrs *attrs) | |
1729 | { | |
1730 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1731 | dma_addr_t dma_addr; | |
1732 | int ret, prot, len = PAGE_ALIGN(size + offset); | |
1733 | ||
1734 | dma_addr = __alloc_iova(mapping, len); | |
1735 | if (dma_addr == DMA_ERROR_CODE) | |
1736 | return dma_addr; | |
1737 | ||
1738 | prot = __dma_direction_to_prot(dir); | |
1739 | ||
1740 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
1741 | if (ret < 0) | |
1742 | goto fail; | |
1743 | ||
1744 | return dma_addr + offset; | |
1745 | fail: | |
1746 | __free_iova(mapping, dma_addr, len); | |
1747 | return DMA_ERROR_CODE; | |
1748 | } | |
1749 | ||
1750 | /** | |
1751 | * arm_iommu_map_page | |
1752 | * @dev: valid struct device pointer | |
1753 | * @page: page that buffer resides in | |
1754 | * @offset: offset into page for start of buffer | |
1755 | * @size: size of buffer to map | |
1756 | * @dir: DMA transfer direction | |
1757 | * | |
1758 | * IOMMU aware version of arm_dma_map_page() | |
1759 | */ | |
1760 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1761 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1762 | struct dma_attrs *attrs) | |
1763 | { | |
1764 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1765 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1766 | ||
1767 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1768 | } | |
1769 | ||
1770 | /** | |
1771 | * arm_coherent_iommu_unmap_page | |
1772 | * @dev: valid struct device pointer | |
1773 | * @handle: DMA address of buffer | |
1774 | * @size: size of buffer (same as passed to dma_map_page) | |
1775 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1776 | * | |
1777 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1778 | */ | |
1779 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1780 | size_t size, enum dma_data_direction dir, | |
1781 | struct dma_attrs *attrs) | |
1782 | { | |
1783 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1784 | dma_addr_t iova = handle & PAGE_MASK; | |
1785 | int offset = handle & ~PAGE_MASK; | |
1786 | int len = PAGE_ALIGN(size + offset); | |
1787 | ||
1788 | if (!iova) | |
1789 | return; | |
1790 | ||
1791 | iommu_unmap(mapping->domain, iova, len); | |
1792 | __free_iova(mapping, iova, len); | |
1793 | } | |
1794 | ||
1795 | /** | |
1796 | * arm_iommu_unmap_page | |
1797 | * @dev: valid struct device pointer | |
1798 | * @handle: DMA address of buffer | |
1799 | * @size: size of buffer (same as passed to dma_map_page) | |
1800 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1801 | * | |
1802 | * IOMMU aware version of arm_dma_unmap_page() | |
1803 | */ | |
1804 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1805 | size_t size, enum dma_data_direction dir, | |
1806 | struct dma_attrs *attrs) | |
1807 | { | |
1808 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1809 | dma_addr_t iova = handle & PAGE_MASK; | |
1810 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1811 | int offset = handle & ~PAGE_MASK; | |
1812 | int len = PAGE_ALIGN(size + offset); | |
1813 | ||
1814 | if (!iova) | |
1815 | return; | |
1816 | ||
1817 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1818 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1819 | ||
1820 | iommu_unmap(mapping->domain, iova, len); | |
1821 | __free_iova(mapping, iova, len); | |
1822 | } | |
1823 | ||
1824 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1825 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1826 | { | |
1827 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1828 | dma_addr_t iova = handle & PAGE_MASK; | |
1829 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1830 | unsigned int offset = handle & ~PAGE_MASK; | |
1831 | ||
1832 | if (!iova) | |
1833 | return; | |
1834 | ||
1835 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1836 | } | |
1837 | ||
1838 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1839 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1840 | { | |
1841 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1842 | dma_addr_t iova = handle & PAGE_MASK; | |
1843 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1844 | unsigned int offset = handle & ~PAGE_MASK; | |
1845 | ||
1846 | if (!iova) | |
1847 | return; | |
1848 | ||
1849 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1850 | } | |
1851 | ||
1852 | struct dma_map_ops iommu_ops = { | |
1853 | .alloc = arm_iommu_alloc_attrs, | |
1854 | .free = arm_iommu_free_attrs, | |
1855 | .mmap = arm_iommu_mmap_attrs, | |
1856 | .get_sgtable = arm_iommu_get_sgtable, | |
1857 | ||
1858 | .map_page = arm_iommu_map_page, | |
1859 | .unmap_page = arm_iommu_unmap_page, | |
1860 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1861 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1862 | ||
1863 | .map_sg = arm_iommu_map_sg, | |
1864 | .unmap_sg = arm_iommu_unmap_sg, | |
1865 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1866 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1867 | ||
1868 | .set_dma_mask = arm_dma_set_mask, | |
1869 | }; | |
1870 | ||
1871 | struct dma_map_ops iommu_coherent_ops = { | |
1872 | .alloc = arm_iommu_alloc_attrs, | |
1873 | .free = arm_iommu_free_attrs, | |
1874 | .mmap = arm_iommu_mmap_attrs, | |
1875 | .get_sgtable = arm_iommu_get_sgtable, | |
1876 | ||
1877 | .map_page = arm_coherent_iommu_map_page, | |
1878 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1879 | ||
1880 | .map_sg = arm_coherent_iommu_map_sg, | |
1881 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
1882 | ||
1883 | .set_dma_mask = arm_dma_set_mask, | |
1884 | }; | |
1885 | ||
1886 | /** | |
1887 | * arm_iommu_create_mapping | |
1888 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1889 | * @base: start address of the valid IO address space | |
1890 | * @size: maximum size of the valid IO address space | |
1891 | * | |
1892 | * Creates a mapping structure which holds information about used/unused | |
1893 | * IO address ranges, which is required to perform memory allocation and | |
1894 | * mapping with IOMMU aware functions. | |
1895 | * | |
1896 | * The client device need to be attached to the mapping with | |
1897 | * arm_iommu_attach_device function. | |
1898 | */ | |
1899 | struct dma_iommu_mapping * | |
1900 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) | |
1901 | { | |
1902 | unsigned int bits = size >> PAGE_SHIFT; | |
1903 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
1904 | struct dma_iommu_mapping *mapping; | |
1905 | int extensions = 1; | |
1906 | int err = -ENOMEM; | |
1907 | ||
1908 | /* currently only 32-bit DMA address space is supported */ | |
1909 | if (size > DMA_BIT_MASK(32) + 1) | |
1910 | return ERR_PTR(-ERANGE); | |
1911 | ||
1912 | if (!bitmap_size) | |
1913 | return ERR_PTR(-EINVAL); | |
1914 | ||
1915 | if (bitmap_size > PAGE_SIZE) { | |
1916 | extensions = bitmap_size / PAGE_SIZE; | |
1917 | bitmap_size = PAGE_SIZE; | |
1918 | } | |
1919 | ||
1920 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1921 | if (!mapping) | |
1922 | goto err; | |
1923 | ||
1924 | mapping->bitmap_size = bitmap_size; | |
1925 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
1926 | GFP_KERNEL); | |
1927 | if (!mapping->bitmaps) | |
1928 | goto err2; | |
1929 | ||
1930 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); | |
1931 | if (!mapping->bitmaps[0]) | |
1932 | goto err3; | |
1933 | ||
1934 | mapping->nr_bitmaps = 1; | |
1935 | mapping->extensions = extensions; | |
1936 | mapping->base = base; | |
1937 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1938 | ||
1939 | spin_lock_init(&mapping->lock); | |
1940 | ||
1941 | mapping->domain = iommu_domain_alloc(bus); | |
1942 | if (!mapping->domain) | |
1943 | goto err4; | |
1944 | ||
1945 | kref_init(&mapping->kref); | |
1946 | return mapping; | |
1947 | err4: | |
1948 | kfree(mapping->bitmaps[0]); | |
1949 | err3: | |
1950 | kfree(mapping->bitmaps); | |
1951 | err2: | |
1952 | kfree(mapping); | |
1953 | err: | |
1954 | return ERR_PTR(err); | |
1955 | } | |
1956 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); | |
1957 | ||
1958 | static void release_iommu_mapping(struct kref *kref) | |
1959 | { | |
1960 | int i; | |
1961 | struct dma_iommu_mapping *mapping = | |
1962 | container_of(kref, struct dma_iommu_mapping, kref); | |
1963 | ||
1964 | iommu_domain_free(mapping->domain); | |
1965 | for (i = 0; i < mapping->nr_bitmaps; i++) | |
1966 | kfree(mapping->bitmaps[i]); | |
1967 | kfree(mapping->bitmaps); | |
1968 | kfree(mapping); | |
1969 | } | |
1970 | ||
1971 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) | |
1972 | { | |
1973 | int next_bitmap; | |
1974 | ||
1975 | if (mapping->nr_bitmaps >= mapping->extensions) | |
1976 | return -EINVAL; | |
1977 | ||
1978 | next_bitmap = mapping->nr_bitmaps; | |
1979 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
1980 | GFP_ATOMIC); | |
1981 | if (!mapping->bitmaps[next_bitmap]) | |
1982 | return -ENOMEM; | |
1983 | ||
1984 | mapping->nr_bitmaps++; | |
1985 | ||
1986 | return 0; | |
1987 | } | |
1988 | ||
1989 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1990 | { | |
1991 | if (mapping) | |
1992 | kref_put(&mapping->kref, release_iommu_mapping); | |
1993 | } | |
1994 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); | |
1995 | ||
1996 | static int __arm_iommu_attach_device(struct device *dev, | |
1997 | struct dma_iommu_mapping *mapping) | |
1998 | { | |
1999 | int err; | |
2000 | ||
2001 | err = iommu_attach_device(mapping->domain, dev); | |
2002 | if (err) | |
2003 | return err; | |
2004 | ||
2005 | kref_get(&mapping->kref); | |
2006 | to_dma_iommu_mapping(dev) = mapping; | |
2007 | ||
2008 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2009 | return 0; | |
2010 | } | |
2011 | ||
2012 | /** | |
2013 | * arm_iommu_attach_device | |
2014 | * @dev: valid struct device pointer | |
2015 | * @mapping: io address space mapping structure (returned from | |
2016 | * arm_iommu_create_mapping) | |
2017 | * | |
2018 | * Attaches specified io address space mapping to the provided device. | |
2019 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2020 | * IOMMU aware version. | |
2021 | * | |
2022 | * More than one client might be attached to the same io address space | |
2023 | * mapping. | |
2024 | */ | |
2025 | int arm_iommu_attach_device(struct device *dev, | |
2026 | struct dma_iommu_mapping *mapping) | |
2027 | { | |
2028 | int err; | |
2029 | ||
2030 | err = __arm_iommu_attach_device(dev, mapping); | |
2031 | if (err) | |
2032 | return err; | |
2033 | ||
2034 | set_dma_ops(dev, &iommu_ops); | |
2035 | return 0; | |
2036 | } | |
2037 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); | |
2038 | ||
2039 | static void __arm_iommu_detach_device(struct device *dev) | |
2040 | { | |
2041 | struct dma_iommu_mapping *mapping; | |
2042 | ||
2043 | mapping = to_dma_iommu_mapping(dev); | |
2044 | if (!mapping) { | |
2045 | dev_warn(dev, "Not attached\n"); | |
2046 | return; | |
2047 | } | |
2048 | ||
2049 | iommu_detach_device(mapping->domain, dev); | |
2050 | kref_put(&mapping->kref, release_iommu_mapping); | |
2051 | to_dma_iommu_mapping(dev) = NULL; | |
2052 | ||
2053 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2054 | } | |
2055 | ||
2056 | /** | |
2057 | * arm_iommu_detach_device | |
2058 | * @dev: valid struct device pointer | |
2059 | * | |
2060 | * Detaches the provided device from a previously attached map. | |
2061 | * This voids the dma operations (dma_map_ops pointer) | |
2062 | */ | |
2063 | void arm_iommu_detach_device(struct device *dev) | |
2064 | { | |
2065 | __arm_iommu_detach_device(dev); | |
2066 | set_dma_ops(dev, NULL); | |
2067 | } | |
2068 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); | |
2069 | ||
2070 | static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) | |
2071 | { | |
2072 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2073 | } | |
2074 | ||
2075 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2076 | struct iommu_ops *iommu) | |
2077 | { | |
2078 | struct dma_iommu_mapping *mapping; | |
2079 | ||
2080 | if (!iommu) | |
2081 | return false; | |
2082 | ||
2083 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2084 | if (IS_ERR(mapping)) { | |
2085 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2086 | size, dev_name(dev)); | |
2087 | return false; | |
2088 | } | |
2089 | ||
2090 | if (__arm_iommu_attach_device(dev, mapping)) { | |
2091 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", | |
2092 | dev_name(dev)); | |
2093 | arm_iommu_release_mapping(mapping); | |
2094 | return false; | |
2095 | } | |
2096 | ||
2097 | return true; | |
2098 | } | |
2099 | ||
2100 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2101 | { | |
2102 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
2103 | ||
2104 | if (!mapping) | |
2105 | return; | |
2106 | ||
2107 | __arm_iommu_detach_device(dev); | |
2108 | arm_iommu_release_mapping(mapping); | |
2109 | } | |
2110 | ||
2111 | #else | |
2112 | ||
2113 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2114 | struct iommu_ops *iommu) | |
2115 | { | |
2116 | return false; | |
2117 | } | |
2118 | ||
2119 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2120 | ||
2121 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2122 | ||
2123 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2124 | ||
2125 | static struct dma_map_ops *arm_get_dma_map_ops(bool coherent) | |
2126 | { | |
2127 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2128 | } | |
2129 | ||
2130 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2131 | struct iommu_ops *iommu, bool coherent) | |
2132 | { | |
2133 | struct dma_map_ops *dma_ops; | |
2134 | ||
2135 | dev->archdata.dma_coherent = coherent; | |
2136 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) | |
2137 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2138 | else | |
2139 | dma_ops = arm_get_dma_map_ops(coherent); | |
2140 | ||
2141 | set_dma_ops(dev, dma_ops); | |
2142 | } | |
2143 | ||
2144 | void arch_teardown_dma_ops(struct device *dev) | |
2145 | { | |
2146 | arm_teardown_iommu_dma_ops(dev); | |
2147 | } |