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1 | /* | |
2 | * Device Tree Include file for Marvell Armada 37xx family of SoCs. | |
3 | * | |
4 | * Copyright (C) 2016 Marvell | |
5 | * | |
6 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPL or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This file is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This file is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * Or, alternatively, | |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use, | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
48 | ||
49 | / { | |
50 | model = "Marvell Armada 37xx SoC"; | |
51 | compatible = "marvell,armada3700"; | |
52 | interrupt-parent = <&gic>; | |
53 | #address-cells = <2>; | |
54 | #size-cells = <2>; | |
55 | ||
56 | aliases { | |
57 | serial0 = &uart0; | |
58 | }; | |
59 | ||
60 | cpus { | |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | cpu@0 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a53", "arm,armv8"; | |
66 | reg = <0>; | |
67 | enable-method = "psci"; | |
68 | }; | |
69 | }; | |
70 | ||
71 | psci { | |
72 | compatible = "arm,psci-0.2"; | |
73 | method = "smc"; | |
74 | }; | |
75 | ||
76 | timer { | |
77 | compatible = "arm,armv8-timer"; | |
78 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
79 | <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
82 | }; | |
83 | ||
84 | soc { | |
85 | compatible = "simple-bus"; | |
86 | #address-cells = <2>; | |
87 | #size-cells = <2>; | |
88 | ranges; | |
89 | ||
90 | internal-regs@d0000000 { | |
91 | #address-cells = <1>; | |
92 | #size-cells = <1>; | |
93 | compatible = "simple-bus"; | |
94 | /* 32M internal register @ 0xd000_0000 */ | |
95 | ranges = <0x0 0x0 0xd0000000 0x2000000>; | |
96 | ||
97 | spi0: spi@10600 { | |
98 | compatible = "marvell,armada-3700-spi"; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | reg = <0x10600 0xA00>; | |
102 | clocks = <&nb_periph_clk 7>; | |
103 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; | |
104 | num-cs = <4>; | |
105 | status = "disabled"; | |
106 | }; | |
107 | ||
108 | i2c0: i2c@11000 { | |
109 | compatible = "marvell,armada-3700-i2c"; | |
110 | reg = <0x11000 0x24>; | |
111 | #address-cells = <1>; | |
112 | #size-cells = <0>; | |
113 | clocks = <&nb_periph_clk 10>; | |
114 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
115 | mrvl,i2c-fast-mode; | |
116 | status = "disabled"; | |
117 | }; | |
118 | ||
119 | i2c1: i2c@11080 { | |
120 | compatible = "marvell,armada-3700-i2c"; | |
121 | reg = <0x11080 0x24>; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <0>; | |
124 | clocks = <&nb_periph_clk 9>; | |
125 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
126 | mrvl,i2c-fast-mode; | |
127 | status = "disabled"; | |
128 | }; | |
129 | ||
130 | uart0: serial@12000 { | |
131 | compatible = "marvell,armada-3700-uart"; | |
132 | reg = <0x12000 0x400>; | |
133 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
137 | nb_periph_clk: nb-periph-clk@13000 { | |
138 | compatible = "marvell,armada-3700-periph-clock-nb"; | |
139 | reg = <0x13000 0x100>; | |
140 | clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, | |
141 | <&tbg 3>, <&xtalclk>; | |
142 | #clock-cells = <1>; | |
143 | }; | |
144 | ||
145 | sb_periph_clk: sb-periph-clk@18000 { | |
146 | compatible = "marvell,armada-3700-periph-clock-sb"; | |
147 | reg = <0x18000 0x100>; | |
148 | clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, | |
149 | <&tbg 3>, <&xtalclk>; | |
150 | #clock-cells = <1>; | |
151 | }; | |
152 | ||
153 | tbg: tbg@13200 { | |
154 | compatible = "marvell,armada-3700-tbg-clock"; | |
155 | reg = <0x13200 0x100>; | |
156 | clocks = <&xtalclk>; | |
157 | #clock-cells = <1>; | |
158 | }; | |
159 | ||
160 | pinctrl_nb: pinctrl@13800 { | |
161 | compatible = "marvell,armada3710-nb-pinctrl", | |
162 | "syscon", "simple-mfd"; | |
163 | reg = <0x13800 0x100>, <0x13C00 0x20>; | |
164 | gpionb: gpio { | |
165 | #gpio-cells = <2>; | |
166 | gpio-ranges = <&pinctrl_nb 0 0 36>; | |
167 | gpio-controller; | |
168 | interrupts = | |
169 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
170 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
171 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
172 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
173 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
181 | ||
182 | }; | |
183 | ||
184 | xtalclk: xtal-clk { | |
185 | compatible = "marvell,armada-3700-xtal-clock"; | |
186 | clock-output-names = "xtal"; | |
187 | #clock-cells = <0>; | |
188 | }; | |
189 | ||
190 | spi_quad_pins: spi-quad-pins { | |
191 | groups = "spi_quad"; | |
192 | function = "spi"; | |
193 | }; | |
194 | ||
195 | i2c1_pins: i2c1-pins { | |
196 | groups = "i2c1"; | |
197 | function = "i2c"; | |
198 | }; | |
199 | ||
200 | i2c2_pins: i2c2-pins { | |
201 | groups = "i2c2"; | |
202 | function = "i2c"; | |
203 | }; | |
204 | ||
205 | uart1_pins: uart1-pins { | |
206 | groups = "uart1"; | |
207 | function = "uart"; | |
208 | }; | |
209 | ||
210 | uart2_pins: uart2-pins { | |
211 | groups = "uart2"; | |
212 | function = "uart"; | |
213 | }; | |
214 | }; | |
215 | ||
216 | pinctrl_sb: pinctrl@18800 { | |
217 | compatible = "marvell,armada3710-sb-pinctrl", | |
218 | "syscon", "simple-mfd"; | |
219 | reg = <0x18800 0x100>, <0x18C00 0x20>; | |
220 | gpiosb: gpio { | |
221 | #gpio-cells = <2>; | |
222 | gpio-ranges = <&pinctrl_sb 0 0 30>; | |
223 | gpio-controller; | |
224 | interrupts = | |
225 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, | |
226 | <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
230 | }; | |
231 | ||
232 | rgmii_pins: mii-pins { | |
233 | groups = "rgmii"; | |
234 | function = "mii"; | |
235 | }; | |
236 | ||
237 | }; | |
238 | ||
239 | eth0: ethernet@30000 { | |
240 | compatible = "marvell,armada-3700-neta"; | |
241 | reg = <0x30000 0x4000>; | |
242 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
243 | clocks = <&sb_periph_clk 8>; | |
244 | status = "disabled"; | |
245 | }; | |
246 | ||
247 | mdio: mdio@32004 { | |
248 | #address-cells = <1>; | |
249 | #size-cells = <0>; | |
250 | compatible = "marvell,orion-mdio"; | |
251 | reg = <0x32004 0x4>; | |
252 | }; | |
253 | ||
254 | eth1: ethernet@40000 { | |
255 | compatible = "marvell,armada-3700-neta"; | |
256 | reg = <0x40000 0x4000>; | |
257 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&sb_periph_clk 7>; | |
259 | status = "disabled"; | |
260 | }; | |
261 | ||
262 | usb3: usb@58000 { | |
263 | compatible = "marvell,armada3700-xhci", | |
264 | "generic-xhci"; | |
265 | reg = <0x58000 0x4000>; | |
266 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
267 | clocks = <&sb_periph_clk 12>; | |
268 | status = "disabled"; | |
269 | }; | |
270 | ||
271 | usb2: usb@5e000 { | |
272 | compatible = "marvell,armada-3700-ehci"; | |
273 | reg = <0x5e000 0x2000>; | |
274 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
275 | status = "disabled"; | |
276 | }; | |
277 | ||
278 | xor@60900 { | |
279 | compatible = "marvell,armada-3700-xor"; | |
280 | reg = <0x60900 0x100>, | |
281 | <0x60b00 0x100>; | |
282 | ||
283 | xor10 { | |
284 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
285 | }; | |
286 | xor11 { | |
287 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
288 | }; | |
289 | }; | |
290 | ||
291 | sdhci1: sdhci@d0000 { | |
292 | compatible = "marvell,armada-3700-sdhci", | |
293 | "marvell,sdhci-xenon"; | |
294 | reg = <0xd0000 0x300>, | |
295 | <0x1e808 0x4>; | |
296 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
297 | clocks = <&nb_periph_clk 0>; | |
298 | clock-names = "core"; | |
299 | status = "disabled"; | |
300 | }; | |
301 | ||
302 | sdhci0: sdhci@d8000 { | |
303 | compatible = "marvell,armada-3700-sdhci", | |
304 | "marvell,sdhci-xenon"; | |
305 | reg = <0xd8000 0x300>, | |
306 | <0x17808 0x4>; | |
307 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
308 | clocks = <&nb_periph_clk 0>; | |
309 | clock-names = "core"; | |
310 | status = "disabled"; | |
311 | }; | |
312 | ||
313 | sata: sata@e0000 { | |
314 | compatible = "marvell,armada-3700-ahci"; | |
315 | reg = <0xe0000 0x2000>; | |
316 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
320 | gic: interrupt-controller@1d00000 { | |
321 | compatible = "arm,gic-v3"; | |
322 | #interrupt-cells = <3>; | |
323 | interrupt-controller; | |
324 | reg = <0x1d00000 0x10000>, /* GICD */ | |
325 | <0x1d40000 0x40000>; /* GICR */ | |
326 | }; | |
327 | }; | |
328 | ||
329 | pcie0: pcie@d0070000 { | |
330 | compatible = "marvell,armada-3700-pcie"; | |
331 | device_type = "pci"; | |
332 | status = "disabled"; | |
333 | reg = <0 0xd0070000 0 0x20000>; | |
334 | #address-cells = <3>; | |
335 | #size-cells = <2>; | |
336 | bus-range = <0x00 0xff>; | |
337 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
338 | #interrupt-cells = <1>; | |
339 | msi-parent = <&pcie0>; | |
340 | msi-controller; | |
341 | ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ | |
342 | 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ | |
343 | interrupt-map-mask = <0 0 0 7>; | |
344 | interrupt-map = <0 0 0 1 &pcie_intc 0>, | |
345 | <0 0 0 2 &pcie_intc 1>, | |
346 | <0 0 0 3 &pcie_intc 2>, | |
347 | <0 0 0 4 &pcie_intc 3>; | |
348 | pcie_intc: interrupt-controller { | |
349 | interrupt-controller; | |
350 | #interrupt-cells = <1>; | |
351 | }; | |
352 | }; | |
353 | }; | |
354 | }; |