[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / include / asm / arch_gicv3.h

/*
 * arch/arm64/include/asm/arch_gicv3.h
 *
 * Copyright (C) 2015 ARM Ltd.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARCH_GICV3_H
#define __ASM_ARCH_GICV3_H

#include <asm/sysreg.h>

#define ICC_IAR0_EL1			sys_reg(3, 0, 12, 8, 0)
#define ICC_EOIR0_EL1			sys_reg(3, 0, 12, 8, 1)
#define ICC_HPPIR0_EL1			sys_reg(3, 0, 12, 8, 2)
#define ICC_BPR0_EL1			sys_reg(3, 0, 12, 8, 3)
#define ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
#define ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
#define ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
#define ICC_GRPEN0_EL1			sys_reg(3, 0, 12, 12, 6)
#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
#define ICC_BPR1_EL1			sys_reg(3, 0, 12, 12, 3)
#define ICC_HPPIR1_EL1			sys_reg(3, 0, 12, 12, 2)
#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

/*
 * System register definitions
 */
#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)

#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)

#define ICH_LR0_EL2			__LR0_EL2(0)
#define ICH_LR1_EL2			__LR0_EL2(1)
#define ICH_LR2_EL2			__LR0_EL2(2)
#define ICH_LR3_EL2			__LR0_EL2(3)
#define ICH_LR4_EL2			__LR0_EL2(4)
#define ICH_LR5_EL2			__LR0_EL2(5)
#define ICH_LR6_EL2			__LR0_EL2(6)
#define ICH_LR7_EL2			__LR0_EL2(7)
#define ICH_LR8_EL2			__LR8_EL2(0)
#define ICH_LR9_EL2			__LR8_EL2(1)
#define ICH_LR10_EL2			__LR8_EL2(2)
#define ICH_LR11_EL2			__LR8_EL2(3)
#define ICH_LR12_EL2			__LR8_EL2(4)
#define ICH_LR13_EL2			__LR8_EL2(5)
#define ICH_LR14_EL2			__LR8_EL2(6)
#define ICH_LR15_EL2			__LR8_EL2(7)

#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)

#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)

#ifndef __ASSEMBLY__

#include <linux/stringify.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>

#define read_gicreg			read_sysreg_s
#define write_gicreg			write_sysreg_s

/*
 * Low-level accessors
 *
 * These system registers are 32 bits, but we make sure that the compiler
 * sets the GP register's most significant bits to 0 with an explicit cast.
 */

static inline void gic_write_eoir(u32 irq)
{
	write_sysreg_s(irq, ICC_EOIR1_EL1);
	isb();
}

static inline void gic_write_dir(u32 irq)
{
	write_sysreg_s(irq, ICC_DIR_EL1);
	isb();
}

static inline u64 gic_read_iar_common(void)
{
	u64 irqstat;

	irqstat = read_sysreg_s(ICC_IAR1_EL1);
	dsb(sy);
	return irqstat;
}

/*
 * Cavium ThunderX erratum 23154
 *
 * The gicv3 of ThunderX requires a modified version for reading the
 * IAR status to ensure data synchronization (access to icc_iar1_el1
 * is not sync'ed before and after).
 */
static inline u64 gic_read_iar_cavium_thunderx(void)
{
	u64 irqstat;

	nops(8);
	irqstat = read_sysreg_s(ICC_IAR1_EL1);
	nops(4);
	mb();

	return irqstat;
}

static inline void gic_write_pmr(u32 val)
{
	write_sysreg_s(val, ICC_PMR_EL1);
}

static inline void gic_write_ctlr(u32 val)
{
	write_sysreg_s(val, ICC_CTLR_EL1);
	isb();
}

static inline void gic_write_grpen1(u32 val)
{
	write_sysreg_s(val, ICC_GRPEN1_EL1);
	isb();
}

static inline void gic_write_sgi1r(u64 val)
{
	write_sysreg_s(val, ICC_SGI1R_EL1);
}

static inline u32 gic_read_sre(void)
{
	return read_sysreg_s(ICC_SRE_EL1);
}

static inline void gic_write_sre(u32 val)
{
	write_sysreg_s(val, ICC_SRE_EL1);
	isb();
}

static inline void gic_write_bpr1(u32 val)
{
	asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
}

#define gic_read_typer(c)		readq_relaxed(c)
#define gic_write_irouter(v, c)		writeq_relaxed(v, c)

#define gic_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))

#define gits_read_baser(c)		readq_relaxed(c)
#define gits_write_baser(v, c)		writeq_relaxed(v, c)

#define gits_read_cbaser(c)		readq_relaxed(c)
#define gits_write_cbaser(v, c)		writeq_relaxed(v, c)

#define gits_write_cwriter(v, c)	writeq_relaxed(v, c)

#define gicr_read_propbaser(c)		readq_relaxed(c)
#define gicr_write_propbaser(v, c)	writeq_relaxed(v, c)

#define gicr_write_pendbaser(v, c)	writeq_relaxed(v, c)
#define gicr_read_pendbaser(c)		readq_relaxed(c)

#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
Commit	Line	Data
	1	/*
	2	* arch/arm64/include/asm/arch_gicv3.h
	3	*
	4	* Copyright (C) 2015 ARM Ltd.
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18	#ifndef __ASM_ARCH_GICV3_H
	19	#define __ASM_ARCH_GICV3_H
	20
	21	#include <asm/sysreg.h>
	22
	23	#define ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
	24	#define ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
	25	#define ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
	26	#define ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
	27	#define ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 \| n)
	28	#define ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
	29	#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
	30	#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
	31	#define ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
	32	#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
	33	#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
	34	#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
	35	#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
	36	#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
	37	#define ICC_GRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
	38	#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
	39	#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
	40	#define ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
	41	#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
	42
	43	/*
	44	* System register definitions
	45	*/
	46	#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
	47	#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
	48	#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
	49	#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
	50	#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
	51	#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
	52	#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
	53
	54	#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
	55	#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
	56
	57	#define ICH_LR0_EL2 __LR0_EL2(0)
	58	#define ICH_LR1_EL2 __LR0_EL2(1)
	59	#define ICH_LR2_EL2 __LR0_EL2(2)
	60	#define ICH_LR3_EL2 __LR0_EL2(3)
	61	#define ICH_LR4_EL2 __LR0_EL2(4)
	62	#define ICH_LR5_EL2 __LR0_EL2(5)
	63	#define ICH_LR6_EL2 __LR0_EL2(6)
	64	#define ICH_LR7_EL2 __LR0_EL2(7)
	65	#define ICH_LR8_EL2 __LR8_EL2(0)
	66	#define ICH_LR9_EL2 __LR8_EL2(1)
	67	#define ICH_LR10_EL2 __LR8_EL2(2)
	68	#define ICH_LR11_EL2 __LR8_EL2(3)
	69	#define ICH_LR12_EL2 __LR8_EL2(4)
	70	#define ICH_LR13_EL2 __LR8_EL2(5)
	71	#define ICH_LR14_EL2 __LR8_EL2(6)
	72	#define ICH_LR15_EL2 __LR8_EL2(7)
	73
	74	#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
	75	#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
	76	#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
	77	#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
	78	#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
	79
	80	#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
	81	#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
	82	#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
	83	#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
	84	#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
	85
	86	#ifndef __ASSEMBLY__
	87
	88	#include <linux/stringify.h>
	89	#include <asm/barrier.h>
	90	#include <asm/cacheflush.h>
	91
	92	#define read_gicreg read_sysreg_s
	93	#define write_gicreg write_sysreg_s
	94
	95	/*
	96	* Low-level accessors
	97	*
	98	* These system registers are 32 bits, but we make sure that the compiler
	99	* sets the GP register's most significant bits to 0 with an explicit cast.
	100	*/
	101
	102	static inline void gic_write_eoir(u32 irq)
	103	{
	104	write_sysreg_s(irq, ICC_EOIR1_EL1);
	105	isb();
	106	}
	107
	108	static inline void gic_write_dir(u32 irq)
	109	{
	110	write_sysreg_s(irq, ICC_DIR_EL1);
	111	isb();
	112	}
	113
	114	static inline u64 gic_read_iar_common(void)
	115	{
	116	u64 irqstat;
	117
	118	irqstat = read_sysreg_s(ICC_IAR1_EL1);
	119	dsb(sy);
	120	return irqstat;
	121	}
	122
	123	/*
	124	* Cavium ThunderX erratum 23154
	125	*
	126	* The gicv3 of ThunderX requires a modified version for reading the
	127	* IAR status to ensure data synchronization (access to icc_iar1_el1
	128	* is not sync'ed before and after).
	129	*/
	130	static inline u64 gic_read_iar_cavium_thunderx(void)
	131	{
	132	u64 irqstat;
	133
	134	nops(8);
	135	irqstat = read_sysreg_s(ICC_IAR1_EL1);
	136	nops(4);
	137	mb();
	138
	139	return irqstat;
	140	}
	141
	142	static inline void gic_write_pmr(u32 val)
	143	{
	144	write_sysreg_s(val, ICC_PMR_EL1);
	145	}
	146
	147	static inline void gic_write_ctlr(u32 val)
	148	{
	149	write_sysreg_s(val, ICC_CTLR_EL1);
	150	isb();
	151	}
	152
	153	static inline void gic_write_grpen1(u32 val)
	154	{
	155	write_sysreg_s(val, ICC_GRPEN1_EL1);
	156	isb();
	157	}
	158
	159	static inline void gic_write_sgi1r(u64 val)
	160	{
	161	write_sysreg_s(val, ICC_SGI1R_EL1);
	162	}
	163
	164	static inline u32 gic_read_sre(void)
	165	{
	166	return read_sysreg_s(ICC_SRE_EL1);
	167	}
	168
	169	static inline void gic_write_sre(u32 val)
	170	{
	171	write_sysreg_s(val, ICC_SRE_EL1);
	172	isb();
	173	}
	174
	175	static inline void gic_write_bpr1(u32 val)
	176	{
	177	asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
	178	}
	179
	180	#define gic_read_typer(c) readq_relaxed(c)
	181	#define gic_write_irouter(v, c) writeq_relaxed(v, c)
	182
	183	#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
	184
	185	#define gits_read_baser(c) readq_relaxed(c)
	186	#define gits_write_baser(v, c) writeq_relaxed(v, c)
	187
	188	#define gits_read_cbaser(c) readq_relaxed(c)
	189	#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
	190
	191	#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
	192
	193	#define gicr_read_propbaser(c) readq_relaxed(c)
	194	#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
	195
	196	#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
	197	#define gicr_read_pendbaser(c) readq_relaxed(c)
	198
	199	#endif /* __ASSEMBLY__ */
	200	#endif /* __ASM_ARCH_GICV3_H */