]>
Commit | Line | Data |
---|---|---|
1 | /* SPDX-License-Identifier: GPL-2.0-only */ | |
2 | /* | |
3 | * arch/arm64/include/asm/cpucaps.h | |
4 | * | |
5 | * Copyright (C) 2016 ARM Ltd. | |
6 | */ | |
7 | #ifndef __ASM_CPUCAPS_H | |
8 | #define __ASM_CPUCAPS_H | |
9 | ||
10 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 | |
11 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 | |
12 | #define ARM64_WORKAROUND_845719 2 | |
13 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 | |
14 | #define ARM64_HAS_PAN 4 | |
15 | #define ARM64_HAS_LSE_ATOMICS 5 | |
16 | #define ARM64_WORKAROUND_CAVIUM_23154 6 | |
17 | #define ARM64_WORKAROUND_834220 7 | |
18 | #define ARM64_HAS_NO_HW_PREFETCH 8 | |
19 | #define ARM64_HAS_VIRT_HOST_EXTN 11 | |
20 | #define ARM64_WORKAROUND_CAVIUM_27456 12 | |
21 | #define ARM64_HAS_32BIT_EL0 13 | |
22 | #define ARM64_SPECTRE_V3A 14 | |
23 | #define ARM64_HAS_CNP 15 | |
24 | #define ARM64_HAS_NO_FPSIMD 16 | |
25 | #define ARM64_WORKAROUND_REPEAT_TLBI 17 | |
26 | #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 | |
27 | #define ARM64_WORKAROUND_858921 19 | |
28 | #define ARM64_WORKAROUND_CAVIUM_30115 20 | |
29 | #define ARM64_HAS_DCPOP 21 | |
30 | #define ARM64_SVE 22 | |
31 | #define ARM64_UNMAP_KERNEL_AT_EL0 23 | |
32 | #define ARM64_SPECTRE_V2 24 | |
33 | #define ARM64_HAS_RAS_EXTN 25 | |
34 | #define ARM64_WORKAROUND_843419 26 | |
35 | #define ARM64_HAS_CACHE_IDC 27 | |
36 | #define ARM64_HAS_CACHE_DIC 28 | |
37 | #define ARM64_HW_DBM 29 | |
38 | #define ARM64_SPECTRE_V4 30 | |
39 | #define ARM64_MISMATCHED_CACHE_TYPE 31 | |
40 | #define ARM64_HAS_STAGE2_FWB 32 | |
41 | #define ARM64_HAS_CRC32 33 | |
42 | #define ARM64_SSBS 34 | |
43 | #define ARM64_WORKAROUND_1418040 35 | |
44 | #define ARM64_HAS_SB 36 | |
45 | #define ARM64_WORKAROUND_SPECULATIVE_AT 37 | |
46 | #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 | |
47 | #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39 | |
48 | #define ARM64_HAS_GENERIC_AUTH_ARCH 40 | |
49 | #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 | |
50 | #define ARM64_HAS_IRQ_PRIO_MASKING 42 | |
51 | #define ARM64_HAS_DCPODP 43 | |
52 | #define ARM64_WORKAROUND_1463225 44 | |
53 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 | |
54 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 | |
55 | #define ARM64_WORKAROUND_1542419 47 | |
56 | #define ARM64_HAS_E0PD 48 | |
57 | #define ARM64_HAS_RNG 49 | |
58 | #define ARM64_HAS_AMU_EXTN 50 | |
59 | #define ARM64_HAS_ADDRESS_AUTH 51 | |
60 | #define ARM64_HAS_GENERIC_AUTH 52 | |
61 | #define ARM64_HAS_32BIT_EL1 53 | |
62 | #define ARM64_BTI 54 | |
63 | #define ARM64_HAS_ARMv8_4_TTL 55 | |
64 | #define ARM64_HAS_TLB_RANGE 56 | |
65 | #define ARM64_MTE 57 | |
66 | #define ARM64_WORKAROUND_1508412 58 | |
67 | #define ARM64_HAS_LDAPR 59 | |
68 | #define ARM64_KVM_PROTECTED_MODE 60 | |
69 | #define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61 | |
70 | ||
71 | #define ARM64_NCAPS 62 | |
72 | ||
73 | #endif /* __ASM_CPUCAPS_H */ |