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1 | /* | |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_CPUTYPE_H | |
17 | #define __ASM_CPUTYPE_H | |
18 | ||
19 | #define INVALID_HWID ULONG_MAX | |
20 | ||
21 | #define MPIDR_UP_BITMASK (0x1 << 30) | |
22 | #define MPIDR_MT_BITMASK (0x1 << 24) | |
23 | #define MPIDR_HWID_BITMASK 0xff00ffffff | |
24 | ||
25 | #define MPIDR_LEVEL_BITS_SHIFT 3 | |
26 | #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) | |
27 | #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) | |
28 | ||
29 | #define MPIDR_LEVEL_SHIFT(level) \ | |
30 | (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) | |
31 | ||
32 | #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ | |
33 | ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) | |
34 | ||
35 | #define MIDR_REVISION_MASK 0xf | |
36 | #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) | |
37 | #define MIDR_PARTNUM_SHIFT 4 | |
38 | #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) | |
39 | #define MIDR_PARTNUM(midr) \ | |
40 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) | |
41 | #define MIDR_ARCHITECTURE_SHIFT 16 | |
42 | #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) | |
43 | #define MIDR_ARCHITECTURE(midr) \ | |
44 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) | |
45 | #define MIDR_VARIANT_SHIFT 20 | |
46 | #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) | |
47 | #define MIDR_VARIANT(midr) \ | |
48 | (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) | |
49 | #define MIDR_IMPLEMENTOR_SHIFT 24 | |
50 | #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) | |
51 | #define MIDR_IMPLEMENTOR(midr) \ | |
52 | (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) | |
53 | ||
54 | #define MIDR_CPU_MODEL(imp, partnum) \ | |
55 | (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ | |
56 | (0xf << MIDR_ARCHITECTURE_SHIFT) | \ | |
57 | ((partnum) << MIDR_PARTNUM_SHIFT)) | |
58 | ||
59 | #define MIDR_CPU_VAR_REV(var, rev) \ | |
60 | (((var) << MIDR_VARIANT_SHIFT) | (rev)) | |
61 | ||
62 | #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ | |
63 | MIDR_ARCHITECTURE_MASK) | |
64 | ||
65 | #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ | |
66 | ({ \ | |
67 | u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ | |
68 | u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ | |
69 | \ | |
70 | _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ | |
71 | }) | |
72 | ||
73 | #define ARM_CPU_IMP_ARM 0x41 | |
74 | #define ARM_CPU_IMP_APM 0x50 | |
75 | #define ARM_CPU_IMP_CAVIUM 0x43 | |
76 | #define ARM_CPU_IMP_BRCM 0x42 | |
77 | #define ARM_CPU_IMP_QCOM 0x51 | |
78 | ||
79 | #define ARM_CPU_PART_AEM_V8 0xD0F | |
80 | #define ARM_CPU_PART_FOUNDATION 0xD00 | |
81 | #define ARM_CPU_PART_CORTEX_A57 0xD07 | |
82 | #define ARM_CPU_PART_CORTEX_A72 0xD08 | |
83 | #define ARM_CPU_PART_CORTEX_A53 0xD03 | |
84 | #define ARM_CPU_PART_CORTEX_A73 0xD09 | |
85 | #define ARM_CPU_PART_CORTEX_A75 0xD0A | |
86 | ||
87 | #define APM_CPU_PART_POTENZA 0x000 | |
88 | ||
89 | #define CAVIUM_CPU_PART_THUNDERX 0x0A1 | |
90 | #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 | |
91 | #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 | |
92 | #define CAVIUM_CPU_PART_THUNDERX2 0x0AF | |
93 | ||
94 | #define BRCM_CPU_PART_VULCAN 0x516 | |
95 | ||
96 | #define QCOM_CPU_PART_FALKOR_V1 0x800 | |
97 | #define QCOM_CPU_PART_FALKOR 0xC00 | |
98 | #define QCOM_CPU_PART_KRYO 0x200 | |
99 | ||
100 | #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) | |
101 | #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) | |
102 | #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) | |
103 | #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) | |
104 | #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) | |
105 | #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) | |
106 | #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) | |
107 | #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) | |
108 | #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) | |
109 | #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) | |
110 | #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) | |
111 | #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) | |
112 | #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) | |
113 | ||
114 | #ifndef __ASSEMBLY__ | |
115 | ||
116 | #include <asm/sysreg.h> | |
117 | ||
118 | #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) | |
119 | ||
120 | /* | |
121 | * The CPU ID never changes at run time, so we might as well tell the | |
122 | * compiler that it's constant. Use this function to read the CPU ID | |
123 | * rather than directly reading processor_id or read_cpuid() directly. | |
124 | */ | |
125 | static inline u32 __attribute_const__ read_cpuid_id(void) | |
126 | { | |
127 | return read_cpuid(MIDR_EL1); | |
128 | } | |
129 | ||
130 | static inline u64 __attribute_const__ read_cpuid_mpidr(void) | |
131 | { | |
132 | return read_cpuid(MPIDR_EL1); | |
133 | } | |
134 | ||
135 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) | |
136 | { | |
137 | return MIDR_IMPLEMENTOR(read_cpuid_id()); | |
138 | } | |
139 | ||
140 | static inline unsigned int __attribute_const__ read_cpuid_part_number(void) | |
141 | { | |
142 | return MIDR_PARTNUM(read_cpuid_id()); | |
143 | } | |
144 | ||
145 | static inline u32 __attribute_const__ read_cpuid_cachetype(void) | |
146 | { | |
147 | return read_cpuid(CTR_EL0); | |
148 | } | |
149 | #endif /* __ASSEMBLY__ */ | |
150 | ||
151 | #endif |