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arm64/mm: Separate boot-time page tables from swapper_pg_dir
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / include / asm / pgtable.h
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1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/bug.h>
20#include <asm/proc-fns.h>
21
22#include <asm/memory.h>
23#include <asm/pgtable-hwdef.h>
24#include <asm/pgtable-prot.h>
25
26/*
27 * VMALLOC range.
28 *
29 * VMALLOC_START: beginning of the kernel vmalloc space
30 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space
31 * and fixed mappings
32 */
33#define VMALLOC_START (MODULES_END)
34#define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
35
36#define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
37
38#define FIRST_USER_ADDRESS 0UL
39
40#ifndef __ASSEMBLY__
41
42#include <asm/cmpxchg.h>
43#include <asm/fixmap.h>
44#include <linux/mmdebug.h>
45#include <linux/mm_types.h>
46#include <linux/sched.h>
47
48extern void __pte_error(const char *file, int line, unsigned long val);
49extern void __pmd_error(const char *file, int line, unsigned long val);
50extern void __pud_error(const char *file, int line, unsigned long val);
51extern void __pgd_error(const char *file, int line, unsigned long val);
52
53/*
54 * ZERO_PAGE is a global shared page that is always zero: used
55 * for zero-mapped memory areas etc..
56 */
57extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
58#define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
59
60#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
61
62/*
63 * Macros to convert between a physical address and its placement in a
64 * page table entry, taking care of 52-bit addresses.
65 */
66#ifdef CONFIG_ARM64_PA_BITS_52
67#define __pte_to_phys(pte) \
68 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
69#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
70#else
71#define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
72#define __phys_to_pte_val(phys) (phys)
73#endif
74
75#define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
76#define pfn_pte(pfn,prot) \
77 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
78
79#define pte_none(pte) (!pte_val(pte))
80#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
81#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
82
83/*
84 * The following only work if pte_present(). Undefined behaviour otherwise.
85 */
86#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
87#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
88#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
89#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
90#define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
91#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
92
93#define pte_cont_addr_end(addr, end) \
94({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
95 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
96})
97
98#define pmd_cont_addr_end(addr, end) \
99({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
100 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
101})
102
103#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
104#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
105#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
106
107#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
108/*
109 * Execute-only user mappings do not have the PTE_USER bit set. All valid
110 * kernel mappings have the PTE_UXN bit set.
111 */
112#define pte_valid_not_user(pte) \
113 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
114#define pte_valid_young(pte) \
115 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
116#define pte_valid_user(pte) \
117 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
118
119/*
120 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
121 * so that we don't erroneously return false for pages that have been
122 * remapped as PROT_NONE but are yet to be flushed from the TLB.
123 */
124#define pte_accessible(mm, pte) \
125 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
126
127/*
128 * p??_access_permitted() is true for valid user mappings (subject to the
129 * write permission check) other than user execute-only which do not have the
130 * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set.
131 */
132#define pte_access_permitted(pte, write) \
133 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
134#define pmd_access_permitted(pmd, write) \
135 (pte_access_permitted(pmd_pte(pmd), (write)))
136#define pud_access_permitted(pud, write) \
137 (pte_access_permitted(pud_pte(pud), (write)))
138
139static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
140{
141 pte_val(pte) &= ~pgprot_val(prot);
142 return pte;
143}
144
145static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
146{
147 pte_val(pte) |= pgprot_val(prot);
148 return pte;
149}
150
151static inline pte_t pte_wrprotect(pte_t pte)
152{
153 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
154 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
155 return pte;
156}
157
158static inline pte_t pte_mkwrite(pte_t pte)
159{
160 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
161 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
162 return pte;
163}
164
165static inline pte_t pte_mkclean(pte_t pte)
166{
167 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
168 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
169
170 return pte;
171}
172
173static inline pte_t pte_mkdirty(pte_t pte)
174{
175 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
176
177 if (pte_write(pte))
178 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
179
180 return pte;
181}
182
183static inline pte_t pte_mkold(pte_t pte)
184{
185 return clear_pte_bit(pte, __pgprot(PTE_AF));
186}
187
188static inline pte_t pte_mkyoung(pte_t pte)
189{
190 return set_pte_bit(pte, __pgprot(PTE_AF));
191}
192
193static inline pte_t pte_mkspecial(pte_t pte)
194{
195 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
196}
197
198static inline pte_t pte_mkcont(pte_t pte)
199{
200 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
201 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
202}
203
204static inline pte_t pte_mknoncont(pte_t pte)
205{
206 return clear_pte_bit(pte, __pgprot(PTE_CONT));
207}
208
209static inline pte_t pte_mkpresent(pte_t pte)
210{
211 return set_pte_bit(pte, __pgprot(PTE_VALID));
212}
213
214static inline pmd_t pmd_mkcont(pmd_t pmd)
215{
216 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
217}
218
219static inline void set_pte(pte_t *ptep, pte_t pte)
220{
221 WRITE_ONCE(*ptep, pte);
222
223 /*
224 * Only if the new pte is valid and kernel, otherwise TLB maintenance
225 * or update_mmu_cache() have the necessary barriers.
226 */
227 if (pte_valid_not_user(pte))
228 dsb(ishst);
229}
230
231extern void __sync_icache_dcache(pte_t pteval);
232
233/*
234 * PTE bits configuration in the presence of hardware Dirty Bit Management
235 * (PTE_WRITE == PTE_DBM):
236 *
237 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
238 * 0 0 | 1 0 0
239 * 0 1 | 1 1 0
240 * 1 0 | 1 0 1
241 * 1 1 | 0 1 x
242 *
243 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
244 * the page fault mechanism. Checking the dirty status of a pte becomes:
245 *
246 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
247 */
248static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
249 pte_t *ptep, pte_t pte)
250{
251 pte_t old_pte;
252
253 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
254 __sync_icache_dcache(pte);
255
256 /*
257 * If the existing pte is valid, check for potential race with
258 * hardware updates of the pte (ptep_set_access_flags safely changes
259 * valid ptes without going through an invalid entry).
260 */
261 old_pte = READ_ONCE(*ptep);
262 if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) &&
263 (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) {
264 VM_WARN_ONCE(!pte_young(pte),
265 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
266 __func__, pte_val(old_pte), pte_val(pte));
267 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
268 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
269 __func__, pte_val(old_pte), pte_val(pte));
270 }
271
272 set_pte(ptep, pte);
273}
274
275#define __HAVE_ARCH_PTE_SAME
276static inline int pte_same(pte_t pte_a, pte_t pte_b)
277{
278 pteval_t lhs, rhs;
279
280 lhs = pte_val(pte_a);
281 rhs = pte_val(pte_b);
282
283 if (pte_present(pte_a))
284 lhs &= ~PTE_RDONLY;
285
286 if (pte_present(pte_b))
287 rhs &= ~PTE_RDONLY;
288
289 return (lhs == rhs);
290}
291
292/*
293 * Huge pte definitions.
294 */
295#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
296#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
297
298/*
299 * Hugetlb definitions.
300 */
301#define HUGE_MAX_HSTATE 4
302#define HPAGE_SHIFT PMD_SHIFT
303#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
304#define HPAGE_MASK (~(HPAGE_SIZE - 1))
305#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
306
307static inline pte_t pgd_pte(pgd_t pgd)
308{
309 return __pte(pgd_val(pgd));
310}
311
312static inline pte_t pud_pte(pud_t pud)
313{
314 return __pte(pud_val(pud));
315}
316
317static inline pmd_t pud_pmd(pud_t pud)
318{
319 return __pmd(pud_val(pud));
320}
321
322static inline pte_t pmd_pte(pmd_t pmd)
323{
324 return __pte(pmd_val(pmd));
325}
326
327static inline pmd_t pte_pmd(pte_t pte)
328{
329 return __pmd(pte_val(pte));
330}
331
332static inline pgprot_t mk_sect_prot(pgprot_t prot)
333{
334 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
335}
336
337#ifdef CONFIG_NUMA_BALANCING
338/*
339 * See the comment in include/asm-generic/pgtable.h
340 */
341static inline int pte_protnone(pte_t pte)
342{
343 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
344}
345
346static inline int pmd_protnone(pmd_t pmd)
347{
348 return pte_protnone(pmd_pte(pmd));
349}
350#endif
351
352/*
353 * THP definitions.
354 */
355
356#ifdef CONFIG_TRANSPARENT_HUGEPAGE
357#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
358#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
359
360#define pmd_present(pmd) pte_present(pmd_pte(pmd))
361#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
362#define pmd_young(pmd) pte_young(pmd_pte(pmd))
363#define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
364#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
365#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
366#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
367#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
368#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
369#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
370#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
371
372#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
373
374#define pmd_write(pmd) pte_write(pmd_pte(pmd))
375
376#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
377
378#define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
379#define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
380#define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
381#define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
382#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
383
384#define pud_write(pud) pte_write(pud_pte(pud))
385
386#define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
387#define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
388#define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
389#define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
390
391#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
392
393#define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
394#define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
395
396#define __pgprot_modify(prot,mask,bits) \
397 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
398
399/*
400 * Mark the prot value as uncacheable and unbufferable.
401 */
402#define pgprot_noncached(prot) \
403 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
404#define pgprot_writecombine(prot) \
405 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
406#define pgprot_device(prot) \
407 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
408#define __HAVE_PHYS_MEM_ACCESS_PROT
409struct file;
410extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
411 unsigned long size, pgprot_t vma_prot);
412
413#define pmd_none(pmd) (!pmd_val(pmd))
414
415#define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
416
417#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
418 PMD_TYPE_TABLE)
419#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
420 PMD_TYPE_SECT)
421
422#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
423#define pud_sect(pud) (0)
424#define pud_table(pud) (1)
425#else
426#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
427 PUD_TYPE_SECT)
428#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
429 PUD_TYPE_TABLE)
430#endif
431
432static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
433{
434 WRITE_ONCE(*pmdp, pmd);
435
436 if (pmd_valid(pmd))
437 dsb(ishst);
438}
439
440static inline void pmd_clear(pmd_t *pmdp)
441{
442 set_pmd(pmdp, __pmd(0));
443}
444
445static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
446{
447 return __pmd_to_phys(pmd);
448}
449
450/* Find an entry in the third-level page table. */
451#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
452
453#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
454#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
455
456#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
457#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
458#define pte_unmap(pte) do { } while (0)
459#define pte_unmap_nested(pte) do { } while (0)
460
461#define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
462#define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
463#define pte_clear_fixmap() clear_fixmap(FIX_PTE)
464
465#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd)))
466
467/* use ONLY for statically allocated translation tables */
468#define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
469
470/*
471 * Conversion functions: convert a page and protection to a page entry,
472 * and a page entry and page directory to the page they refer to.
473 */
474#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
475
476#if CONFIG_PGTABLE_LEVELS > 2
477
478#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
479
480#define pud_none(pud) (!pud_val(pud))
481#define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
482#define pud_present(pud) pte_present(pud_pte(pud))
483#define pud_valid(pud) pte_valid(pud_pte(pud))
484
485static inline void set_pud(pud_t *pudp, pud_t pud)
486{
487 WRITE_ONCE(*pudp, pud);
488
489 if (pud_valid(pud))
490 dsb(ishst);
491}
492
493static inline void pud_clear(pud_t *pudp)
494{
495 set_pud(pudp, __pud(0));
496}
497
498static inline phys_addr_t pud_page_paddr(pud_t pud)
499{
500 return __pud_to_phys(pud);
501}
502
503/* Find an entry in the second-level page table. */
504#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
505
506#define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
507#define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
508
509#define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
510#define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
511#define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
512
513#define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud)))
514
515/* use ONLY for statically allocated translation tables */
516#define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
517
518#else
519
520#define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
521
522/* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
523#define pmd_set_fixmap(addr) NULL
524#define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
525#define pmd_clear_fixmap()
526
527#define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
528
529#endif /* CONFIG_PGTABLE_LEVELS > 2 */
530
531#if CONFIG_PGTABLE_LEVELS > 3
532
533#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
534
535#define pgd_none(pgd) (!pgd_val(pgd))
536#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
537#define pgd_present(pgd) (pgd_val(pgd))
538
539static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
540{
541 WRITE_ONCE(*pgdp, pgd);
542 dsb(ishst);
543}
544
545static inline void pgd_clear(pgd_t *pgdp)
546{
547 set_pgd(pgdp, __pgd(0));
548}
549
550static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
551{
552 return __pgd_to_phys(pgd);
553}
554
555/* Find an entry in the frst-level page table. */
556#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
557
558#define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
559#define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr))))
560
561#define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
562#define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr))
563#define pud_clear_fixmap() clear_fixmap(FIX_PUD)
564
565#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd)))
566
567/* use ONLY for statically allocated translation tables */
568#define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
569
570#else
571
572#define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
573
574/* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
575#define pud_set_fixmap(addr) NULL
576#define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
577#define pud_clear_fixmap()
578
579#define pud_offset_kimg(dir,addr) ((pud_t *)dir)
580
581#endif /* CONFIG_PGTABLE_LEVELS > 3 */
582
583#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
584
585/* to find an entry in a page-table-directory */
586#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
587
588#define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr))
589
590#define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr)))
591
592/* to find an entry in a kernel page-table-directory */
593#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
594
595#define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
596#define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
597
598static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
599{
600 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
601 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
602 /* preserve the hardware dirty information */
603 if (pte_hw_dirty(pte))
604 pte = pte_mkdirty(pte);
605 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
606 return pte;
607}
608
609static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
610{
611 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
612}
613
614#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
615extern int ptep_set_access_flags(struct vm_area_struct *vma,
616 unsigned long address, pte_t *ptep,
617 pte_t entry, int dirty);
618
619#ifdef CONFIG_TRANSPARENT_HUGEPAGE
620#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
621static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
622 unsigned long address, pmd_t *pmdp,
623 pmd_t entry, int dirty)
624{
625 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
626}
627#endif
628
629/*
630 * Atomic pte/pmd modifications.
631 */
632#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
633static inline int __ptep_test_and_clear_young(pte_t *ptep)
634{
635 pte_t old_pte, pte;
636
637 pte = READ_ONCE(*ptep);
638 do {
639 old_pte = pte;
640 pte = pte_mkold(pte);
641 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
642 pte_val(old_pte), pte_val(pte));
643 } while (pte_val(pte) != pte_val(old_pte));
644
645 return pte_young(pte);
646}
647
648static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
649 unsigned long address,
650 pte_t *ptep)
651{
652 return __ptep_test_and_clear_young(ptep);
653}
654
655#ifdef CONFIG_TRANSPARENT_HUGEPAGE
656#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
657static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
658 unsigned long address,
659 pmd_t *pmdp)
660{
661 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
662}
663#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
664
665#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
666static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
667 unsigned long address, pte_t *ptep)
668{
669 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
670}
671
672#ifdef CONFIG_TRANSPARENT_HUGEPAGE
673#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
674static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
675 unsigned long address, pmd_t *pmdp)
676{
677 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
678}
679#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
680
681/*
682 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
683 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
684 */
685#define __HAVE_ARCH_PTEP_SET_WRPROTECT
686static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
687{
688 pte_t old_pte, pte;
689
690 pte = READ_ONCE(*ptep);
691 do {
692 old_pte = pte;
693 /*
694 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
695 * clear), set the PTE_DIRTY bit.
696 */
697 if (pte_hw_dirty(pte))
698 pte = pte_mkdirty(pte);
699 pte = pte_wrprotect(pte);
700 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
701 pte_val(old_pte), pte_val(pte));
702 } while (pte_val(pte) != pte_val(old_pte));
703}
704
705#ifdef CONFIG_TRANSPARENT_HUGEPAGE
706#define __HAVE_ARCH_PMDP_SET_WRPROTECT
707static inline void pmdp_set_wrprotect(struct mm_struct *mm,
708 unsigned long address, pmd_t *pmdp)
709{
710 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
711}
712
713#define pmdp_establish pmdp_establish
714static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
715 unsigned long address, pmd_t *pmdp, pmd_t pmd)
716{
717 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
718}
719#endif
720
721extern pgd_t init_pg_dir[PTRS_PER_PGD];
722extern pgd_t init_pg_end[];
723extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
724extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
725extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
726
727/*
728 * Encode and decode a swap entry:
729 * bits 0-1: present (must be zero)
730 * bits 2-7: swap type
731 * bits 8-57: swap offset
732 * bit 58: PTE_PROT_NONE (must be zero)
733 */
734#define __SWP_TYPE_SHIFT 2
735#define __SWP_TYPE_BITS 6
736#define __SWP_OFFSET_BITS 50
737#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
738#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
739#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
740
741#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
742#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
743#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
744
745#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
746#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
747
748/*
749 * Ensure that there are not more swap files than can be encoded in the kernel
750 * PTEs.
751 */
752#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
753
754extern int kern_addr_valid(unsigned long addr);
755
756#include <asm-generic/pgtable.h>
757
758void pgd_cache_init(void);
759#define pgtable_cache_init pgd_cache_init
760
761/*
762 * On AArch64, the cache coherency is handled via the set_pte_at() function.
763 */
764static inline void update_mmu_cache(struct vm_area_struct *vma,
765 unsigned long addr, pte_t *ptep)
766{
767 /*
768 * We don't do anything here, so there's a very small chance of
769 * us retaking a user fault which we just fixed up. The alternative
770 * is doing a dsb(ishst), but that penalises the fastpath.
771 */
772}
773
774#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
775
776#define kc_vaddr_to_offset(v) ((v) & ~VA_START)
777#define kc_offset_to_vaddr(o) ((o) | VA_START)
778
779#ifdef CONFIG_ARM64_PA_BITS_52
780#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
781#else
782#define phys_to_ttbr(addr) (addr)
783#endif
784
785#endif /* !__ASSEMBLY__ */
786
787#endif /* __ASM_PGTABLE_H */
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