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1 | /* | |
2 | * Based on arch/arm/mm/proc.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | #include <asm/assembler.h> | |
24 | #include <asm/asm-offsets.h> | |
25 | #include <asm/hwcap.h> | |
26 | #include <asm/pgtable.h> | |
27 | #include <asm/pgtable-hwdef.h> | |
28 | #include <asm/cpufeature.h> | |
29 | #include <asm/alternative.h> | |
30 | ||
31 | #ifdef CONFIG_ARM64_64K_PAGES | |
32 | #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K | |
33 | #elif defined(CONFIG_ARM64_16K_PAGES) | |
34 | #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K | |
35 | #else /* CONFIG_ARM64_4K_PAGES */ | |
36 | #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K | |
37 | #endif | |
38 | ||
39 | #define TCR_SMP_FLAGS TCR_SHARED | |
40 | ||
41 | /* PTWs cacheable, inner/outer WBWA */ | |
42 | #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | |
43 | ||
44 | #define MAIR(attr, mt) ((attr) << ((mt) * 8)) | |
45 | ||
46 | /* | |
47 | * cpu_do_idle() | |
48 | * | |
49 | * Idle the processor (wait for interrupt). | |
50 | */ | |
51 | ENTRY(cpu_do_idle) | |
52 | dsb sy // WFI may enter a low-power mode | |
53 | wfi | |
54 | ret | |
55 | ENDPROC(cpu_do_idle) | |
56 | ||
57 | #ifdef CONFIG_CPU_PM | |
58 | /** | |
59 | * cpu_do_suspend - save CPU registers context | |
60 | * | |
61 | * x0: virtual address of context pointer | |
62 | */ | |
63 | ENTRY(cpu_do_suspend) | |
64 | mrs x2, tpidr_el0 | |
65 | mrs x3, tpidrro_el0 | |
66 | mrs x4, contextidr_el1 | |
67 | mrs x5, cpacr_el1 | |
68 | mrs x6, tcr_el1 | |
69 | mrs x7, vbar_el1 | |
70 | mrs x8, mdscr_el1 | |
71 | mrs x9, oslsr_el1 | |
72 | mrs x10, sctlr_el1 | |
73 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN | |
74 | mrs x11, tpidr_el1 | |
75 | alternative_else | |
76 | mrs x11, tpidr_el2 | |
77 | alternative_endif | |
78 | mrs x12, sp_el0 | |
79 | stp x2, x3, [x0] | |
80 | stp x4, xzr, [x0, #16] | |
81 | stp x5, x6, [x0, #32] | |
82 | stp x7, x8, [x0, #48] | |
83 | stp x9, x10, [x0, #64] | |
84 | stp x11, x12, [x0, #80] | |
85 | ret | |
86 | ENDPROC(cpu_do_suspend) | |
87 | ||
88 | /** | |
89 | * cpu_do_resume - restore CPU register context | |
90 | * | |
91 | * x0: Address of context pointer | |
92 | */ | |
93 | .pushsection ".idmap.text", "awx" | |
94 | ENTRY(cpu_do_resume) | |
95 | ldp x2, x3, [x0] | |
96 | ldp x4, x5, [x0, #16] | |
97 | ldp x6, x8, [x0, #32] | |
98 | ldp x9, x10, [x0, #48] | |
99 | ldp x11, x12, [x0, #64] | |
100 | ldp x13, x14, [x0, #80] | |
101 | msr tpidr_el0, x2 | |
102 | msr tpidrro_el0, x3 | |
103 | msr contextidr_el1, x4 | |
104 | msr cpacr_el1, x6 | |
105 | ||
106 | /* Don't change t0sz here, mask those bits when restoring */ | |
107 | mrs x5, tcr_el1 | |
108 | bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH | |
109 | ||
110 | msr tcr_el1, x8 | |
111 | msr vbar_el1, x9 | |
112 | ||
113 | /* | |
114 | * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking | |
115 | * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug | |
116 | * exception. Mask them until local_daif_restore() in cpu_suspend() | |
117 | * resets them. | |
118 | */ | |
119 | disable_daif | |
120 | msr mdscr_el1, x10 | |
121 | ||
122 | msr sctlr_el1, x12 | |
123 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN | |
124 | msr tpidr_el1, x13 | |
125 | alternative_else | |
126 | msr tpidr_el2, x13 | |
127 | alternative_endif | |
128 | msr sp_el0, x14 | |
129 | /* | |
130 | * Restore oslsr_el1 by writing oslar_el1 | |
131 | */ | |
132 | ubfx x11, x11, #1, #1 | |
133 | msr oslar_el1, x11 | |
134 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 | |
135 | isb | |
136 | ret | |
137 | ENDPROC(cpu_do_resume) | |
138 | .popsection | |
139 | #endif | |
140 | ||
141 | /* | |
142 | * cpu_do_switch_mm(pgd_phys, tsk) | |
143 | * | |
144 | * Set the translation table base pointer to be pgd_phys. | |
145 | * | |
146 | * - pgd_phys - physical address of new TTB | |
147 | */ | |
148 | ENTRY(cpu_do_switch_mm) | |
149 | mrs x2, ttbr1_el1 | |
150 | mmid x1, x1 // get mm->context.id | |
151 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
152 | bfi x0, x1, #48, #16 // set the ASID field in TTBR0 | |
153 | #endif | |
154 | bfi x2, x1, #48, #16 // set the ASID | |
155 | msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) | |
156 | isb | |
157 | msr ttbr0_el1, x0 // now update TTBR0 | |
158 | isb | |
159 | b post_ttbr_update_workaround // Back to C code... | |
160 | ENDPROC(cpu_do_switch_mm) | |
161 | ||
162 | .pushsection ".idmap.text", "awx" | |
163 | ||
164 | .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 | |
165 | adrp \tmp1, empty_zero_page | |
166 | msr ttbr1_el1, \tmp1 | |
167 | isb | |
168 | tlbi vmalle1 | |
169 | dsb nsh | |
170 | isb | |
171 | .endm | |
172 | ||
173 | /* | |
174 | * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) | |
175 | * | |
176 | * This is the low-level counterpart to cpu_replace_ttbr1, and should not be | |
177 | * called by anything else. It can only be executed from a TTBR0 mapping. | |
178 | */ | |
179 | ENTRY(idmap_cpu_replace_ttbr1) | |
180 | save_and_disable_daif flags=x2 | |
181 | ||
182 | __idmap_cpu_set_reserved_ttbr1 x1, x3 | |
183 | ||
184 | msr ttbr1_el1, x0 | |
185 | isb | |
186 | ||
187 | restore_daif x2 | |
188 | ||
189 | ret | |
190 | ENDPROC(idmap_cpu_replace_ttbr1) | |
191 | .popsection | |
192 | ||
193 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 | |
194 | .pushsection ".idmap.text", "awx" | |
195 | ||
196 | .macro __idmap_kpti_get_pgtable_ent, type | |
197 | dc cvac, cur_\()\type\()p // Ensure any existing dirty | |
198 | dmb sy // lines are written back before | |
199 | ldr \type, [cur_\()\type\()p] // loading the entry | |
200 | tbz \type, #0, skip_\()\type // Skip invalid and | |
201 | tbnz \type, #11, skip_\()\type // non-global entries | |
202 | .endm | |
203 | ||
204 | .macro __idmap_kpti_put_pgtable_ent_ng, type | |
205 | orr \type, \type, #PTE_NG // Same bit for blocks and pages | |
206 | str \type, [cur_\()\type\()p] // Update the entry and ensure it | |
207 | dc civac, cur_\()\type\()p // is visible to all CPUs. | |
208 | .endm | |
209 | ||
210 | /* | |
211 | * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper) | |
212 | * | |
213 | * Called exactly once from stop_machine context by each CPU found during boot. | |
214 | */ | |
215 | __idmap_kpti_flag: | |
216 | .long 1 | |
217 | ENTRY(idmap_kpti_install_ng_mappings) | |
218 | cpu .req w0 | |
219 | num_cpus .req w1 | |
220 | swapper_pa .req x2 | |
221 | swapper_ttb .req x3 | |
222 | flag_ptr .req x4 | |
223 | cur_pgdp .req x5 | |
224 | end_pgdp .req x6 | |
225 | pgd .req x7 | |
226 | cur_pudp .req x8 | |
227 | end_pudp .req x9 | |
228 | pud .req x10 | |
229 | cur_pmdp .req x11 | |
230 | end_pmdp .req x12 | |
231 | pmd .req x13 | |
232 | cur_ptep .req x14 | |
233 | end_ptep .req x15 | |
234 | pte .req x16 | |
235 | ||
236 | mrs swapper_ttb, ttbr1_el1 | |
237 | adr flag_ptr, __idmap_kpti_flag | |
238 | ||
239 | cbnz cpu, __idmap_kpti_secondary | |
240 | ||
241 | /* We're the boot CPU. Wait for the others to catch up */ | |
242 | sevl | |
243 | 1: wfe | |
244 | ldaxr w18, [flag_ptr] | |
245 | eor w18, w18, num_cpus | |
246 | cbnz w18, 1b | |
247 | ||
248 | /* We need to walk swapper, so turn off the MMU. */ | |
249 | pre_disable_mmu_workaround | |
250 | mrs x18, sctlr_el1 | |
251 | bic x18, x18, #SCTLR_ELx_M | |
252 | msr sctlr_el1, x18 | |
253 | isb | |
254 | ||
255 | /* Everybody is enjoying the idmap, so we can rewrite swapper. */ | |
256 | /* PGD */ | |
257 | mov cur_pgdp, swapper_pa | |
258 | add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8) | |
259 | do_pgd: __idmap_kpti_get_pgtable_ent pgd | |
260 | tbnz pgd, #1, walk_puds | |
261 | next_pgd: | |
262 | __idmap_kpti_put_pgtable_ent_ng pgd | |
263 | skip_pgd: | |
264 | add cur_pgdp, cur_pgdp, #8 | |
265 | cmp cur_pgdp, end_pgdp | |
266 | b.ne do_pgd | |
267 | ||
268 | /* Publish the updated tables and nuke all the TLBs */ | |
269 | dsb sy | |
270 | tlbi vmalle1is | |
271 | dsb ish | |
272 | isb | |
273 | ||
274 | /* We're done: fire up the MMU again */ | |
275 | mrs x18, sctlr_el1 | |
276 | orr x18, x18, #SCTLR_ELx_M | |
277 | msr sctlr_el1, x18 | |
278 | isb | |
279 | ||
280 | /* Set the flag to zero to indicate that we're all done */ | |
281 | str wzr, [flag_ptr] | |
282 | ret | |
283 | ||
284 | /* PUD */ | |
285 | walk_puds: | |
286 | .if CONFIG_PGTABLE_LEVELS > 3 | |
287 | pte_to_phys cur_pudp, pgd | |
288 | add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8) | |
289 | do_pud: __idmap_kpti_get_pgtable_ent pud | |
290 | tbnz pud, #1, walk_pmds | |
291 | next_pud: | |
292 | __idmap_kpti_put_pgtable_ent_ng pud | |
293 | skip_pud: | |
294 | add cur_pudp, cur_pudp, 8 | |
295 | cmp cur_pudp, end_pudp | |
296 | b.ne do_pud | |
297 | b next_pgd | |
298 | .else /* CONFIG_PGTABLE_LEVELS <= 3 */ | |
299 | mov pud, pgd | |
300 | b walk_pmds | |
301 | next_pud: | |
302 | b next_pgd | |
303 | .endif | |
304 | ||
305 | /* PMD */ | |
306 | walk_pmds: | |
307 | .if CONFIG_PGTABLE_LEVELS > 2 | |
308 | pte_to_phys cur_pmdp, pud | |
309 | add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8) | |
310 | do_pmd: __idmap_kpti_get_pgtable_ent pmd | |
311 | tbnz pmd, #1, walk_ptes | |
312 | next_pmd: | |
313 | __idmap_kpti_put_pgtable_ent_ng pmd | |
314 | skip_pmd: | |
315 | add cur_pmdp, cur_pmdp, #8 | |
316 | cmp cur_pmdp, end_pmdp | |
317 | b.ne do_pmd | |
318 | b next_pud | |
319 | .else /* CONFIG_PGTABLE_LEVELS <= 2 */ | |
320 | mov pmd, pud | |
321 | b walk_ptes | |
322 | next_pmd: | |
323 | b next_pud | |
324 | .endif | |
325 | ||
326 | /* PTE */ | |
327 | walk_ptes: | |
328 | pte_to_phys cur_ptep, pmd | |
329 | add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8) | |
330 | do_pte: __idmap_kpti_get_pgtable_ent pte | |
331 | __idmap_kpti_put_pgtable_ent_ng pte | |
332 | skip_pte: | |
333 | add cur_ptep, cur_ptep, #8 | |
334 | cmp cur_ptep, end_ptep | |
335 | b.ne do_pte | |
336 | b next_pmd | |
337 | ||
338 | /* Secondary CPUs end up here */ | |
339 | __idmap_kpti_secondary: | |
340 | /* Uninstall swapper before surgery begins */ | |
341 | __idmap_cpu_set_reserved_ttbr1 x18, x17 | |
342 | ||
343 | /* Increment the flag to let the boot CPU we're ready */ | |
344 | 1: ldxr w18, [flag_ptr] | |
345 | add w18, w18, #1 | |
346 | stxr w17, w18, [flag_ptr] | |
347 | cbnz w17, 1b | |
348 | ||
349 | /* Wait for the boot CPU to finish messing around with swapper */ | |
350 | sevl | |
351 | 1: wfe | |
352 | ldxr w18, [flag_ptr] | |
353 | cbnz w18, 1b | |
354 | ||
355 | /* All done, act like nothing happened */ | |
356 | msr ttbr1_el1, swapper_ttb | |
357 | isb | |
358 | ret | |
359 | ||
360 | .unreq cpu | |
361 | .unreq num_cpus | |
362 | .unreq swapper_pa | |
363 | .unreq swapper_ttb | |
364 | .unreq flag_ptr | |
365 | .unreq cur_pgdp | |
366 | .unreq end_pgdp | |
367 | .unreq pgd | |
368 | .unreq cur_pudp | |
369 | .unreq end_pudp | |
370 | .unreq pud | |
371 | .unreq cur_pmdp | |
372 | .unreq end_pmdp | |
373 | .unreq pmd | |
374 | .unreq cur_ptep | |
375 | .unreq end_ptep | |
376 | .unreq pte | |
377 | ENDPROC(idmap_kpti_install_ng_mappings) | |
378 | .popsection | |
379 | #endif | |
380 | ||
381 | /* | |
382 | * __cpu_setup | |
383 | * | |
384 | * Initialise the processor for turning the MMU on. Return in x0 the | |
385 | * value of the SCTLR_EL1 register. | |
386 | */ | |
387 | .pushsection ".idmap.text", "awx" | |
388 | ENTRY(__cpu_setup) | |
389 | tlbi vmalle1 // Invalidate local TLB | |
390 | dsb nsh | |
391 | ||
392 | mov x0, #3 << 20 | |
393 | msr cpacr_el1, x0 // Enable FP/ASIMD | |
394 | mov x0, #1 << 12 // Reset mdscr_el1 and disable | |
395 | msr mdscr_el1, x0 // access to the DCC from EL0 | |
396 | isb // Unmask debug exceptions now, | |
397 | enable_dbg // since this is per-cpu | |
398 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 | |
399 | /* | |
400 | * Memory region attributes for LPAE: | |
401 | * | |
402 | * n = AttrIndx[2:0] | |
403 | * n MAIR | |
404 | * DEVICE_nGnRnE 000 00000000 | |
405 | * DEVICE_nGnRE 001 00000100 | |
406 | * DEVICE_GRE 010 00001100 | |
407 | * NORMAL_NC 011 01000100 | |
408 | * NORMAL 100 11111111 | |
409 | * NORMAL_WT 101 10111011 | |
410 | */ | |
411 | ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ | |
412 | MAIR(0x04, MT_DEVICE_nGnRE) | \ | |
413 | MAIR(0x0c, MT_DEVICE_GRE) | \ | |
414 | MAIR(0x44, MT_NORMAL_NC) | \ | |
415 | MAIR(0xff, MT_NORMAL) | \ | |
416 | MAIR(0xbb, MT_NORMAL_WT) | |
417 | msr mair_el1, x5 | |
418 | /* | |
419 | * Prepare SCTLR | |
420 | */ | |
421 | mov_q x0, SCTLR_EL1_SET | |
422 | /* | |
423 | * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for | |
424 | * both user and kernel. | |
425 | */ | |
426 | ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ | |
427 | TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 | |
428 | tcr_set_idmap_t0sz x10, x9 | |
429 | ||
430 | /* | |
431 | * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in | |
432 | * TCR_EL1. | |
433 | */ | |
434 | mrs x9, ID_AA64MMFR0_EL1 | |
435 | bfi x10, x9, #32, #3 | |
436 | #ifdef CONFIG_ARM64_HW_AFDBM | |
437 | /* | |
438 | * Hardware update of the Access and Dirty bits. | |
439 | */ | |
440 | mrs x9, ID_AA64MMFR1_EL1 | |
441 | and x9, x9, #0xf | |
442 | cbz x9, 2f | |
443 | cmp x9, #2 | |
444 | b.lt 1f | |
445 | orr x10, x10, #TCR_HD // hardware Dirty flag update | |
446 | 1: orr x10, x10, #TCR_HA // hardware Access flag update | |
447 | 2: | |
448 | #endif /* CONFIG_ARM64_HW_AFDBM */ | |
449 | msr tcr_el1, x10 | |
450 | ret // return to head.S | |
451 | ENDPROC(__cpu_setup) |