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Hibernation: Clean up Kconfig (V2)
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1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6mainmenu "Blackfin Kernel Configuration"
7
8config MMU
9 bool
10 default n
11
12config FPU
13 bool
14 default n
15
16config RWSEM_GENERIC_SPINLOCK
17 bool
18 default y
19
20config RWSEM_XCHGADD_ALGORITHM
21 bool
22 default n
23
24config BLACKFIN
25 bool
26 default y
27
28config ZONE_DMA
29 bool
30 default y
31
32config SEMAPHORE_SLEEPERS
33 bool
34 default y
35
36config GENERIC_FIND_NEXT_BIT
37 bool
38 default y
39
40config GENERIC_HWEIGHT
41 bool
42 default y
43
44config GENERIC_HARDIRQS
45 bool
46 default y
47
48config GENERIC_IRQ_PROBE
49 bool
50 default y
51
52config GENERIC_TIME
53 bool
54 default n
55
56config GENERIC_GPIO
57 bool
58 default y
59
60config FORCE_MAX_ZONEORDER
61 int
62 default "14"
63
64config GENERIC_CALIBRATE_DELAY
65 bool
66 default y
67
68config HARDWARE_PM
69 def_bool y
70 depends on OPROFILE
71
72source "init/Kconfig"
73source "kernel/Kconfig.preempt"
74
75menu "Blackfin Processor Options"
76
77comment "Processor and Board Settings"
78
79choice
80 prompt "CPU"
81 default BF533
82
83config BF522
84 bool "BF522"
85 help
86 BF522 Processor Support.
87
88config BF523
89 bool "BF523"
90 help
91 BF523 Processor Support.
92
93config BF524
94 bool "BF524"
95 help
96 BF524 Processor Support.
97
98config BF525
99 bool "BF525"
100 help
101 BF525 Processor Support.
102
103config BF526
104 bool "BF526"
105 help
106 BF526 Processor Support.
107
108config BF527
109 bool "BF527"
110 help
111 BF527 Processor Support.
112
113config BF531
114 bool "BF531"
115 help
116 BF531 Processor Support.
117
118config BF532
119 bool "BF532"
120 help
121 BF532 Processor Support.
122
123config BF533
124 bool "BF533"
125 help
126 BF533 Processor Support.
127
128config BF534
129 bool "BF534"
130 help
131 BF534 Processor Support.
132
133config BF536
134 bool "BF536"
135 help
136 BF536 Processor Support.
137
138config BF537
139 bool "BF537"
140 help
141 BF537 Processor Support.
142
143config BF542
144 bool "BF542"
145 help
146 BF542 Processor Support.
147
148config BF544
149 bool "BF544"
150 help
151 BF544 Processor Support.
152
153config BF547
154 bool "BF547"
155 help
156 BF547 Processor Support.
157
158config BF548
159 bool "BF548"
160 help
161 BF548 Processor Support.
162
163config BF549
164 bool "BF549"
165 help
166 BF549 Processor Support.
167
168config BF561
169 bool "BF561"
170 help
171 Not Supported Yet - Work in progress - BF561 Processor Support.
172
173endchoice
174
175choice
176 prompt "Silicon Rev"
177 default BF_REV_0_1 if BF527
178 default BF_REV_0_2 if BF537
179 default BF_REV_0_3 if BF533
180 default BF_REV_0_0 if BF549
181
182config BF_REV_0_0
183 bool "0.0"
184 depends on (BF52x || BF54x)
185
186config BF_REV_0_1
187 bool "0.1"
188 depends on (BF52x || BF54x)
189
190config BF_REV_0_2
191 bool "0.2"
192 depends on (BF537 || BF536 || BF534)
193
194config BF_REV_0_3
195 bool "0.3"
196 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
197
198config BF_REV_0_4
199 bool "0.4"
200 depends on (BF561 || BF533 || BF532 || BF531)
201
202config BF_REV_0_5
203 bool "0.5"
204 depends on (BF561 || BF533 || BF532 || BF531)
205
206config BF_REV_ANY
207 bool "any"
208
209config BF_REV_NONE
210 bool "none"
211
212endchoice
213
214config BF52x
215 bool
216 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
217 default y
218
219config BF53x
220 bool
221 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
222 default y
223
224config BF54x
225 bool
226 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
227 default y
228
229config BFIN_DUAL_CORE
230 bool
231 depends on (BF561)
232 default y
233
234config BFIN_SINGLE_CORE
235 bool
236 depends on !BFIN_DUAL_CORE
237 default y
238
239config MEM_GENERIC_BOARD
240 bool
241 depends on GENERIC_BOARD
242 default y
243
244config MEM_MT48LC64M4A2FB_7E
245 bool
246 depends on (BFIN533_STAMP)
247 default y
248
249config MEM_MT48LC16M16A2TG_75
250 bool
251 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
252 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
253 || H8606_HVSISTEMAS)
254 default y
255
256config MEM_MT48LC32M8A2_75
257 bool
258 depends on (BFIN537_STAMP || PNAV10)
259 default y
260
261config MEM_MT48LC8M32B2B5_7
262 bool
263 depends on (BFIN561_BLUETECHNIX_CM)
264 default y
265
266config MEM_MT48LC32M16A2TG_75
267 bool
268 depends on (BFIN527_EZKIT)
269 default y
270
271source "arch/blackfin/mach-bf527/Kconfig"
272source "arch/blackfin/mach-bf533/Kconfig"
273source "arch/blackfin/mach-bf561/Kconfig"
274source "arch/blackfin/mach-bf537/Kconfig"
275source "arch/blackfin/mach-bf548/Kconfig"
276
277menu "Board customizations"
278
279config CMDLINE_BOOL
280 bool "Default bootloader kernel arguments"
281
282config CMDLINE
283 string "Initial kernel command string"
284 depends on CMDLINE_BOOL
285 default "console=ttyBF0,57600"
286 help
287 If you don't have a boot loader capable of passing a command line string
288 to the kernel, you may specify one here. As a minimum, you should specify
289 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
290
291comment "Clock/PLL Setup"
292
293config CLKIN_HZ
294 int "Crystal Frequency in Hz"
295 default "11059200" if BFIN533_STAMP
296 default "27000000" if BFIN533_EZKIT
297 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
298 default "30000000" if BFIN561_EZKIT
299 default "24576000" if PNAV10
300 help
301 The frequency of CLKIN crystal oscillator on the board in Hz.
302
303config BFIN_KERNEL_CLOCK
304 bool "Re-program Clocks while Kernel boots?"
305 default n
306 help
307 This option decides if kernel clocks are re-programed from the
308 bootloader settings. If the clocks are not set, the SDRAM settings
309 are also not changed, and the Bootloader does 100% of the hardware
310 configuration.
311
312config PLL_BYPASS
313 bool "Bypass PLL"
314 depends on BFIN_KERNEL_CLOCK
315 default n
316
317config CLKIN_HALF
318 bool "Half Clock In"
319 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
320 default n
321 help
322 If this is set the clock will be divided by 2, before it goes to the PLL.
323
324config VCO_MULT
325 int "VCO Multiplier"
326 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
327 range 1 64
328 default "22" if BFIN533_EZKIT
329 default "45" if BFIN533_STAMP
330 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
331 default "22" if BFIN533_BLUETECHNIX_CM
332 default "20" if BFIN537_BLUETECHNIX_CM
333 default "20" if BFIN561_BLUETECHNIX_CM
334 default "20" if BFIN561_EZKIT
335 default "16" if H8606_HVSISTEMAS
336 help
337 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
338 PLL Frequency = (Crystal Frequency) * (this setting)
339
340choice
341 prompt "Core Clock Divider"
342 depends on BFIN_KERNEL_CLOCK
343 default CCLK_DIV_1
344 help
345 This sets the frequency of the core. It can be 1, 2, 4 or 8
346 Core Frequency = (PLL frequency) / (this setting)
347
348config CCLK_DIV_1
349 bool "1"
350
351config CCLK_DIV_2
352 bool "2"
353
354config CCLK_DIV_4
355 bool "4"
356
357config CCLK_DIV_8
358 bool "8"
359endchoice
360
361config SCLK_DIV
362 int "System Clock Divider"
363 depends on BFIN_KERNEL_CLOCK
364 range 1 15
365 default 5 if BFIN533_EZKIT
366 default 5 if BFIN533_STAMP
367 default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
368 default 5 if BFIN533_BLUETECHNIX_CM
369 default 4 if BFIN537_BLUETECHNIX_CM
370 default 4 if BFIN561_BLUETECHNIX_CM
371 default 5 if BFIN561_EZKIT
372 default 3 if H8606_HVSISTEMAS
373 help
374 This sets the frequency of the system clock (including SDRAM or DDR).
375 This can be between 1 and 15
376 System Clock = (PLL frequency) / (this setting)
377
378#
379# Max & Min Speeds for various Chips
380#
381config MAX_VCO_HZ
382 int
383 default 600000000 if BF522
384 default 400000000 if BF523
385 default 400000000 if BF524
386 default 600000000 if BF525
387 default 400000000 if BF526
388 default 600000000 if BF527
389 default 400000000 if BF531
390 default 400000000 if BF532
391 default 750000000 if BF533
392 default 500000000 if BF534
393 default 400000000 if BF536
394 default 600000000 if BF537
395 default 533333333 if BF538
396 default 533333333 if BF539
397 default 600000000 if BF542
398 default 533333333 if BF544
399 default 600000000 if BF547
400 default 600000000 if BF548
401 default 533333333 if BF549
402 default 600000000 if BF561
403
404config MIN_VCO_HZ
405 int
406 default 50000000
407
408config MAX_SCLK_HZ
409 int
410 default 133333333
411
412config MIN_SCLK_HZ
413 int
414 default 27000000
415
416comment "Kernel Timer/Scheduler"
417
418source kernel/Kconfig.hz
419
420comment "Memory Setup"
421
422config MEM_SIZE
423 int "SDRAM Memory Size in MBytes"
424 default 32 if BFIN533_EZKIT
425 default 64 if BFIN527_EZKIT
426 default 64 if BFIN537_STAMP
427 default 64 if BFIN548_EZKIT
428 default 64 if BFIN561_EZKIT
429 default 128 if BFIN533_STAMP
430 default 64 if PNAV10
431 default 32 if H8606_HVSISTEMAS
432
433config MEM_ADD_WIDTH
434 int "SDRAM Memory Address Width"
435 depends on (!BF54x)
436 default 9 if BFIN533_EZKIT
437 default 9 if BFIN561_EZKIT
438 default 9 if H8606_HVSISTEMAS
439 default 10 if BFIN527_EZKIT
440 default 10 if BFIN537_STAMP
441 default 11 if BFIN533_STAMP
442 default 10 if PNAV10
443
444
445choice
446 prompt "DDR SDRAM Chip Type"
447 depends on BFIN548_EZKIT
448 default MEM_MT46V32M16_5B
449
450config MEM_MT46V32M16_6T
451 bool "MT46V32M16_6T"
452
453config MEM_MT46V32M16_5B
454 bool "MT46V32M16_5B"
455endchoice
456
457config ENET_FLASH_PIN
458 int "PF port/pin used for flash and ethernet sharing"
459 depends on (BFIN533_STAMP)
460 default 0
461 help
462 PF port/pin used for flash and ethernet sharing to allow other PF
463 pins to be used on other platforms without having to touch common
464 code.
465 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
466
467config BOOT_LOAD
468 hex "Kernel load address for booting"
469 default "0x1000"
470 range 0x1000 0x20000000
471 help
472 This option allows you to set the load address of the kernel.
473 This can be useful if you are on a board which has a small amount
474 of memory or you wish to reserve some memory at the beginning of
475 the address space.
476
477 Note that you need to keep this value above 4k (0x1000) as this
478 memory region is used to capture NULL pointer references as well
479 as some core kernel functions.
480
481choice
482 prompt "Blackfin Exception Scratch Register"
483 default BFIN_SCRATCH_REG_RETN
484 help
485 Select the resource to reserve for the Exception handler:
486 - RETN: Non-Maskable Interrupt (NMI)
487 - RETE: Exception Return (JTAG/ICE)
488 - CYCLES: Performance counter
489
490 If you are unsure, please select "RETN".
491
492config BFIN_SCRATCH_REG_RETN
493 bool "RETN"
494 help
495 Use the RETN register in the Blackfin exception handler
496 as a stack scratch register. This means you cannot
497 safely use NMI on the Blackfin while running Linux, but
498 you can debug the system with a JTAG ICE and use the
499 CYCLES performance registers.
500
501 If you are unsure, please select "RETN".
502
503config BFIN_SCRATCH_REG_RETE
504 bool "RETE"
505 help
506 Use the RETE register in the Blackfin exception handler
507 as a stack scratch register. This means you cannot
508 safely use a JTAG ICE while debugging a Blackfin board,
509 but you can safely use the CYCLES performance registers
510 and the NMI.
511
512 If you are unsure, please select "RETN".
513
514config BFIN_SCRATCH_REG_CYCLES
515 bool "CYCLES"
516 help
517 Use the CYCLES register in the Blackfin exception handler
518 as a stack scratch register. This means you cannot
519 safely use the CYCLES performance registers on a Blackfin
520 board at anytime, but you can debug the system with a JTAG
521 ICE and use the NMI.
522
523 If you are unsure, please select "RETN".
524
525endchoice
526
527endmenu
528
529
530menu "Blackfin Kernel Optimizations"
531
532comment "Memory Optimizations"
533
534config I_ENTRY_L1
535 bool "Locate interrupt entry code in L1 Memory"
536 default y
537 help
538 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
539 into L1 instruction memory. (less latency)
540
541config EXCPT_IRQ_SYSC_L1
542 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
543 default y
544 help
545 If enabled, the entire ASM lowlevel exception and interrupt entry code
546 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
547 (less latency)
548
549config DO_IRQ_L1
550 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
551 default y
552 help
553 If enabled, the frequently called do_irq dispatcher function is linked
554 into L1 instruction memory. (less latency)
555
556config CORE_TIMER_IRQ_L1
557 bool "Locate frequently called timer_interrupt() function in L1 Memory"
558 default y
559 help
560 If enabled, the frequently called timer_interrupt() function is linked
561 into L1 instruction memory. (less latency)
562
563config IDLE_L1
564 bool "Locate frequently idle function in L1 Memory"
565 default y
566 help
567 If enabled, the frequently called idle function is linked
568 into L1 instruction memory. (less latency)
569
570config SCHEDULE_L1
571 bool "Locate kernel schedule function in L1 Memory"
572 default y
573 help
574 If enabled, the frequently called kernel schedule is linked
575 into L1 instruction memory. (less latency)
576
577config ARITHMETIC_OPS_L1
578 bool "Locate kernel owned arithmetic functions in L1 Memory"
579 default y
580 help
581 If enabled, arithmetic functions are linked
582 into L1 instruction memory. (less latency)
583
584config ACCESS_OK_L1
585 bool "Locate access_ok function in L1 Memory"
586 default y
587 help
588 If enabled, the access_ok function is linked
589 into L1 instruction memory. (less latency)
590
591config MEMSET_L1
592 bool "Locate memset function in L1 Memory"
593 default y
594 help
595 If enabled, the memset function is linked
596 into L1 instruction memory. (less latency)
597
598config MEMCPY_L1
599 bool "Locate memcpy function in L1 Memory"
600 default y
601 help
602 If enabled, the memcpy function is linked
603 into L1 instruction memory. (less latency)
604
605config SYS_BFIN_SPINLOCK_L1
606 bool "Locate sys_bfin_spinlock function in L1 Memory"
607 default y
608 help
609 If enabled, sys_bfin_spinlock function is linked
610 into L1 instruction memory. (less latency)
611
612config IP_CHECKSUM_L1
613 bool "Locate IP Checksum function in L1 Memory"
614 default n
615 help
616 If enabled, the IP Checksum function is linked
617 into L1 instruction memory. (less latency)
618
619config CACHELINE_ALIGNED_L1
620 bool "Locate cacheline_aligned data to L1 Data Memory"
621 default y if !BF54x
622 default n if BF54x
623 depends on !BF531
624 help
625 If enabled, cacheline_anligned data is linked
626 into L1 data memory. (less latency)
627
628config SYSCALL_TAB_L1
629 bool "Locate Syscall Table L1 Data Memory"
630 default n
631 depends on !BF531
632 help
633 If enabled, the Syscall LUT is linked
634 into L1 data memory. (less latency)
635
636config CPLB_SWITCH_TAB_L1
637 bool "Locate CPLB Switch Tables L1 Data Memory"
638 default n
639 depends on !BF531
640 help
641 If enabled, the CPLB Switch Tables are linked
642 into L1 data memory. (less latency)
643
644endmenu
645
646
647choice
648 prompt "Kernel executes from"
649 help
650 Choose the memory type that the kernel will be running in.
651
652config RAMKERNEL
653 bool "RAM"
654 help
655 The kernel will be resident in RAM when running.
656
657config ROMKERNEL
658 bool "ROM"
659 help
660 The kernel will be resident in FLASH/ROM when running.
661
662endchoice
663
664source "mm/Kconfig"
665
666config LARGE_ALLOCS
667 bool "Allow allocating large blocks (> 1MB) of memory"
668 help
669 Allow the slab memory allocator to keep chains for very large
670 memory sizes - upto 32MB. You may need this if your system has
671 a lot of RAM, and you need to able to allocate very large
672 contiguous chunks. If unsure, say N.
673
674config BFIN_GPTIMERS
675 tristate "Enable Blackfin General Purpose Timers API"
676 default n
677 help
678 Enable support for the General Purpose Timers API. If you
679 are unsure, say N.
680
681 To compile this driver as a module, choose M here: the module
682 will be called gptimers.ko.
683
684config BFIN_DMA_5XX
685 bool "Enable DMA Support"
686 depends on (BF52x || BF53x || BF561 || BF54x)
687 default y
688 help
689 DMA driver for BF5xx.
690
691choice
692 prompt "Uncached SDRAM region"
693 default DMA_UNCACHED_1M
694 depends on BFIN_DMA_5XX
695config DMA_UNCACHED_2M
696 bool "Enable 2M DMA region"
697config DMA_UNCACHED_1M
698 bool "Enable 1M DMA region"
699config DMA_UNCACHED_NONE
700 bool "Disable DMA region"
701endchoice
702
703
704comment "Cache Support"
705config BFIN_ICACHE
706 bool "Enable ICACHE"
707config BFIN_DCACHE
708 bool "Enable DCACHE"
709config BFIN_DCACHE_BANKA
710 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
711 depends on BFIN_DCACHE && !BF531
712 default n
713config BFIN_ICACHE_LOCK
714 bool "Enable Instruction Cache Locking"
715
716choice
717 prompt "Policy"
718 depends on BFIN_DCACHE
719 default BFIN_WB
720config BFIN_WB
721 bool "Write back"
722 help
723 Write Back Policy:
724 Cached data will be written back to SDRAM only when needed.
725 This can give a nice increase in performance, but beware of
726 broken drivers that do not properly invalidate/flush their
727 cache.
728
729 Write Through Policy:
730 Cached data will always be written back to SDRAM when the
731 cache is updated. This is a completely safe setting, but
732 performance is worse than Write Back.
733
734 If you are unsure of the options and you want to be safe,
735 then go with Write Through.
736
737config BFIN_WT
738 bool "Write through"
739 help
740 Write Back Policy:
741 Cached data will be written back to SDRAM only when needed.
742 This can give a nice increase in performance, but beware of
743 broken drivers that do not properly invalidate/flush their
744 cache.
745
746 Write Through Policy:
747 Cached data will always be written back to SDRAM when the
748 cache is updated. This is a completely safe setting, but
749 performance is worse than Write Back.
750
751 If you are unsure of the options and you want to be safe,
752 then go with Write Through.
753
754endchoice
755
756config L1_MAX_PIECE
757 int "Set the max L1 SRAM pieces"
758 default 16
759 help
760 Set the max memory pieces for the L1 SRAM allocation algorithm.
761 Min value is 16. Max value is 1024.
762
763
764config MPU
765 bool "Enable the memory protection unit (EXPERIMENTAL)"
766 default n
767 help
768 Use the processor's MPU to protect applications from accessing
769 memory they do not own. This comes at a performance penalty
770 and is recommended only for debugging.
771
772comment "Asynchonous Memory Configuration"
773
774menu "EBIU_AMGCTL Global Control"
775config C_AMCKEN
776 bool "Enable CLKOUT"
777 default y
778
779config C_CDPRIO
780 bool "DMA has priority over core for ext. accesses"
781 default n
782
783config C_B0PEN
784 depends on BF561
785 bool "Bank 0 16 bit packing enable"
786 default y
787
788config C_B1PEN
789 depends on BF561
790 bool "Bank 1 16 bit packing enable"
791 default y
792
793config C_B2PEN
794 depends on BF561
795 bool "Bank 2 16 bit packing enable"
796 default y
797
798config C_B3PEN
799 depends on BF561
800 bool "Bank 3 16 bit packing enable"
801 default n
802
803choice
804 prompt"Enable Asynchonous Memory Banks"
805 default C_AMBEN_ALL
806
807config C_AMBEN
808 bool "Disable All Banks"
809
810config C_AMBEN_B0
811 bool "Enable Bank 0"
812
813config C_AMBEN_B0_B1
814 bool "Enable Bank 0 & 1"
815
816config C_AMBEN_B0_B1_B2
817 bool "Enable Bank 0 & 1 & 2"
818
819config C_AMBEN_ALL
820 bool "Enable All Banks"
821endchoice
822endmenu
823
824menu "EBIU_AMBCTL Control"
825config BANK_0
826 hex "Bank 0"
827 default 0x7BB0
828
829config BANK_1
830 hex "Bank 1"
831 default 0x7BB0
832
833config BANK_2
834 hex "Bank 2"
835 default 0x7BB0
836
837config BANK_3
838 hex "Bank 3"
839 default 0x99B3
840endmenu
841
842config EBIU_MBSCTLVAL
843 hex "EBIU Bank Select Control Register"
844 depends on BF54x
845 default 0
846
847config EBIU_MODEVAL
848 hex "Flash Memory Mode Control Register"
849 depends on BF54x
850 default 1
851
852config EBIU_FCTLVAL
853 hex "Flash Memory Bank Control Register"
854 depends on BF54x
855 default 6
856endmenu
857
858#############################################################################
859menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
860
861config PCI
862 bool "PCI support"
863 help
864 Support for PCI bus.
865
866source "drivers/pci/Kconfig"
867
868config HOTPLUG
869 bool "Support for hot-pluggable device"
870 help
871 Say Y here if you want to plug devices into your computer while
872 the system is running, and be able to use them quickly. In many
873 cases, the devices can likewise be unplugged at any time too.
874
875 One well known example of this is PCMCIA- or PC-cards, credit-card
876 size devices such as network cards, modems or hard drives which are
877 plugged into slots found on all modern laptop computers. Another
878 example, used on modern desktops as well as laptops, is USB.
879
880 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
881 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
882 Then your kernel will automatically call out to a user mode "policy
883 agent" (/sbin/hotplug) to load modules and set up software needed
884 to use devices as you hotplug them.
885
886source "drivers/pcmcia/Kconfig"
887
888source "drivers/pci/hotplug/Kconfig"
889
890endmenu
891
892menu "Executable file formats"
893
894source "fs/Kconfig.binfmt"
895
896endmenu
897
898menu "Power management options"
899source "kernel/power/Kconfig"
900
901choice
902 prompt "Select PM Wakeup Event Source"
903 default PM_WAKEUP_GPIO_BY_SIC_IWR
904 depends on PM
905 help
906 If you have a GPIO already configured as input with the corresponding PORTx_MASK
907 bit set - "Specify Wakeup Event by SIC_IWR value"
908
909config PM_WAKEUP_GPIO_BY_SIC_IWR
910 bool "Specify Wakeup Event by SIC_IWR value"
911config PM_WAKEUP_BY_GPIO
912 bool "Cause Wakeup Event by GPIO"
913config PM_WAKEUP_GPIO_API
914 bool "Configure Wakeup Event by PM GPIO API"
915
916endchoice
917
918config PM_WAKEUP_SIC_IWR
919 hex "Wakeup Events (SIC_IWR)"
920 depends on PM_WAKEUP_GPIO_BY_SIC_IWR
921 default 0x8 if (BF537 || BF536 || BF534)
922 default 0x80 if (BF533 || BF532 || BF531)
923 default 0x80 if (BF54x)
924 default 0x80 if (BF52x)
925
926config PM_WAKEUP_GPIO_NUMBER
927 int "Wakeup GPIO number"
928 range 0 47
929 depends on PM_WAKEUP_BY_GPIO
930 default 2 if BFIN537_STAMP
931
932choice
933 prompt "GPIO Polarity"
934 depends on PM_WAKEUP_BY_GPIO
935 default PM_WAKEUP_GPIO_POLAR_H
936config PM_WAKEUP_GPIO_POLAR_H
937 bool "Active High"
938config PM_WAKEUP_GPIO_POLAR_L
939 bool "Active Low"
940config PM_WAKEUP_GPIO_POLAR_EDGE_F
941 bool "Falling EDGE"
942config PM_WAKEUP_GPIO_POLAR_EDGE_R
943 bool "Rising EDGE"
944config PM_WAKEUP_GPIO_POLAR_EDGE_B
945 bool "Both EDGE"
946endchoice
947
948endmenu
949
950if (BF537 || BF533 || BF54x)
951
952menu "CPU Frequency scaling"
953
954source "drivers/cpufreq/Kconfig"
955
956config CPU_FREQ
957 bool
958 default n
959 help
960 If you want to enable this option, you should select the
961 DPMC driver from Character Devices.
962endmenu
963
964endif
965
966source "net/Kconfig"
967
968source "drivers/Kconfig"
969
970source "fs/Kconfig"
971
972source "kernel/Kconfig.instrumentation"
973
974source "arch/blackfin/Kconfig.debug"
975
976source "security/Kconfig"
977
978source "crypto/Kconfig"
979
980source "lib/Kconfig"
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