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1 | // SPDX-License-Identifier: GPL-2.0 | |
2 | /dts-v1/; | |
3 | / { | |
4 | compatible = "gnu,gdbsim"; | |
5 | #address-cells = <1>; | |
6 | #size-cells = <1>; | |
7 | interrupt-parent = <&h8intc>; | |
8 | ||
9 | chosen { | |
10 | bootargs = "earlyprintk=h8300-sim"; | |
11 | stdout-path = <&sci0>; | |
12 | }; | |
13 | aliases { | |
14 | serial0 = &sci0; | |
15 | serial1 = &sci1; | |
16 | }; | |
17 | ||
18 | xclk: oscillator { | |
19 | #clock-cells = <0>; | |
20 | compatible = "fixed-clock"; | |
21 | clock-frequency = <20000000>; | |
22 | clock-output-names = "xtal"; | |
23 | }; | |
24 | core_clk: core_clk { | |
25 | compatible = "renesas,h8300-div-clock"; | |
26 | clocks = <&xclk>; | |
27 | #clock-cells = <0>; | |
28 | reg = <0xfee01b 2>; | |
29 | renesas,width = <2>; | |
30 | }; | |
31 | fclk: fclk { | |
32 | compatible = "fixed-factor-clock"; | |
33 | clocks = <&core_clk>; | |
34 | #clock-cells = <0>; | |
35 | clock-div = <1>; | |
36 | clock-mult = <1>; | |
37 | }; | |
38 | ||
39 | memory@400000 { | |
40 | device_type = "memory"; | |
41 | reg = <0x400000 0x400000>; | |
42 | }; | |
43 | ||
44 | cpus { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <0>; | |
47 | cpu@0 { | |
48 | compatible = "renesas,h8300"; | |
49 | clock-frequency = <20000000>; | |
50 | }; | |
51 | }; | |
52 | ||
53 | h8intc: interrupt-controller@fee012 { | |
54 | compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; | |
55 | #interrupt-cells = <2>; | |
56 | interrupt-controller; | |
57 | reg = <0xfee012 7>; | |
58 | }; | |
59 | ||
60 | bsc: memory-controller@fee01e { | |
61 | compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; | |
62 | reg = <0xfee01e 8>; | |
63 | }; | |
64 | ||
65 | timer8: timer@ffff80 { | |
66 | compatible = "renesas,8bit-timer"; | |
67 | reg = <0xffff80 10>; | |
68 | interrupts = <36 0>; | |
69 | clocks = <&fclk>; | |
70 | clock-names = "fck"; | |
71 | }; | |
72 | ||
73 | timer16: timer@ffff68 { | |
74 | compatible = "renesas,16bit-timer"; | |
75 | reg = <0xffff68 8>, <0xffff60 8>; | |
76 | interrupts = <24 0>; | |
77 | renesas,channel = <0>; | |
78 | clocks = <&fclk>; | |
79 | clock-names = "fck"; | |
80 | }; | |
81 | ||
82 | sci0: serial@ffffb0 { | |
83 | compatible = "renesas,sci"; | |
84 | reg = <0xffffb0 8>; | |
85 | interrupts = <52 0>, <53 0>, <54 0>, <55 0>; | |
86 | clocks = <&fclk>; | |
87 | clock-names = "fck"; | |
88 | }; | |
89 | ||
90 | sci1: serial@ffffb8 { | |
91 | compatible = "renesas,sci"; | |
92 | reg = <0xffffb8 8>; | |
93 | interrupts = <56 0>, <57 0>, <58 0>, <59 0>; | |
94 | clocks = <&fclk>; | |
95 | clock-names = "fck"; | |
96 | }; | |
97 | }; |