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1 | #ifndef __CVMX_CONFIG_H__ | |
2 | #define __CVMX_CONFIG_H__ | |
3 | ||
4 | /************************* Config Specific Defines ************************/ | |
5 | #define CVMX_LLM_NUM_PORTS 1 | |
6 | #define CVMX_NULL_POINTER_PROTECT 1 | |
7 | #define CVMX_ENABLE_DEBUG_PRINTS 1 | |
8 | /* PKO queues per port for interface 0 (ports 0-15) */ | |
9 | #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 | |
10 | /* PKO queues per port for interface 1 (ports 16-31) */ | |
11 | #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 | |
12 | /* Limit on the number of PKO ports enabled for interface 0 */ | |
13 | #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 | |
14 | /* Limit on the number of PKO ports enabled for interface 1 */ | |
15 | #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 | |
16 | /* PKO queues per port for PCI (ports 32-35) */ | |
17 | #define CVMX_PKO_QUEUES_PER_PORT_PCI 1 | |
18 | /* PKO queues per port for Loop devices (ports 36-39) */ | |
19 | #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 | |
20 | ||
21 | /************************* FPA allocation *********************************/ | |
22 | /* Pool sizes in bytes, must be multiple of a cache line */ | |
23 | #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) | |
24 | #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) | |
25 | #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) | |
26 | #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) | |
27 | #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) | |
28 | #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) | |
29 | #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) | |
30 | #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) | |
31 | ||
32 | /* Pools in use */ | |
33 | /* Packet buffers */ | |
34 | #define CVMX_FPA_PACKET_POOL (0) | |
35 | #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE | |
36 | /* Work queue entries */ | |
37 | #define CVMX_FPA_WQE_POOL (1) | |
38 | #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE | |
39 | /* PKO queue command buffers */ | |
40 | #define CVMX_FPA_OUTPUT_BUFFER_POOL (2) | |
41 | #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE | |
42 | ||
43 | /************************* FAU allocation ********************************/ | |
44 | /* The fetch and add registers are allocated here. They are arranged | |
45 | * in order of descending size so that all alignment constraints are | |
46 | * automatically met. The enums are linked so that the following enum | |
47 | * continues allocating where the previous one left off, so the | |
48 | * numbering within each enum always starts with zero. The macros | |
49 | * take care of the address increment size, so the values entered | |
50 | * always increase by 1. FAU registers are accessed with byte | |
51 | * addresses. | |
52 | */ | |
53 | ||
54 | #define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) | |
55 | typedef enum { | |
56 | CVMX_FAU_REG_64_START = 0, | |
57 | CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), | |
58 | } cvmx_fau_reg_64_t; | |
59 | ||
60 | #define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) | |
61 | typedef enum { | |
62 | CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, | |
63 | CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), | |
64 | } cvmx_fau_reg_32_t; | |
65 | ||
66 | #define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) | |
67 | typedef enum { | |
68 | CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, | |
69 | CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), | |
70 | } cvmx_fau_reg_16_t; | |
71 | ||
72 | #define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) | |
73 | typedef enum { | |
74 | CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, | |
75 | CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), | |
76 | } cvmx_fau_reg_8_t; | |
77 | ||
78 | /* | |
79 | * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first | |
80 | * available FAU address that is not allocated in cvmx-config.h. This | |
81 | * is 64 bit aligned. | |
82 | */ | |
83 | #define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) | |
84 | #define CVMX_FAU_REG_END (2048) | |
85 | ||
86 | /********************** scratch memory allocation *************************/ | |
87 | /* Scratchpad memory allocation. Note that these are byte memory | |
88 | * addresses. Some uses of scratchpad (IOBDMA for example) require | |
89 | * the use of 8-byte aligned addresses, so proper alignment needs to | |
90 | * be taken into account. | |
91 | */ | |
92 | /* Generic scratch iobdma area */ | |
93 | #define CVMX_SCR_SCRATCH (0) | |
94 | /* First location available after cvmx-config.h allocated region. */ | |
95 | #define CVMX_SCR_REG_AVAIL_BASE (8) | |
96 | ||
97 | /* | |
98 | * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve | |
99 | * before the beginning of the packet. If necessary, override the | |
100 | * default here. See the IPD section of the hardware manual for MBUFF | |
101 | * SKIP details. | |
102 | */ | |
103 | #define CVMX_HELPER_FIRST_MBUFF_SKIP 184 | |
104 | ||
105 | /* | |
106 | * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve | |
107 | * in each chained packet element. If necessary, override the default | |
108 | * here. | |
109 | */ | |
110 | #define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 | |
111 | ||
112 | /* | |
113 | * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is | |
114 | * enabled for all input ports. This controls if IPD sends | |
115 | * backpressure to all ports if Octeon's FPA pools don't have enough | |
116 | * packet or work queue entries. Even when this is off, it is still | |
117 | * possible to get backpressure from individual hardware ports. When | |
118 | * configuring backpressure, also check | |
119 | * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override | |
120 | * the default here. | |
121 | */ | |
122 | #define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 | |
123 | ||
124 | /* | |
125 | * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper | |
126 | * function. Once it is enabled the hardware starts accepting | |
127 | * packets. You might want to skip the IPD enable if configuration | |
128 | * changes are need from the default helper setup. If necessary, | |
129 | * override the default here. | |
130 | */ | |
131 | #define CVMX_HELPER_ENABLE_IPD 0 | |
132 | ||
133 | /* | |
134 | * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns | |
135 | * to incoming packets. | |
136 | */ | |
137 | #define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED | |
138 | ||
139 | #define CVMX_ENABLE_PARAMETER_CHECKING 0 | |
140 | ||
141 | /* | |
142 | * The following select which fields are used by the PIP to generate | |
143 | * the tag on INPUT | |
144 | * 0: don't include | |
145 | * 1: include | |
146 | */ | |
147 | #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 | |
148 | #define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 | |
149 | #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 | |
150 | #define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 | |
151 | #define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 | |
152 | #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 | |
153 | #define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 | |
154 | #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 | |
155 | #define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 | |
156 | #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 | |
157 | #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 | |
158 | ||
159 | /* Select skip mode for input ports */ | |
160 | #define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 | |
161 | ||
162 | /* | |
163 | * Force backpressure to be disabled. This overrides all other | |
164 | * backpressure configuration. | |
165 | */ | |
166 | #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 | |
167 | ||
168 | #endif /* __CVMX_CONFIG_H__ */ |