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1 | // SPDX-License-Identifier: GPL-2.0-or-later | |
2 | /* | |
3 | * Processor capabilities determination functions. | |
4 | * | |
5 | * Copyright (C) xxxx the Anonymous | |
6 | * Copyright (C) 1994 - 2006 Ralf Baechle | |
7 | * Copyright (C) 2003, 2004 Maciej W. Rozycki | |
8 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. | |
9 | */ | |
10 | #include <linux/init.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/smp.h> | |
14 | #include <linux/stddef.h> | |
15 | #include <linux/export.h> | |
16 | ||
17 | #include <asm/bugs.h> | |
18 | #include <asm/cpu.h> | |
19 | #include <asm/cpu-features.h> | |
20 | #include <asm/cpu-type.h> | |
21 | #include <asm/fpu.h> | |
22 | #include <asm/mipsregs.h> | |
23 | #include <asm/mipsmtregs.h> | |
24 | #include <asm/msa.h> | |
25 | #include <asm/watch.h> | |
26 | #include <asm/elf.h> | |
27 | #include <asm/pgtable-bits.h> | |
28 | #include <asm/spram.h> | |
29 | #include <linux/uaccess.h> | |
30 | ||
31 | /* Hardware capabilities */ | |
32 | unsigned int elf_hwcap __read_mostly; | |
33 | EXPORT_SYMBOL_GPL(elf_hwcap); | |
34 | ||
35 | #ifdef CONFIG_MIPS_FP_SUPPORT | |
36 | ||
37 | /* | |
38 | * Get the FPU Implementation/Revision. | |
39 | */ | |
40 | static inline unsigned long cpu_get_fpu_id(void) | |
41 | { | |
42 | unsigned long tmp, fpu_id; | |
43 | ||
44 | tmp = read_c0_status(); | |
45 | __enable_fpu(FPU_AS_IS); | |
46 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
47 | write_c0_status(tmp); | |
48 | return fpu_id; | |
49 | } | |
50 | ||
51 | /* | |
52 | * Check if the CPU has an external FPU. | |
53 | */ | |
54 | static inline int __cpu_has_fpu(void) | |
55 | { | |
56 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; | |
57 | } | |
58 | ||
59 | /* | |
60 | * Determine the FCSR mask for FPU hardware. | |
61 | */ | |
62 | static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) | |
63 | { | |
64 | unsigned long sr, mask, fcsr, fcsr0, fcsr1; | |
65 | ||
66 | fcsr = c->fpu_csr31; | |
67 | mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; | |
68 | ||
69 | sr = read_c0_status(); | |
70 | __enable_fpu(FPU_AS_IS); | |
71 | ||
72 | fcsr0 = fcsr & mask; | |
73 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
74 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
75 | ||
76 | fcsr1 = fcsr | ~mask; | |
77 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
78 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
79 | ||
80 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
81 | ||
82 | write_c0_status(sr); | |
83 | ||
84 | c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; | |
85 | } | |
86 | ||
87 | /* | |
88 | * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes | |
89 | * supported by FPU hardware. | |
90 | */ | |
91 | static void cpu_set_fpu_2008(struct cpuinfo_mips *c) | |
92 | { | |
93 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
94 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
95 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
96 | unsigned long sr, fir, fcsr, fcsr0, fcsr1; | |
97 | ||
98 | sr = read_c0_status(); | |
99 | __enable_fpu(FPU_AS_IS); | |
100 | ||
101 | fir = read_32bit_cp1_register(CP1_REVISION); | |
102 | if (fir & MIPS_FPIR_HAS2008) { | |
103 | fcsr = read_32bit_cp1_register(CP1_STATUS); | |
104 | ||
105 | fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); | |
106 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
107 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
108 | ||
109 | fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
110 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
111 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
112 | ||
113 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
114 | ||
115 | if (!(fcsr0 & FPU_CSR_NAN2008)) | |
116 | c->options |= MIPS_CPU_NAN_LEGACY; | |
117 | if (fcsr1 & FPU_CSR_NAN2008) | |
118 | c->options |= MIPS_CPU_NAN_2008; | |
119 | ||
120 | if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) | |
121 | c->fpu_msk31 &= ~FPU_CSR_ABS2008; | |
122 | else | |
123 | c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; | |
124 | ||
125 | if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) | |
126 | c->fpu_msk31 &= ~FPU_CSR_NAN2008; | |
127 | else | |
128 | c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; | |
129 | } else { | |
130 | c->options |= MIPS_CPU_NAN_LEGACY; | |
131 | } | |
132 | ||
133 | write_c0_status(sr); | |
134 | } else { | |
135 | c->options |= MIPS_CPU_NAN_LEGACY; | |
136 | } | |
137 | } | |
138 | ||
139 | /* | |
140 | * IEEE 754 conformance mode to use. Affects the NaN encoding and the | |
141 | * ABS.fmt/NEG.fmt execution mode. | |
142 | */ | |
143 | static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; | |
144 | ||
145 | /* | |
146 | * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes | |
147 | * to support by the FPU emulator according to the IEEE 754 conformance | |
148 | * mode selected. Note that "relaxed" straps the emulator so that it | |
149 | * allows 2008-NaN binaries even for legacy processors. | |
150 | */ | |
151 | static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) | |
152 | { | |
153 | c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); | |
154 | c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); | |
155 | c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); | |
156 | ||
157 | switch (ieee754) { | |
158 | case STRICT: | |
159 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
160 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
161 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
162 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; | |
163 | } else { | |
164 | c->options |= MIPS_CPU_NAN_LEGACY; | |
165 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
166 | } | |
167 | break; | |
168 | case LEGACY: | |
169 | c->options |= MIPS_CPU_NAN_LEGACY; | |
170 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
171 | break; | |
172 | case STD2008: | |
173 | c->options |= MIPS_CPU_NAN_2008; | |
174 | c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
175 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
176 | break; | |
177 | case RELAXED: | |
178 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; | |
179 | break; | |
180 | } | |
181 | } | |
182 | ||
183 | /* | |
184 | * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode | |
185 | * according to the "ieee754=" parameter. | |
186 | */ | |
187 | static void cpu_set_nan_2008(struct cpuinfo_mips *c) | |
188 | { | |
189 | switch (ieee754) { | |
190 | case STRICT: | |
191 | mips_use_nan_legacy = !!cpu_has_nan_legacy; | |
192 | mips_use_nan_2008 = !!cpu_has_nan_2008; | |
193 | break; | |
194 | case LEGACY: | |
195 | mips_use_nan_legacy = !!cpu_has_nan_legacy; | |
196 | mips_use_nan_2008 = !cpu_has_nan_legacy; | |
197 | break; | |
198 | case STD2008: | |
199 | mips_use_nan_legacy = !cpu_has_nan_2008; | |
200 | mips_use_nan_2008 = !!cpu_has_nan_2008; | |
201 | break; | |
202 | case RELAXED: | |
203 | mips_use_nan_legacy = true; | |
204 | mips_use_nan_2008 = true; | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
209 | /* | |
210 | * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override | |
211 | * settings: | |
212 | * | |
213 | * strict: accept binaries that request a NaN encoding supported by the FPU | |
214 | * legacy: only accept legacy-NaN binaries | |
215 | * 2008: only accept 2008-NaN binaries | |
216 | * relaxed: accept any binaries regardless of whether supported by the FPU | |
217 | */ | |
218 | static int __init ieee754_setup(char *s) | |
219 | { | |
220 | if (!s) | |
221 | return -1; | |
222 | else if (!strcmp(s, "strict")) | |
223 | ieee754 = STRICT; | |
224 | else if (!strcmp(s, "legacy")) | |
225 | ieee754 = LEGACY; | |
226 | else if (!strcmp(s, "2008")) | |
227 | ieee754 = STD2008; | |
228 | else if (!strcmp(s, "relaxed")) | |
229 | ieee754 = RELAXED; | |
230 | else | |
231 | return -1; | |
232 | ||
233 | if (!(boot_cpu_data.options & MIPS_CPU_FPU)) | |
234 | cpu_set_nofpu_2008(&boot_cpu_data); | |
235 | cpu_set_nan_2008(&boot_cpu_data); | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | early_param("ieee754", ieee754_setup); | |
241 | ||
242 | /* | |
243 | * Set the FIR feature flags for the FPU emulator. | |
244 | */ | |
245 | static void cpu_set_nofpu_id(struct cpuinfo_mips *c) | |
246 | { | |
247 | u32 value; | |
248 | ||
249 | value = 0; | |
250 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
251 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
252 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
253 | value |= MIPS_FPIR_D | MIPS_FPIR_S; | |
254 | if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
255 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
256 | value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; | |
257 | if (c->options & MIPS_CPU_NAN_2008) | |
258 | value |= MIPS_FPIR_HAS2008; | |
259 | c->fpu_id = value; | |
260 | } | |
261 | ||
262 | /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ | |
263 | static unsigned int mips_nofpu_msk31; | |
264 | ||
265 | /* | |
266 | * Set options for FPU hardware. | |
267 | */ | |
268 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) | |
269 | { | |
270 | c->fpu_id = cpu_get_fpu_id(); | |
271 | mips_nofpu_msk31 = c->fpu_msk31; | |
272 | ||
273 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
274 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
275 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
276 | if (c->fpu_id & MIPS_FPIR_3D) | |
277 | c->ases |= MIPS_ASE_MIPS3D; | |
278 | if (c->fpu_id & MIPS_FPIR_UFRP) | |
279 | c->options |= MIPS_CPU_UFR; | |
280 | if (c->fpu_id & MIPS_FPIR_FREP) | |
281 | c->options |= MIPS_CPU_FRE; | |
282 | } | |
283 | ||
284 | cpu_set_fpu_fcsr_mask(c); | |
285 | cpu_set_fpu_2008(c); | |
286 | cpu_set_nan_2008(c); | |
287 | } | |
288 | ||
289 | /* | |
290 | * Set options for the FPU emulator. | |
291 | */ | |
292 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) | |
293 | { | |
294 | c->options &= ~MIPS_CPU_FPU; | |
295 | c->fpu_msk31 = mips_nofpu_msk31; | |
296 | ||
297 | cpu_set_nofpu_2008(c); | |
298 | cpu_set_nan_2008(c); | |
299 | cpu_set_nofpu_id(c); | |
300 | } | |
301 | ||
302 | static int mips_fpu_disabled; | |
303 | ||
304 | static int __init fpu_disable(char *s) | |
305 | { | |
306 | cpu_set_nofpu_opts(&boot_cpu_data); | |
307 | mips_fpu_disabled = 1; | |
308 | ||
309 | return 1; | |
310 | } | |
311 | ||
312 | __setup("nofpu", fpu_disable); | |
313 | ||
314 | #else /* !CONFIG_MIPS_FP_SUPPORT */ | |
315 | ||
316 | #define mips_fpu_disabled 1 | |
317 | ||
318 | static inline unsigned long cpu_get_fpu_id(void) | |
319 | { | |
320 | return FPIR_IMP_NONE; | |
321 | } | |
322 | ||
323 | static inline int __cpu_has_fpu(void) | |
324 | { | |
325 | return 0; | |
326 | } | |
327 | ||
328 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) | |
329 | { | |
330 | /* no-op */ | |
331 | } | |
332 | ||
333 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) | |
334 | { | |
335 | /* no-op */ | |
336 | } | |
337 | ||
338 | #endif /* CONFIG_MIPS_FP_SUPPORT */ | |
339 | ||
340 | static inline unsigned long cpu_get_msa_id(void) | |
341 | { | |
342 | unsigned long status, msa_id; | |
343 | ||
344 | status = read_c0_status(); | |
345 | __enable_fpu(FPU_64BIT); | |
346 | enable_msa(); | |
347 | msa_id = read_msa_ir(); | |
348 | disable_msa(); | |
349 | write_c0_status(status); | |
350 | return msa_id; | |
351 | } | |
352 | ||
353 | static int mips_dsp_disabled; | |
354 | ||
355 | static int __init dsp_disable(char *s) | |
356 | { | |
357 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); | |
358 | mips_dsp_disabled = 1; | |
359 | ||
360 | return 1; | |
361 | } | |
362 | ||
363 | __setup("nodsp", dsp_disable); | |
364 | ||
365 | static int mips_htw_disabled; | |
366 | ||
367 | static int __init htw_disable(char *s) | |
368 | { | |
369 | mips_htw_disabled = 1; | |
370 | cpu_data[0].options &= ~MIPS_CPU_HTW; | |
371 | write_c0_pwctl(read_c0_pwctl() & | |
372 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
373 | ||
374 | return 1; | |
375 | } | |
376 | ||
377 | __setup("nohtw", htw_disable); | |
378 | ||
379 | static int mips_ftlb_disabled; | |
380 | static int mips_has_ftlb_configured; | |
381 | ||
382 | enum ftlb_flags { | |
383 | FTLB_EN = 1 << 0, | |
384 | FTLB_SET_PROB = 1 << 1, | |
385 | }; | |
386 | ||
387 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); | |
388 | ||
389 | static int __init ftlb_disable(char *s) | |
390 | { | |
391 | unsigned int config4, mmuextdef; | |
392 | ||
393 | /* | |
394 | * If the core hasn't done any FTLB configuration, there is nothing | |
395 | * for us to do here. | |
396 | */ | |
397 | if (!mips_has_ftlb_configured) | |
398 | return 1; | |
399 | ||
400 | /* Disable it in the boot cpu */ | |
401 | if (set_ftlb_enable(&cpu_data[0], 0)) { | |
402 | pr_warn("Can't turn FTLB off\n"); | |
403 | return 1; | |
404 | } | |
405 | ||
406 | config4 = read_c0_config4(); | |
407 | ||
408 | /* Check that FTLB has been disabled */ | |
409 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
410 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ | |
411 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { | |
412 | /* This should never happen */ | |
413 | pr_warn("FTLB could not be disabled!\n"); | |
414 | return 1; | |
415 | } | |
416 | ||
417 | mips_ftlb_disabled = 1; | |
418 | mips_has_ftlb_configured = 0; | |
419 | ||
420 | /* | |
421 | * noftlb is mainly used for debug purposes so print | |
422 | * an informative message instead of using pr_debug() | |
423 | */ | |
424 | pr_info("FTLB has been disabled\n"); | |
425 | ||
426 | /* | |
427 | * Some of these bits are duplicated in the decode_config4. | |
428 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case | |
429 | * once FTLB has been disabled so undo what decode_config4 did. | |
430 | */ | |
431 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * | |
432 | cpu_data[0].tlbsizeftlbsets; | |
433 | cpu_data[0].tlbsizeftlbsets = 0; | |
434 | cpu_data[0].tlbsizeftlbways = 0; | |
435 | ||
436 | return 1; | |
437 | } | |
438 | ||
439 | __setup("noftlb", ftlb_disable); | |
440 | ||
441 | /* | |
442 | * Check if the CPU has per tc perf counters | |
443 | */ | |
444 | static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) | |
445 | { | |
446 | if (read_c0_config7() & MTI_CONF7_PTC) | |
447 | c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; | |
448 | } | |
449 | ||
450 | static inline void check_errata(void) | |
451 | { | |
452 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
453 | ||
454 | switch (current_cpu_type()) { | |
455 | case CPU_34K: | |
456 | /* | |
457 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
458 | * This code only handles VPE0, any SMP/RTOS code | |
459 | * making use of VPE1 will be responsable for that VPE. | |
460 | */ | |
461 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
462 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
463 | break; | |
464 | default: | |
465 | break; | |
466 | } | |
467 | } | |
468 | ||
469 | void __init check_bugs32(void) | |
470 | { | |
471 | check_errata(); | |
472 | } | |
473 | ||
474 | /* | |
475 | * Probe whether cpu has config register by trying to play with | |
476 | * alternate cache bit and see whether it matters. | |
477 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
478 | */ | |
479 | static inline int cpu_has_confreg(void) | |
480 | { | |
481 | #ifdef CONFIG_CPU_R3000 | |
482 | extern unsigned long r3k_cache_size(unsigned long); | |
483 | unsigned long size1, size2; | |
484 | unsigned long cfg = read_c0_conf(); | |
485 | ||
486 | size1 = r3k_cache_size(ST0_ISC); | |
487 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
488 | size2 = r3k_cache_size(ST0_ISC); | |
489 | write_c0_conf(cfg); | |
490 | return size1 != size2; | |
491 | #else | |
492 | return 0; | |
493 | #endif | |
494 | } | |
495 | ||
496 | static inline void set_elf_platform(int cpu, const char *plat) | |
497 | { | |
498 | if (cpu == 0) | |
499 | __elf_platform = plat; | |
500 | } | |
501 | ||
502 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) | |
503 | { | |
504 | #ifdef __NEED_VMBITS_PROBE | |
505 | write_c0_entryhi(0x3fffffffffffe000ULL); | |
506 | back_to_back_c0_hazard(); | |
507 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); | |
508 | #endif | |
509 | } | |
510 | ||
511 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) | |
512 | { | |
513 | switch (isa) { | |
514 | case MIPS_CPU_ISA_M64R2: | |
515 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
516 | /* fall through */ | |
517 | case MIPS_CPU_ISA_M64R1: | |
518 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
519 | /* fall through */ | |
520 | case MIPS_CPU_ISA_V: | |
521 | c->isa_level |= MIPS_CPU_ISA_V; | |
522 | /* fall through */ | |
523 | case MIPS_CPU_ISA_IV: | |
524 | c->isa_level |= MIPS_CPU_ISA_IV; | |
525 | /* fall through */ | |
526 | case MIPS_CPU_ISA_III: | |
527 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; | |
528 | break; | |
529 | ||
530 | /* R6 incompatible with everything else */ | |
531 | case MIPS_CPU_ISA_M64R6: | |
532 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; | |
533 | /* fall through */ | |
534 | case MIPS_CPU_ISA_M32R6: | |
535 | c->isa_level |= MIPS_CPU_ISA_M32R6; | |
536 | /* Break here so we don't add incompatible ISAs */ | |
537 | break; | |
538 | case MIPS_CPU_ISA_M32R2: | |
539 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
540 | /* fall through */ | |
541 | case MIPS_CPU_ISA_M32R1: | |
542 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
543 | /* fall through */ | |
544 | case MIPS_CPU_ISA_II: | |
545 | c->isa_level |= MIPS_CPU_ISA_II; | |
546 | break; | |
547 | } | |
548 | } | |
549 | ||
550 | static char unknown_isa[] = KERN_ERR \ | |
551 | "Unsupported ISA type, c0.config0: %d."; | |
552 | ||
553 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) | |
554 | { | |
555 | ||
556 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | |
557 | ||
558 | /* | |
559 | * 0 = All TLBWR instructions go to FTLB | |
560 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | |
561 | * FTLB and 1 goes to the VTLB. | |
562 | * 2 = 7:1: As above with 7:1 ratio. | |
563 | * 3 = 3:1: As above with 3:1 ratio. | |
564 | * | |
565 | * Use the linear midpoint as the probability threshold. | |
566 | */ | |
567 | if (probability >= 12) | |
568 | return 1; | |
569 | else if (probability >= 6) | |
570 | return 2; | |
571 | else | |
572 | /* | |
573 | * So FTLB is less than 4 times bigger than VTLB. | |
574 | * A 3:1 ratio can still be useful though. | |
575 | */ | |
576 | return 3; | |
577 | } | |
578 | ||
579 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) | |
580 | { | |
581 | unsigned int config; | |
582 | ||
583 | /* It's implementation dependent how the FTLB can be enabled */ | |
584 | switch (c->cputype) { | |
585 | case CPU_PROAPTIV: | |
586 | case CPU_P5600: | |
587 | case CPU_P6600: | |
588 | /* proAptiv & related cores use Config6 to enable the FTLB */ | |
589 | config = read_c0_config6(); | |
590 | ||
591 | if (flags & FTLB_EN) | |
592 | config |= MIPS_CONF6_FTLBEN; | |
593 | else | |
594 | config &= ~MIPS_CONF6_FTLBEN; | |
595 | ||
596 | if (flags & FTLB_SET_PROB) { | |
597 | config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); | |
598 | config |= calculate_ftlb_probability(c) | |
599 | << MIPS_CONF6_FTLBP_SHIFT; | |
600 | } | |
601 | ||
602 | write_c0_config6(config); | |
603 | back_to_back_c0_hazard(); | |
604 | break; | |
605 | case CPU_I6400: | |
606 | case CPU_I6500: | |
607 | /* There's no way to disable the FTLB */ | |
608 | if (!(flags & FTLB_EN)) | |
609 | return 1; | |
610 | return 0; | |
611 | case CPU_LOONGSON3: | |
612 | /* Flush ITLB, DTLB, VTLB and FTLB */ | |
613 | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | | |
614 | LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); | |
615 | /* Loongson-3 cores use Config6 to enable the FTLB */ | |
616 | config = read_c0_config6(); | |
617 | if (flags & FTLB_EN) | |
618 | /* Enable FTLB */ | |
619 | write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); | |
620 | else | |
621 | /* Disable FTLB */ | |
622 | write_c0_config6(config | MIPS_CONF6_FTLBDIS); | |
623 | break; | |
624 | default: | |
625 | return 1; | |
626 | } | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) | |
632 | { | |
633 | unsigned int config0; | |
634 | int isa, mt; | |
635 | ||
636 | config0 = read_c0_config(); | |
637 | ||
638 | /* | |
639 | * Look for Standard TLB or Dual VTLB and FTLB | |
640 | */ | |
641 | mt = config0 & MIPS_CONF_MT; | |
642 | if (mt == MIPS_CONF_MT_TLB) | |
643 | c->options |= MIPS_CPU_TLB; | |
644 | else if (mt == MIPS_CONF_MT_FTLB) | |
645 | c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; | |
646 | ||
647 | isa = (config0 & MIPS_CONF_AT) >> 13; | |
648 | switch (isa) { | |
649 | case 0: | |
650 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
651 | case 0: | |
652 | set_isa(c, MIPS_CPU_ISA_M32R1); | |
653 | break; | |
654 | case 1: | |
655 | set_isa(c, MIPS_CPU_ISA_M32R2); | |
656 | break; | |
657 | case 2: | |
658 | set_isa(c, MIPS_CPU_ISA_M32R6); | |
659 | break; | |
660 | default: | |
661 | goto unknown; | |
662 | } | |
663 | break; | |
664 | case 2: | |
665 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
666 | case 0: | |
667 | set_isa(c, MIPS_CPU_ISA_M64R1); | |
668 | break; | |
669 | case 1: | |
670 | set_isa(c, MIPS_CPU_ISA_M64R2); | |
671 | break; | |
672 | case 2: | |
673 | set_isa(c, MIPS_CPU_ISA_M64R6); | |
674 | break; | |
675 | default: | |
676 | goto unknown; | |
677 | } | |
678 | break; | |
679 | default: | |
680 | goto unknown; | |
681 | } | |
682 | ||
683 | return config0 & MIPS_CONF_M; | |
684 | ||
685 | unknown: | |
686 | panic(unknown_isa, config0); | |
687 | } | |
688 | ||
689 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
690 | { | |
691 | unsigned int config1; | |
692 | ||
693 | config1 = read_c0_config1(); | |
694 | ||
695 | if (config1 & MIPS_CONF1_MD) | |
696 | c->ases |= MIPS_ASE_MDMX; | |
697 | if (config1 & MIPS_CONF1_PC) | |
698 | c->options |= MIPS_CPU_PERF; | |
699 | if (config1 & MIPS_CONF1_WR) | |
700 | c->options |= MIPS_CPU_WATCH; | |
701 | if (config1 & MIPS_CONF1_CA) | |
702 | c->ases |= MIPS_ASE_MIPS16; | |
703 | if (config1 & MIPS_CONF1_EP) | |
704 | c->options |= MIPS_CPU_EJTAG; | |
705 | if (config1 & MIPS_CONF1_FP) { | |
706 | c->options |= MIPS_CPU_FPU; | |
707 | c->options |= MIPS_CPU_32FPR; | |
708 | } | |
709 | if (cpu_has_tlb) { | |
710 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
711 | c->tlbsizevtlb = c->tlbsize; | |
712 | c->tlbsizeftlbsets = 0; | |
713 | } | |
714 | ||
715 | return config1 & MIPS_CONF_M; | |
716 | } | |
717 | ||
718 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
719 | { | |
720 | unsigned int config2; | |
721 | ||
722 | config2 = read_c0_config2(); | |
723 | ||
724 | if (config2 & MIPS_CONF2_SL) | |
725 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
726 | ||
727 | return config2 & MIPS_CONF_M; | |
728 | } | |
729 | ||
730 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
731 | { | |
732 | unsigned int config3; | |
733 | ||
734 | config3 = read_c0_config3(); | |
735 | ||
736 | if (config3 & MIPS_CONF3_SM) { | |
737 | c->ases |= MIPS_ASE_SMARTMIPS; | |
738 | c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; | |
739 | } | |
740 | if (config3 & MIPS_CONF3_RXI) | |
741 | c->options |= MIPS_CPU_RIXI; | |
742 | if (config3 & MIPS_CONF3_CTXTC) | |
743 | c->options |= MIPS_CPU_CTXTC; | |
744 | if (config3 & MIPS_CONF3_DSP) | |
745 | c->ases |= MIPS_ASE_DSP; | |
746 | if (config3 & MIPS_CONF3_DSP2P) { | |
747 | c->ases |= MIPS_ASE_DSP2P; | |
748 | if (cpu_has_mips_r6) | |
749 | c->ases |= MIPS_ASE_DSP3; | |
750 | } | |
751 | if (config3 & MIPS_CONF3_VINT) | |
752 | c->options |= MIPS_CPU_VINT; | |
753 | if (config3 & MIPS_CONF3_VEIC) | |
754 | c->options |= MIPS_CPU_VEIC; | |
755 | if (config3 & MIPS_CONF3_LPA) | |
756 | c->options |= MIPS_CPU_LPA; | |
757 | if (config3 & MIPS_CONF3_MT) | |
758 | c->ases |= MIPS_ASE_MIPSMT; | |
759 | if (config3 & MIPS_CONF3_ULRI) | |
760 | c->options |= MIPS_CPU_ULRI; | |
761 | if (config3 & MIPS_CONF3_ISA) | |
762 | c->options |= MIPS_CPU_MICROMIPS; | |
763 | if (config3 & MIPS_CONF3_VZ) | |
764 | c->ases |= MIPS_ASE_VZ; | |
765 | if (config3 & MIPS_CONF3_SC) | |
766 | c->options |= MIPS_CPU_SEGMENTS; | |
767 | if (config3 & MIPS_CONF3_BI) | |
768 | c->options |= MIPS_CPU_BADINSTR; | |
769 | if (config3 & MIPS_CONF3_BP) | |
770 | c->options |= MIPS_CPU_BADINSTRP; | |
771 | if (config3 & MIPS_CONF3_MSA) | |
772 | c->ases |= MIPS_ASE_MSA; | |
773 | if (config3 & MIPS_CONF3_PW) { | |
774 | c->htw_seq = 0; | |
775 | c->options |= MIPS_CPU_HTW; | |
776 | } | |
777 | if (config3 & MIPS_CONF3_CDMM) | |
778 | c->options |= MIPS_CPU_CDMM; | |
779 | if (config3 & MIPS_CONF3_SP) | |
780 | c->options |= MIPS_CPU_SP; | |
781 | ||
782 | return config3 & MIPS_CONF_M; | |
783 | } | |
784 | ||
785 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
786 | { | |
787 | unsigned int config4; | |
788 | unsigned int newcf4; | |
789 | unsigned int mmuextdef; | |
790 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; | |
791 | unsigned long asid_mask; | |
792 | ||
793 | config4 = read_c0_config4(); | |
794 | ||
795 | if (cpu_has_tlb) { | |
796 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) | |
797 | c->options |= MIPS_CPU_TLBINV; | |
798 | ||
799 | /* | |
800 | * R6 has dropped the MMUExtDef field from config4. | |
801 | * On R6 the fields always describe the FTLB, and only if it is | |
802 | * present according to Config.MT. | |
803 | */ | |
804 | if (!cpu_has_mips_r6) | |
805 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
806 | else if (cpu_has_ftlb) | |
807 | mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; | |
808 | else | |
809 | mmuextdef = 0; | |
810 | ||
811 | switch (mmuextdef) { | |
812 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: | |
813 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
814 | c->tlbsizevtlb = c->tlbsize; | |
815 | break; | |
816 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: | |
817 | c->tlbsizevtlb += | |
818 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> | |
819 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; | |
820 | c->tlbsize = c->tlbsizevtlb; | |
821 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; | |
822 | /* fall through */ | |
823 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: | |
824 | if (mips_ftlb_disabled) | |
825 | break; | |
826 | newcf4 = (config4 & ~ftlb_page) | | |
827 | (page_size_ftlb(mmuextdef) << | |
828 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); | |
829 | write_c0_config4(newcf4); | |
830 | back_to_back_c0_hazard(); | |
831 | config4 = read_c0_config4(); | |
832 | if (config4 != newcf4) { | |
833 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", | |
834 | PAGE_SIZE, config4); | |
835 | /* Switch FTLB off */ | |
836 | set_ftlb_enable(c, 0); | |
837 | mips_ftlb_disabled = 1; | |
838 | break; | |
839 | } | |
840 | c->tlbsizeftlbsets = 1 << | |
841 | ((config4 & MIPS_CONF4_FTLBSETS) >> | |
842 | MIPS_CONF4_FTLBSETS_SHIFT); | |
843 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> | |
844 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; | |
845 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; | |
846 | mips_has_ftlb_configured = 1; | |
847 | break; | |
848 | } | |
849 | } | |
850 | ||
851 | c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) | |
852 | >> MIPS_CONF4_KSCREXIST_SHIFT; | |
853 | ||
854 | asid_mask = MIPS_ENTRYHI_ASID; | |
855 | if (config4 & MIPS_CONF4_AE) | |
856 | asid_mask |= MIPS_ENTRYHI_ASIDX; | |
857 | set_cpu_asid_mask(c, asid_mask); | |
858 | ||
859 | /* | |
860 | * Warn if the computed ASID mask doesn't match the mask the kernel | |
861 | * is built for. This may indicate either a serious problem or an | |
862 | * easy optimisation opportunity, but either way should be addressed. | |
863 | */ | |
864 | WARN_ON(asid_mask != cpu_asid_mask(c)); | |
865 | ||
866 | return config4 & MIPS_CONF_M; | |
867 | } | |
868 | ||
869 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) | |
870 | { | |
871 | unsigned int config5, max_mmid_width; | |
872 | unsigned long asid_mask; | |
873 | ||
874 | config5 = read_c0_config5(); | |
875 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); | |
876 | ||
877 | if (cpu_has_mips_r6) { | |
878 | if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid) | |
879 | config5 |= MIPS_CONF5_MI; | |
880 | else | |
881 | config5 &= ~MIPS_CONF5_MI; | |
882 | } | |
883 | ||
884 | write_c0_config5(config5); | |
885 | ||
886 | if (config5 & MIPS_CONF5_EVA) | |
887 | c->options |= MIPS_CPU_EVA; | |
888 | if (config5 & MIPS_CONF5_MRP) | |
889 | c->options |= MIPS_CPU_MAAR; | |
890 | if (config5 & MIPS_CONF5_LLB) | |
891 | c->options |= MIPS_CPU_RW_LLB; | |
892 | if (config5 & MIPS_CONF5_MVH) | |
893 | c->options |= MIPS_CPU_MVH; | |
894 | if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) | |
895 | c->options |= MIPS_CPU_VP; | |
896 | if (config5 & MIPS_CONF5_CA2) | |
897 | c->ases |= MIPS_ASE_MIPS16E2; | |
898 | ||
899 | if (config5 & MIPS_CONF5_CRCP) | |
900 | elf_hwcap |= HWCAP_MIPS_CRC32; | |
901 | ||
902 | if (cpu_has_mips_r6) { | |
903 | /* Ensure the write to config5 above takes effect */ | |
904 | back_to_back_c0_hazard(); | |
905 | ||
906 | /* Check whether we successfully enabled MMID support */ | |
907 | config5 = read_c0_config5(); | |
908 | if (config5 & MIPS_CONF5_MI) | |
909 | c->options |= MIPS_CPU_MMID; | |
910 | ||
911 | /* | |
912 | * Warn if we've hardcoded cpu_has_mmid to a value unsuitable | |
913 | * for the CPU we're running on, or if CPUs in an SMP system | |
914 | * have inconsistent MMID support. | |
915 | */ | |
916 | WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); | |
917 | ||
918 | if (cpu_has_mmid) { | |
919 | write_c0_memorymapid(~0ul); | |
920 | back_to_back_c0_hazard(); | |
921 | asid_mask = read_c0_memorymapid(); | |
922 | ||
923 | /* | |
924 | * We maintain a bitmap to track MMID allocation, and | |
925 | * need a sensible upper bound on the size of that | |
926 | * bitmap. The initial CPU with MMID support (I6500) | |
927 | * supports 16 bit MMIDs, which gives us an 8KiB | |
928 | * bitmap. The architecture recommends that hardware | |
929 | * support 32 bit MMIDs, which would give us a 512MiB | |
930 | * bitmap - that's too big in most cases. | |
931 | * | |
932 | * Cap MMID width at 16 bits for now & we can revisit | |
933 | * this if & when hardware supports anything wider. | |
934 | */ | |
935 | max_mmid_width = 16; | |
936 | if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { | |
937 | pr_info("Capping MMID width at %d bits", | |
938 | max_mmid_width); | |
939 | asid_mask = GENMASK(max_mmid_width - 1, 0); | |
940 | } | |
941 | ||
942 | set_cpu_asid_mask(c, asid_mask); | |
943 | } | |
944 | } | |
945 | ||
946 | return config5 & MIPS_CONF_M; | |
947 | } | |
948 | ||
949 | static void decode_configs(struct cpuinfo_mips *c) | |
950 | { | |
951 | int ok; | |
952 | ||
953 | /* MIPS32 or MIPS64 compliant CPU. */ | |
954 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
955 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
956 | ||
957 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
958 | ||
959 | /* Enable FTLB if present and not disabled */ | |
960 | set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); | |
961 | ||
962 | ok = decode_config0(c); /* Read Config registers. */ | |
963 | BUG_ON(!ok); /* Arch spec violation! */ | |
964 | if (ok) | |
965 | ok = decode_config1(c); | |
966 | if (ok) | |
967 | ok = decode_config2(c); | |
968 | if (ok) | |
969 | ok = decode_config3(c); | |
970 | if (ok) | |
971 | ok = decode_config4(c); | |
972 | if (ok) | |
973 | ok = decode_config5(c); | |
974 | ||
975 | /* Probe the EBase.WG bit */ | |
976 | if (cpu_has_mips_r2_r6) { | |
977 | u64 ebase; | |
978 | unsigned int status; | |
979 | ||
980 | /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ | |
981 | ebase = cpu_has_mips64r6 ? read_c0_ebase_64() | |
982 | : (s32)read_c0_ebase(); | |
983 | if (ebase & MIPS_EBASE_WG) { | |
984 | /* WG bit already set, we can avoid the clumsy probe */ | |
985 | c->options |= MIPS_CPU_EBASE_WG; | |
986 | } else { | |
987 | /* Its UNDEFINED to change EBase while BEV=0 */ | |
988 | status = read_c0_status(); | |
989 | write_c0_status(status | ST0_BEV); | |
990 | irq_enable_hazard(); | |
991 | /* | |
992 | * On pre-r6 cores, this may well clobber the upper bits | |
993 | * of EBase. This is hard to avoid without potentially | |
994 | * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. | |
995 | */ | |
996 | if (cpu_has_mips64r6) | |
997 | write_c0_ebase_64(ebase | MIPS_EBASE_WG); | |
998 | else | |
999 | write_c0_ebase(ebase | MIPS_EBASE_WG); | |
1000 | back_to_back_c0_hazard(); | |
1001 | /* Restore BEV */ | |
1002 | write_c0_status(status); | |
1003 | if (read_c0_ebase() & MIPS_EBASE_WG) { | |
1004 | c->options |= MIPS_CPU_EBASE_WG; | |
1005 | write_c0_ebase(ebase); | |
1006 | } | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | /* configure the FTLB write probability */ | |
1011 | set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); | |
1012 | ||
1013 | mips_probe_watch_registers(c); | |
1014 | ||
1015 | #ifndef CONFIG_MIPS_CPS | |
1016 | if (cpu_has_mips_r2_r6) { | |
1017 | unsigned int core; | |
1018 | ||
1019 | core = get_ebase_cpunum(); | |
1020 | if (cpu_has_mipsmt) | |
1021 | core >>= fls(core_nvpes()) - 1; | |
1022 | cpu_set_core(c, core); | |
1023 | } | |
1024 | #endif | |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * Probe for certain guest capabilities by writing config bits and reading back. | |
1029 | * Finally write back the original value. | |
1030 | */ | |
1031 | #define probe_gc0_config(name, maxconf, bits) \ | |
1032 | do { \ | |
1033 | unsigned int tmp; \ | |
1034 | tmp = read_gc0_##name(); \ | |
1035 | write_gc0_##name(tmp | (bits)); \ | |
1036 | back_to_back_c0_hazard(); \ | |
1037 | maxconf = read_gc0_##name(); \ | |
1038 | write_gc0_##name(tmp); \ | |
1039 | } while (0) | |
1040 | ||
1041 | /* | |
1042 | * Probe for dynamic guest capabilities by changing certain config bits and | |
1043 | * reading back to see if they change. Finally write back the original value. | |
1044 | */ | |
1045 | #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ | |
1046 | do { \ | |
1047 | maxconf = read_gc0_##name(); \ | |
1048 | write_gc0_##name(maxconf ^ (bits)); \ | |
1049 | back_to_back_c0_hazard(); \ | |
1050 | dynconf = maxconf ^ read_gc0_##name(); \ | |
1051 | write_gc0_##name(maxconf); \ | |
1052 | maxconf |= dynconf; \ | |
1053 | } while (0) | |
1054 | ||
1055 | static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) | |
1056 | { | |
1057 | unsigned int config0; | |
1058 | ||
1059 | probe_gc0_config(config, config0, MIPS_CONF_M); | |
1060 | ||
1061 | if (config0 & MIPS_CONF_M) | |
1062 | c->guest.conf |= BIT(1); | |
1063 | return config0 & MIPS_CONF_M; | |
1064 | } | |
1065 | ||
1066 | static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) | |
1067 | { | |
1068 | unsigned int config1, config1_dyn; | |
1069 | ||
1070 | probe_gc0_config_dyn(config1, config1, config1_dyn, | |
1071 | MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | | |
1072 | MIPS_CONF1_FP); | |
1073 | ||
1074 | if (config1 & MIPS_CONF1_FP) | |
1075 | c->guest.options |= MIPS_CPU_FPU; | |
1076 | if (config1_dyn & MIPS_CONF1_FP) | |
1077 | c->guest.options_dyn |= MIPS_CPU_FPU; | |
1078 | ||
1079 | if (config1 & MIPS_CONF1_WR) | |
1080 | c->guest.options |= MIPS_CPU_WATCH; | |
1081 | if (config1_dyn & MIPS_CONF1_WR) | |
1082 | c->guest.options_dyn |= MIPS_CPU_WATCH; | |
1083 | ||
1084 | if (config1 & MIPS_CONF1_PC) | |
1085 | c->guest.options |= MIPS_CPU_PERF; | |
1086 | if (config1_dyn & MIPS_CONF1_PC) | |
1087 | c->guest.options_dyn |= MIPS_CPU_PERF; | |
1088 | ||
1089 | if (config1 & MIPS_CONF_M) | |
1090 | c->guest.conf |= BIT(2); | |
1091 | return config1 & MIPS_CONF_M; | |
1092 | } | |
1093 | ||
1094 | static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) | |
1095 | { | |
1096 | unsigned int config2; | |
1097 | ||
1098 | probe_gc0_config(config2, config2, MIPS_CONF_M); | |
1099 | ||
1100 | if (config2 & MIPS_CONF_M) | |
1101 | c->guest.conf |= BIT(3); | |
1102 | return config2 & MIPS_CONF_M; | |
1103 | } | |
1104 | ||
1105 | static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) | |
1106 | { | |
1107 | unsigned int config3, config3_dyn; | |
1108 | ||
1109 | probe_gc0_config_dyn(config3, config3, config3_dyn, | |
1110 | MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | | |
1111 | MIPS_CONF3_CTXTC); | |
1112 | ||
1113 | if (config3 & MIPS_CONF3_CTXTC) | |
1114 | c->guest.options |= MIPS_CPU_CTXTC; | |
1115 | if (config3_dyn & MIPS_CONF3_CTXTC) | |
1116 | c->guest.options_dyn |= MIPS_CPU_CTXTC; | |
1117 | ||
1118 | if (config3 & MIPS_CONF3_PW) | |
1119 | c->guest.options |= MIPS_CPU_HTW; | |
1120 | ||
1121 | if (config3 & MIPS_CONF3_ULRI) | |
1122 | c->guest.options |= MIPS_CPU_ULRI; | |
1123 | ||
1124 | if (config3 & MIPS_CONF3_SC) | |
1125 | c->guest.options |= MIPS_CPU_SEGMENTS; | |
1126 | ||
1127 | if (config3 & MIPS_CONF3_BI) | |
1128 | c->guest.options |= MIPS_CPU_BADINSTR; | |
1129 | if (config3 & MIPS_CONF3_BP) | |
1130 | c->guest.options |= MIPS_CPU_BADINSTRP; | |
1131 | ||
1132 | if (config3 & MIPS_CONF3_MSA) | |
1133 | c->guest.ases |= MIPS_ASE_MSA; | |
1134 | if (config3_dyn & MIPS_CONF3_MSA) | |
1135 | c->guest.ases_dyn |= MIPS_ASE_MSA; | |
1136 | ||
1137 | if (config3 & MIPS_CONF_M) | |
1138 | c->guest.conf |= BIT(4); | |
1139 | return config3 & MIPS_CONF_M; | |
1140 | } | |
1141 | ||
1142 | static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) | |
1143 | { | |
1144 | unsigned int config4; | |
1145 | ||
1146 | probe_gc0_config(config4, config4, | |
1147 | MIPS_CONF_M | MIPS_CONF4_KSCREXIST); | |
1148 | ||
1149 | c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) | |
1150 | >> MIPS_CONF4_KSCREXIST_SHIFT; | |
1151 | ||
1152 | if (config4 & MIPS_CONF_M) | |
1153 | c->guest.conf |= BIT(5); | |
1154 | return config4 & MIPS_CONF_M; | |
1155 | } | |
1156 | ||
1157 | static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) | |
1158 | { | |
1159 | unsigned int config5, config5_dyn; | |
1160 | ||
1161 | probe_gc0_config_dyn(config5, config5, config5_dyn, | |
1162 | MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); | |
1163 | ||
1164 | if (config5 & MIPS_CONF5_MRP) | |
1165 | c->guest.options |= MIPS_CPU_MAAR; | |
1166 | if (config5_dyn & MIPS_CONF5_MRP) | |
1167 | c->guest.options_dyn |= MIPS_CPU_MAAR; | |
1168 | ||
1169 | if (config5 & MIPS_CONF5_LLB) | |
1170 | c->guest.options |= MIPS_CPU_RW_LLB; | |
1171 | ||
1172 | if (config5 & MIPS_CONF5_MVH) | |
1173 | c->guest.options |= MIPS_CPU_MVH; | |
1174 | ||
1175 | if (config5 & MIPS_CONF_M) | |
1176 | c->guest.conf |= BIT(6); | |
1177 | return config5 & MIPS_CONF_M; | |
1178 | } | |
1179 | ||
1180 | static inline void decode_guest_configs(struct cpuinfo_mips *c) | |
1181 | { | |
1182 | unsigned int ok; | |
1183 | ||
1184 | ok = decode_guest_config0(c); | |
1185 | if (ok) | |
1186 | ok = decode_guest_config1(c); | |
1187 | if (ok) | |
1188 | ok = decode_guest_config2(c); | |
1189 | if (ok) | |
1190 | ok = decode_guest_config3(c); | |
1191 | if (ok) | |
1192 | ok = decode_guest_config4(c); | |
1193 | if (ok) | |
1194 | decode_guest_config5(c); | |
1195 | } | |
1196 | ||
1197 | static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) | |
1198 | { | |
1199 | unsigned int guestctl0, temp; | |
1200 | ||
1201 | guestctl0 = read_c0_guestctl0(); | |
1202 | ||
1203 | if (guestctl0 & MIPS_GCTL0_G0E) | |
1204 | c->options |= MIPS_CPU_GUESTCTL0EXT; | |
1205 | if (guestctl0 & MIPS_GCTL0_G1) | |
1206 | c->options |= MIPS_CPU_GUESTCTL1; | |
1207 | if (guestctl0 & MIPS_GCTL0_G2) | |
1208 | c->options |= MIPS_CPU_GUESTCTL2; | |
1209 | if (!(guestctl0 & MIPS_GCTL0_RAD)) { | |
1210 | c->options |= MIPS_CPU_GUESTID; | |
1211 | ||
1212 | /* | |
1213 | * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 | |
1214 | * first, otherwise all data accesses will be fully virtualised | |
1215 | * as if they were performed by guest mode. | |
1216 | */ | |
1217 | write_c0_guestctl1(0); | |
1218 | tlbw_use_hazard(); | |
1219 | ||
1220 | write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); | |
1221 | back_to_back_c0_hazard(); | |
1222 | temp = read_c0_guestctl0(); | |
1223 | ||
1224 | if (temp & MIPS_GCTL0_DRG) { | |
1225 | write_c0_guestctl0(guestctl0); | |
1226 | c->options |= MIPS_CPU_DRG; | |
1227 | } | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) | |
1232 | { | |
1233 | if (cpu_has_guestid) { | |
1234 | /* determine the number of bits of GuestID available */ | |
1235 | write_c0_guestctl1(MIPS_GCTL1_ID); | |
1236 | back_to_back_c0_hazard(); | |
1237 | c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) | |
1238 | >> MIPS_GCTL1_ID_SHIFT; | |
1239 | write_c0_guestctl1(0); | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) | |
1244 | { | |
1245 | /* determine the number of bits of GTOffset available */ | |
1246 | write_c0_gtoffset(0xffffffff); | |
1247 | back_to_back_c0_hazard(); | |
1248 | c->gtoffset_mask = read_c0_gtoffset(); | |
1249 | write_c0_gtoffset(0); | |
1250 | } | |
1251 | ||
1252 | static inline void cpu_probe_vz(struct cpuinfo_mips *c) | |
1253 | { | |
1254 | cpu_probe_guestctl0(c); | |
1255 | if (cpu_has_guestctl1) | |
1256 | cpu_probe_guestctl1(c); | |
1257 | ||
1258 | cpu_probe_gtoffset(c); | |
1259 | ||
1260 | decode_guest_configs(c); | |
1261 | } | |
1262 | ||
1263 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | |
1264 | | MIPS_CPU_COUNTER) | |
1265 | ||
1266 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |
1267 | { | |
1268 | switch (c->processor_id & PRID_IMP_MASK) { | |
1269 | case PRID_IMP_R2000: | |
1270 | c->cputype = CPU_R2000; | |
1271 | __cpu_name[cpu] = "R2000"; | |
1272 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; | |
1273 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | | |
1274 | MIPS_CPU_NOFPUEX; | |
1275 | if (__cpu_has_fpu()) | |
1276 | c->options |= MIPS_CPU_FPU; | |
1277 | c->tlbsize = 64; | |
1278 | break; | |
1279 | case PRID_IMP_R3000: | |
1280 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { | |
1281 | if (cpu_has_confreg()) { | |
1282 | c->cputype = CPU_R3081E; | |
1283 | __cpu_name[cpu] = "R3081"; | |
1284 | } else { | |
1285 | c->cputype = CPU_R3000A; | |
1286 | __cpu_name[cpu] = "R3000A"; | |
1287 | } | |
1288 | } else { | |
1289 | c->cputype = CPU_R3000; | |
1290 | __cpu_name[cpu] = "R3000"; | |
1291 | } | |
1292 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; | |
1293 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | | |
1294 | MIPS_CPU_NOFPUEX; | |
1295 | if (__cpu_has_fpu()) | |
1296 | c->options |= MIPS_CPU_FPU; | |
1297 | c->tlbsize = 64; | |
1298 | break; | |
1299 | case PRID_IMP_R4000: | |
1300 | if (read_c0_config() & CONF_SC) { | |
1301 | if ((c->processor_id & PRID_REV_MASK) >= | |
1302 | PRID_REV_R4400) { | |
1303 | c->cputype = CPU_R4400PC; | |
1304 | __cpu_name[cpu] = "R4400PC"; | |
1305 | } else { | |
1306 | c->cputype = CPU_R4000PC; | |
1307 | __cpu_name[cpu] = "R4000PC"; | |
1308 | } | |
1309 | } else { | |
1310 | int cca = read_c0_config() & CONF_CM_CMASK; | |
1311 | int mc; | |
1312 | ||
1313 | /* | |
1314 | * SC and MC versions can't be reliably told apart, | |
1315 | * but only the latter support coherent caching | |
1316 | * modes so assume the firmware has set the KSEG0 | |
1317 | * coherency attribute reasonably (if uncached, we | |
1318 | * assume SC). | |
1319 | */ | |
1320 | switch (cca) { | |
1321 | case CONF_CM_CACHABLE_CE: | |
1322 | case CONF_CM_CACHABLE_COW: | |
1323 | case CONF_CM_CACHABLE_CUW: | |
1324 | mc = 1; | |
1325 | break; | |
1326 | default: | |
1327 | mc = 0; | |
1328 | break; | |
1329 | } | |
1330 | if ((c->processor_id & PRID_REV_MASK) >= | |
1331 | PRID_REV_R4400) { | |
1332 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; | |
1333 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; | |
1334 | } else { | |
1335 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; | |
1336 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | set_isa(c, MIPS_CPU_ISA_III); | |
1341 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1342 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1343 | MIPS_CPU_WATCH | MIPS_CPU_VCE | | |
1344 | MIPS_CPU_LLSC; | |
1345 | c->tlbsize = 48; | |
1346 | break; | |
1347 | case PRID_IMP_VR41XX: | |
1348 | set_isa(c, MIPS_CPU_ISA_III); | |
1349 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1350 | c->options = R4K_OPTS; | |
1351 | c->tlbsize = 32; | |
1352 | switch (c->processor_id & 0xf0) { | |
1353 | case PRID_REV_VR4111: | |
1354 | c->cputype = CPU_VR4111; | |
1355 | __cpu_name[cpu] = "NEC VR4111"; | |
1356 | break; | |
1357 | case PRID_REV_VR4121: | |
1358 | c->cputype = CPU_VR4121; | |
1359 | __cpu_name[cpu] = "NEC VR4121"; | |
1360 | break; | |
1361 | case PRID_REV_VR4122: | |
1362 | if ((c->processor_id & 0xf) < 0x3) { | |
1363 | c->cputype = CPU_VR4122; | |
1364 | __cpu_name[cpu] = "NEC VR4122"; | |
1365 | } else { | |
1366 | c->cputype = CPU_VR4181A; | |
1367 | __cpu_name[cpu] = "NEC VR4181A"; | |
1368 | } | |
1369 | break; | |
1370 | case PRID_REV_VR4130: | |
1371 | if ((c->processor_id & 0xf) < 0x4) { | |
1372 | c->cputype = CPU_VR4131; | |
1373 | __cpu_name[cpu] = "NEC VR4131"; | |
1374 | } else { | |
1375 | c->cputype = CPU_VR4133; | |
1376 | c->options |= MIPS_CPU_LLSC; | |
1377 | __cpu_name[cpu] = "NEC VR4133"; | |
1378 | } | |
1379 | break; | |
1380 | default: | |
1381 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
1382 | c->cputype = CPU_VR41XX; | |
1383 | __cpu_name[cpu] = "NEC Vr41xx"; | |
1384 | break; | |
1385 | } | |
1386 | break; | |
1387 | case PRID_IMP_R4300: | |
1388 | c->cputype = CPU_R4300; | |
1389 | __cpu_name[cpu] = "R4300"; | |
1390 | set_isa(c, MIPS_CPU_ISA_III); | |
1391 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1392 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1393 | MIPS_CPU_LLSC; | |
1394 | c->tlbsize = 32; | |
1395 | break; | |
1396 | case PRID_IMP_R4600: | |
1397 | c->cputype = CPU_R4600; | |
1398 | __cpu_name[cpu] = "R4600"; | |
1399 | set_isa(c, MIPS_CPU_ISA_III); | |
1400 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1401 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1402 | MIPS_CPU_LLSC; | |
1403 | c->tlbsize = 48; | |
1404 | break; | |
1405 | #if 0 | |
1406 | case PRID_IMP_R4650: | |
1407 | /* | |
1408 | * This processor doesn't have an MMU, so it's not | |
1409 | * "real easy" to run Linux on it. It is left purely | |
1410 | * for documentation. Commented out because it shares | |
1411 | * it's c0_prid id number with the TX3900. | |
1412 | */ | |
1413 | c->cputype = CPU_R4650; | |
1414 | __cpu_name[cpu] = "R4650"; | |
1415 | set_isa(c, MIPS_CPU_ISA_III); | |
1416 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1417 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; | |
1418 | c->tlbsize = 48; | |
1419 | break; | |
1420 | #endif | |
1421 | case PRID_IMP_TX39: | |
1422 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; | |
1423 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; | |
1424 | ||
1425 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
1426 | c->cputype = CPU_TX3927; | |
1427 | __cpu_name[cpu] = "TX3927"; | |
1428 | c->tlbsize = 64; | |
1429 | } else { | |
1430 | switch (c->processor_id & PRID_REV_MASK) { | |
1431 | case PRID_REV_TX3912: | |
1432 | c->cputype = CPU_TX3912; | |
1433 | __cpu_name[cpu] = "TX3912"; | |
1434 | c->tlbsize = 32; | |
1435 | break; | |
1436 | case PRID_REV_TX3922: | |
1437 | c->cputype = CPU_TX3922; | |
1438 | __cpu_name[cpu] = "TX3922"; | |
1439 | c->tlbsize = 64; | |
1440 | break; | |
1441 | } | |
1442 | } | |
1443 | break; | |
1444 | case PRID_IMP_R4700: | |
1445 | c->cputype = CPU_R4700; | |
1446 | __cpu_name[cpu] = "R4700"; | |
1447 | set_isa(c, MIPS_CPU_ISA_III); | |
1448 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1449 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1450 | MIPS_CPU_LLSC; | |
1451 | c->tlbsize = 48; | |
1452 | break; | |
1453 | case PRID_IMP_TX49: | |
1454 | c->cputype = CPU_TX49XX; | |
1455 | __cpu_name[cpu] = "R49XX"; | |
1456 | set_isa(c, MIPS_CPU_ISA_III); | |
1457 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1458 | c->options = R4K_OPTS | MIPS_CPU_LLSC; | |
1459 | if (!(c->processor_id & 0x08)) | |
1460 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
1461 | c->tlbsize = 48; | |
1462 | break; | |
1463 | case PRID_IMP_R5000: | |
1464 | c->cputype = CPU_R5000; | |
1465 | __cpu_name[cpu] = "R5000"; | |
1466 | set_isa(c, MIPS_CPU_ISA_IV); | |
1467 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1468 | MIPS_CPU_LLSC; | |
1469 | c->tlbsize = 48; | |
1470 | break; | |
1471 | case PRID_IMP_R5432: | |
1472 | c->cputype = CPU_R5432; | |
1473 | __cpu_name[cpu] = "R5432"; | |
1474 | set_isa(c, MIPS_CPU_ISA_IV); | |
1475 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1476 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
1477 | c->tlbsize = 48; | |
1478 | break; | |
1479 | case PRID_IMP_R5500: | |
1480 | c->cputype = CPU_R5500; | |
1481 | __cpu_name[cpu] = "R5500"; | |
1482 | set_isa(c, MIPS_CPU_ISA_IV); | |
1483 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1484 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
1485 | c->tlbsize = 48; | |
1486 | break; | |
1487 | case PRID_IMP_NEVADA: | |
1488 | c->cputype = CPU_NEVADA; | |
1489 | __cpu_name[cpu] = "Nevada"; | |
1490 | set_isa(c, MIPS_CPU_ISA_IV); | |
1491 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1492 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; | |
1493 | c->tlbsize = 48; | |
1494 | break; | |
1495 | case PRID_IMP_RM7000: | |
1496 | c->cputype = CPU_RM7000; | |
1497 | __cpu_name[cpu] = "RM7000"; | |
1498 | set_isa(c, MIPS_CPU_ISA_IV); | |
1499 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1500 | MIPS_CPU_LLSC; | |
1501 | /* | |
1502 | * Undocumented RM7000: Bit 29 in the info register of | |
1503 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 | |
1504 | * entries. | |
1505 | * | |
1506 | * 29 1 => 64 entry JTLB | |
1507 | * 0 => 48 entry JTLB | |
1508 | */ | |
1509 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
1510 | break; | |
1511 | case PRID_IMP_R8000: | |
1512 | c->cputype = CPU_R8000; | |
1513 | __cpu_name[cpu] = "RM8000"; | |
1514 | set_isa(c, MIPS_CPU_ISA_IV); | |
1515 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | | |
1516 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1517 | MIPS_CPU_LLSC; | |
1518 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ | |
1519 | break; | |
1520 | case PRID_IMP_R10000: | |
1521 | c->cputype = CPU_R10000; | |
1522 | __cpu_name[cpu] = "R10000"; | |
1523 | set_isa(c, MIPS_CPU_ISA_IV); | |
1524 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
1525 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1526 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
1527 | MIPS_CPU_LLSC; | |
1528 | c->tlbsize = 64; | |
1529 | break; | |
1530 | case PRID_IMP_R12000: | |
1531 | c->cputype = CPU_R12000; | |
1532 | __cpu_name[cpu] = "R12000"; | |
1533 | set_isa(c, MIPS_CPU_ISA_IV); | |
1534 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
1535 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1536 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
1537 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; | |
1538 | c->tlbsize = 64; | |
1539 | break; | |
1540 | case PRID_IMP_R14000: | |
1541 | if (((c->processor_id >> 4) & 0x0f) > 2) { | |
1542 | c->cputype = CPU_R16000; | |
1543 | __cpu_name[cpu] = "R16000"; | |
1544 | } else { | |
1545 | c->cputype = CPU_R14000; | |
1546 | __cpu_name[cpu] = "R14000"; | |
1547 | } | |
1548 | set_isa(c, MIPS_CPU_ISA_IV); | |
1549 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
1550 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
1551 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
1552 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; | |
1553 | c->tlbsize = 64; | |
1554 | break; | |
1555 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ | |
1556 | switch (c->processor_id & PRID_REV_MASK) { | |
1557 | case PRID_REV_LOONGSON2E: | |
1558 | c->cputype = CPU_LOONGSON2; | |
1559 | __cpu_name[cpu] = "ICT Loongson-2"; | |
1560 | set_elf_platform(cpu, "loongson2e"); | |
1561 | set_isa(c, MIPS_CPU_ISA_III); | |
1562 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1563 | break; | |
1564 | case PRID_REV_LOONGSON2F: | |
1565 | c->cputype = CPU_LOONGSON2; | |
1566 | __cpu_name[cpu] = "ICT Loongson-2"; | |
1567 | set_elf_platform(cpu, "loongson2f"); | |
1568 | set_isa(c, MIPS_CPU_ISA_III); | |
1569 | c->fpu_msk31 |= FPU_CSR_CONDX; | |
1570 | break; | |
1571 | case PRID_REV_LOONGSON3A_R1: | |
1572 | c->cputype = CPU_LOONGSON3; | |
1573 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1574 | set_elf_platform(cpu, "loongson3a"); | |
1575 | set_isa(c, MIPS_CPU_ISA_M64R1); | |
1576 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | | |
1577 | MIPS_ASE_LOONGSON_EXT); | |
1578 | break; | |
1579 | case PRID_REV_LOONGSON3B_R1: | |
1580 | case PRID_REV_LOONGSON3B_R2: | |
1581 | c->cputype = CPU_LOONGSON3; | |
1582 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1583 | set_elf_platform(cpu, "loongson3b"); | |
1584 | set_isa(c, MIPS_CPU_ISA_M64R1); | |
1585 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | | |
1586 | MIPS_ASE_LOONGSON_EXT); | |
1587 | break; | |
1588 | } | |
1589 | ||
1590 | c->options = R4K_OPTS | | |
1591 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
1592 | MIPS_CPU_32FPR; | |
1593 | c->tlbsize = 64; | |
1594 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; | |
1595 | break; | |
1596 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ | |
1597 | decode_configs(c); | |
1598 | ||
1599 | c->cputype = CPU_LOONGSON1; | |
1600 | ||
1601 | switch (c->processor_id & PRID_REV_MASK) { | |
1602 | case PRID_REV_LOONGSON1B: | |
1603 | __cpu_name[cpu] = "Loongson 1B"; | |
1604 | break; | |
1605 | } | |
1606 | ||
1607 | break; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | |
1612 | { | |
1613 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; | |
1614 | switch (c->processor_id & PRID_IMP_MASK) { | |
1615 | case PRID_IMP_QEMU_GENERIC: | |
1616 | c->writecombine = _CACHE_UNCACHED; | |
1617 | c->cputype = CPU_QEMU_GENERIC; | |
1618 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; | |
1619 | break; | |
1620 | case PRID_IMP_4KC: | |
1621 | c->cputype = CPU_4KC; | |
1622 | c->writecombine = _CACHE_UNCACHED; | |
1623 | __cpu_name[cpu] = "MIPS 4Kc"; | |
1624 | break; | |
1625 | case PRID_IMP_4KEC: | |
1626 | case PRID_IMP_4KECR2: | |
1627 | c->cputype = CPU_4KEC; | |
1628 | c->writecombine = _CACHE_UNCACHED; | |
1629 | __cpu_name[cpu] = "MIPS 4KEc"; | |
1630 | break; | |
1631 | case PRID_IMP_4KSC: | |
1632 | case PRID_IMP_4KSD: | |
1633 | c->cputype = CPU_4KSC; | |
1634 | c->writecombine = _CACHE_UNCACHED; | |
1635 | __cpu_name[cpu] = "MIPS 4KSc"; | |
1636 | break; | |
1637 | case PRID_IMP_5KC: | |
1638 | c->cputype = CPU_5KC; | |
1639 | c->writecombine = _CACHE_UNCACHED; | |
1640 | __cpu_name[cpu] = "MIPS 5Kc"; | |
1641 | break; | |
1642 | case PRID_IMP_5KE: | |
1643 | c->cputype = CPU_5KE; | |
1644 | c->writecombine = _CACHE_UNCACHED; | |
1645 | __cpu_name[cpu] = "MIPS 5KE"; | |
1646 | break; | |
1647 | case PRID_IMP_20KC: | |
1648 | c->cputype = CPU_20KC; | |
1649 | c->writecombine = _CACHE_UNCACHED; | |
1650 | __cpu_name[cpu] = "MIPS 20Kc"; | |
1651 | break; | |
1652 | case PRID_IMP_24K: | |
1653 | c->cputype = CPU_24K; | |
1654 | c->writecombine = _CACHE_UNCACHED; | |
1655 | __cpu_name[cpu] = "MIPS 24Kc"; | |
1656 | break; | |
1657 | case PRID_IMP_24KE: | |
1658 | c->cputype = CPU_24K; | |
1659 | c->writecombine = _CACHE_UNCACHED; | |
1660 | __cpu_name[cpu] = "MIPS 24KEc"; | |
1661 | break; | |
1662 | case PRID_IMP_25KF: | |
1663 | c->cputype = CPU_25KF; | |
1664 | c->writecombine = _CACHE_UNCACHED; | |
1665 | __cpu_name[cpu] = "MIPS 25Kc"; | |
1666 | break; | |
1667 | case PRID_IMP_34K: | |
1668 | c->cputype = CPU_34K; | |
1669 | c->writecombine = _CACHE_UNCACHED; | |
1670 | __cpu_name[cpu] = "MIPS 34Kc"; | |
1671 | cpu_set_mt_per_tc_perf(c); | |
1672 | break; | |
1673 | case PRID_IMP_74K: | |
1674 | c->cputype = CPU_74K; | |
1675 | c->writecombine = _CACHE_UNCACHED; | |
1676 | __cpu_name[cpu] = "MIPS 74Kc"; | |
1677 | break; | |
1678 | case PRID_IMP_M14KC: | |
1679 | c->cputype = CPU_M14KC; | |
1680 | c->writecombine = _CACHE_UNCACHED; | |
1681 | __cpu_name[cpu] = "MIPS M14Kc"; | |
1682 | break; | |
1683 | case PRID_IMP_M14KEC: | |
1684 | c->cputype = CPU_M14KEC; | |
1685 | c->writecombine = _CACHE_UNCACHED; | |
1686 | __cpu_name[cpu] = "MIPS M14KEc"; | |
1687 | break; | |
1688 | case PRID_IMP_1004K: | |
1689 | c->cputype = CPU_1004K; | |
1690 | c->writecombine = _CACHE_UNCACHED; | |
1691 | __cpu_name[cpu] = "MIPS 1004Kc"; | |
1692 | cpu_set_mt_per_tc_perf(c); | |
1693 | break; | |
1694 | case PRID_IMP_1074K: | |
1695 | c->cputype = CPU_1074K; | |
1696 | c->writecombine = _CACHE_UNCACHED; | |
1697 | __cpu_name[cpu] = "MIPS 1074Kc"; | |
1698 | break; | |
1699 | case PRID_IMP_INTERAPTIV_UP: | |
1700 | c->cputype = CPU_INTERAPTIV; | |
1701 | __cpu_name[cpu] = "MIPS interAptiv"; | |
1702 | cpu_set_mt_per_tc_perf(c); | |
1703 | break; | |
1704 | case PRID_IMP_INTERAPTIV_MP: | |
1705 | c->cputype = CPU_INTERAPTIV; | |
1706 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; | |
1707 | cpu_set_mt_per_tc_perf(c); | |
1708 | break; | |
1709 | case PRID_IMP_PROAPTIV_UP: | |
1710 | c->cputype = CPU_PROAPTIV; | |
1711 | __cpu_name[cpu] = "MIPS proAptiv"; | |
1712 | break; | |
1713 | case PRID_IMP_PROAPTIV_MP: | |
1714 | c->cputype = CPU_PROAPTIV; | |
1715 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; | |
1716 | break; | |
1717 | case PRID_IMP_P5600: | |
1718 | c->cputype = CPU_P5600; | |
1719 | __cpu_name[cpu] = "MIPS P5600"; | |
1720 | break; | |
1721 | case PRID_IMP_P6600: | |
1722 | c->cputype = CPU_P6600; | |
1723 | __cpu_name[cpu] = "MIPS P6600"; | |
1724 | break; | |
1725 | case PRID_IMP_I6400: | |
1726 | c->cputype = CPU_I6400; | |
1727 | __cpu_name[cpu] = "MIPS I6400"; | |
1728 | break; | |
1729 | case PRID_IMP_I6500: | |
1730 | c->cputype = CPU_I6500; | |
1731 | __cpu_name[cpu] = "MIPS I6500"; | |
1732 | break; | |
1733 | case PRID_IMP_M5150: | |
1734 | c->cputype = CPU_M5150; | |
1735 | __cpu_name[cpu] = "MIPS M5150"; | |
1736 | break; | |
1737 | case PRID_IMP_M6250: | |
1738 | c->cputype = CPU_M6250; | |
1739 | __cpu_name[cpu] = "MIPS M6250"; | |
1740 | break; | |
1741 | } | |
1742 | ||
1743 | decode_configs(c); | |
1744 | ||
1745 | spram_config(); | |
1746 | ||
1747 | switch (__get_cpu_type(c->cputype)) { | |
1748 | case CPU_I6500: | |
1749 | c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; | |
1750 | /* fall-through */ | |
1751 | case CPU_I6400: | |
1752 | c->options |= MIPS_CPU_SHARED_FTLB_RAM; | |
1753 | /* fall-through */ | |
1754 | default: | |
1755 | break; | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) | |
1760 | { | |
1761 | decode_configs(c); | |
1762 | switch (c->processor_id & PRID_IMP_MASK) { | |
1763 | case PRID_IMP_AU1_REV1: | |
1764 | case PRID_IMP_AU1_REV2: | |
1765 | c->cputype = CPU_ALCHEMY; | |
1766 | switch ((c->processor_id >> 24) & 0xff) { | |
1767 | case 0: | |
1768 | __cpu_name[cpu] = "Au1000"; | |
1769 | break; | |
1770 | case 1: | |
1771 | __cpu_name[cpu] = "Au1500"; | |
1772 | break; | |
1773 | case 2: | |
1774 | __cpu_name[cpu] = "Au1100"; | |
1775 | break; | |
1776 | case 3: | |
1777 | __cpu_name[cpu] = "Au1550"; | |
1778 | break; | |
1779 | case 4: | |
1780 | __cpu_name[cpu] = "Au1200"; | |
1781 | if ((c->processor_id & PRID_REV_MASK) == 2) | |
1782 | __cpu_name[cpu] = "Au1250"; | |
1783 | break; | |
1784 | case 5: | |
1785 | __cpu_name[cpu] = "Au1210"; | |
1786 | break; | |
1787 | default: | |
1788 | __cpu_name[cpu] = "Au1xxx"; | |
1789 | break; | |
1790 | } | |
1791 | break; | |
1792 | } | |
1793 | } | |
1794 | ||
1795 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) | |
1796 | { | |
1797 | decode_configs(c); | |
1798 | ||
1799 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; | |
1800 | switch (c->processor_id & PRID_IMP_MASK) { | |
1801 | case PRID_IMP_SB1: | |
1802 | c->cputype = CPU_SB1; | |
1803 | __cpu_name[cpu] = "SiByte SB1"; | |
1804 | /* FPU in pass1 is known to have issues. */ | |
1805 | if ((c->processor_id & PRID_REV_MASK) < 0x02) | |
1806 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); | |
1807 | break; | |
1808 | case PRID_IMP_SB1A: | |
1809 | c->cputype = CPU_SB1A; | |
1810 | __cpu_name[cpu] = "SiByte SB1A"; | |
1811 | break; | |
1812 | } | |
1813 | } | |
1814 | ||
1815 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) | |
1816 | { | |
1817 | decode_configs(c); | |
1818 | switch (c->processor_id & PRID_IMP_MASK) { | |
1819 | case PRID_IMP_SR71000: | |
1820 | c->cputype = CPU_SR71000; | |
1821 | __cpu_name[cpu] = "Sandcraft SR71000"; | |
1822 | c->scache.ways = 8; | |
1823 | c->tlbsize = 64; | |
1824 | break; | |
1825 | } | |
1826 | } | |
1827 | ||
1828 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) | |
1829 | { | |
1830 | decode_configs(c); | |
1831 | switch (c->processor_id & PRID_IMP_MASK) { | |
1832 | case PRID_IMP_PR4450: | |
1833 | c->cputype = CPU_PR4450; | |
1834 | __cpu_name[cpu] = "Philips PR4450"; | |
1835 | set_isa(c, MIPS_CPU_ISA_M32R1); | |
1836 | break; | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) | |
1841 | { | |
1842 | decode_configs(c); | |
1843 | switch (c->processor_id & PRID_IMP_MASK) { | |
1844 | case PRID_IMP_BMIPS32_REV4: | |
1845 | case PRID_IMP_BMIPS32_REV8: | |
1846 | c->cputype = CPU_BMIPS32; | |
1847 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
1848 | set_elf_platform(cpu, "bmips32"); | |
1849 | break; | |
1850 | case PRID_IMP_BMIPS3300: | |
1851 | case PRID_IMP_BMIPS3300_ALT: | |
1852 | case PRID_IMP_BMIPS3300_BUG: | |
1853 | c->cputype = CPU_BMIPS3300; | |
1854 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
1855 | set_elf_platform(cpu, "bmips3300"); | |
1856 | break; | |
1857 | case PRID_IMP_BMIPS43XX: { | |
1858 | int rev = c->processor_id & PRID_REV_MASK; | |
1859 | ||
1860 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1861 | rev <= PRID_REV_BMIPS4380_HI) { | |
1862 | c->cputype = CPU_BMIPS4380; | |
1863 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
1864 | set_elf_platform(cpu, "bmips4380"); | |
1865 | c->options |= MIPS_CPU_RIXI; | |
1866 | } else { | |
1867 | c->cputype = CPU_BMIPS4350; | |
1868 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
1869 | set_elf_platform(cpu, "bmips4350"); | |
1870 | } | |
1871 | break; | |
1872 | } | |
1873 | case PRID_IMP_BMIPS5000: | |
1874 | case PRID_IMP_BMIPS5200: | |
1875 | c->cputype = CPU_BMIPS5000; | |
1876 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) | |
1877 | __cpu_name[cpu] = "Broadcom BMIPS5200"; | |
1878 | else | |
1879 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
1880 | set_elf_platform(cpu, "bmips5000"); | |
1881 | c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; | |
1882 | break; | |
1883 | } | |
1884 | } | |
1885 | ||
1886 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) | |
1887 | { | |
1888 | decode_configs(c); | |
1889 | switch (c->processor_id & PRID_IMP_MASK) { | |
1890 | case PRID_IMP_CAVIUM_CN38XX: | |
1891 | case PRID_IMP_CAVIUM_CN31XX: | |
1892 | case PRID_IMP_CAVIUM_CN30XX: | |
1893 | c->cputype = CPU_CAVIUM_OCTEON; | |
1894 | __cpu_name[cpu] = "Cavium Octeon"; | |
1895 | goto platform; | |
1896 | case PRID_IMP_CAVIUM_CN58XX: | |
1897 | case PRID_IMP_CAVIUM_CN56XX: | |
1898 | case PRID_IMP_CAVIUM_CN50XX: | |
1899 | case PRID_IMP_CAVIUM_CN52XX: | |
1900 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; | |
1901 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1902 | platform: | |
1903 | set_elf_platform(cpu, "octeon"); | |
1904 | break; | |
1905 | case PRID_IMP_CAVIUM_CN61XX: | |
1906 | case PRID_IMP_CAVIUM_CN63XX: | |
1907 | case PRID_IMP_CAVIUM_CN66XX: | |
1908 | case PRID_IMP_CAVIUM_CN68XX: | |
1909 | case PRID_IMP_CAVIUM_CNF71XX: | |
1910 | c->cputype = CPU_CAVIUM_OCTEON2; | |
1911 | __cpu_name[cpu] = "Cavium Octeon II"; | |
1912 | set_elf_platform(cpu, "octeon2"); | |
1913 | break; | |
1914 | case PRID_IMP_CAVIUM_CN70XX: | |
1915 | case PRID_IMP_CAVIUM_CN73XX: | |
1916 | case PRID_IMP_CAVIUM_CNF75XX: | |
1917 | case PRID_IMP_CAVIUM_CN78XX: | |
1918 | c->cputype = CPU_CAVIUM_OCTEON3; | |
1919 | __cpu_name[cpu] = "Cavium Octeon III"; | |
1920 | set_elf_platform(cpu, "octeon3"); | |
1921 | break; | |
1922 | default: | |
1923 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1924 | c->cputype = CPU_UNKNOWN; | |
1925 | break; | |
1926 | } | |
1927 | } | |
1928 | ||
1929 | static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) | |
1930 | { | |
1931 | switch (c->processor_id & PRID_IMP_MASK) { | |
1932 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ | |
1933 | switch (c->processor_id & PRID_REV_MASK) { | |
1934 | case PRID_REV_LOONGSON3A_R2_0: | |
1935 | case PRID_REV_LOONGSON3A_R2_1: | |
1936 | c->cputype = CPU_LOONGSON3; | |
1937 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1938 | set_elf_platform(cpu, "loongson3a"); | |
1939 | set_isa(c, MIPS_CPU_ISA_M64R2); | |
1940 | break; | |
1941 | case PRID_REV_LOONGSON3A_R3_0: | |
1942 | case PRID_REV_LOONGSON3A_R3_1: | |
1943 | c->cputype = CPU_LOONGSON3; | |
1944 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1945 | set_elf_platform(cpu, "loongson3a"); | |
1946 | set_isa(c, MIPS_CPU_ISA_M64R2); | |
1947 | break; | |
1948 | } | |
1949 | ||
1950 | decode_configs(c); | |
1951 | c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; | |
1952 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; | |
1953 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | | |
1954 | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); | |
1955 | break; | |
1956 | default: | |
1957 | panic("Unknown Loongson Processor ID!"); | |
1958 | break; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) | |
1963 | { | |
1964 | decode_configs(c); | |
1965 | /* JZRISC does not implement the CP0 counter. */ | |
1966 | c->options &= ~MIPS_CPU_COUNTER; | |
1967 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); | |
1968 | switch (c->processor_id & PRID_IMP_MASK) { | |
1969 | case PRID_IMP_JZRISC: | |
1970 | c->cputype = CPU_JZRISC; | |
1971 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; | |
1972 | __cpu_name[cpu] = "Ingenic JZRISC"; | |
1973 | /* | |
1974 | * The XBurst core by default attempts to avoid branch target | |
1975 | * buffer lookups by detecting & special casing loops. This | |
1976 | * feature will cause BogoMIPS and lpj calculate in error. | |
1977 | * Set cp0 config7 bit 4 to disable this feature. | |
1978 | */ | |
1979 | set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); | |
1980 | break; | |
1981 | default: | |
1982 | panic("Unknown Ingenic Processor ID!"); | |
1983 | break; | |
1984 | } | |
1985 | ||
1986 | /* | |
1987 | * The config0 register in the Xburst CPUs with a processor ID of | |
1988 | * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, | |
1989 | * but they don't actually support this ISA. | |
1990 | */ | |
1991 | if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0) | |
1992 | c->isa_level &= ~MIPS_CPU_ISA_M32R2; | |
1993 | } | |
1994 | ||
1995 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) | |
1996 | { | |
1997 | decode_configs(c); | |
1998 | ||
1999 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { | |
2000 | c->cputype = CPU_ALCHEMY; | |
2001 | __cpu_name[cpu] = "Au1300"; | |
2002 | /* following stuff is not for Alchemy */ | |
2003 | return; | |
2004 | } | |
2005 | ||
2006 | c->options = (MIPS_CPU_TLB | | |
2007 | MIPS_CPU_4KEX | | |
2008 | MIPS_CPU_COUNTER | | |
2009 | MIPS_CPU_DIVEC | | |
2010 | MIPS_CPU_WATCH | | |
2011 | MIPS_CPU_EJTAG | | |
2012 | MIPS_CPU_LLSC); | |
2013 | ||
2014 | switch (c->processor_id & PRID_IMP_MASK) { | |
2015 | case PRID_IMP_NETLOGIC_XLP2XX: | |
2016 | case PRID_IMP_NETLOGIC_XLP9XX: | |
2017 | case PRID_IMP_NETLOGIC_XLP5XX: | |
2018 | c->cputype = CPU_XLP; | |
2019 | __cpu_name[cpu] = "Broadcom XLPII"; | |
2020 | break; | |
2021 | ||
2022 | case PRID_IMP_NETLOGIC_XLP8XX: | |
2023 | case PRID_IMP_NETLOGIC_XLP3XX: | |
2024 | c->cputype = CPU_XLP; | |
2025 | __cpu_name[cpu] = "Netlogic XLP"; | |
2026 | break; | |
2027 | ||
2028 | case PRID_IMP_NETLOGIC_XLR732: | |
2029 | case PRID_IMP_NETLOGIC_XLR716: | |
2030 | case PRID_IMP_NETLOGIC_XLR532: | |
2031 | case PRID_IMP_NETLOGIC_XLR308: | |
2032 | case PRID_IMP_NETLOGIC_XLR532C: | |
2033 | case PRID_IMP_NETLOGIC_XLR516C: | |
2034 | case PRID_IMP_NETLOGIC_XLR508C: | |
2035 | case PRID_IMP_NETLOGIC_XLR308C: | |
2036 | c->cputype = CPU_XLR; | |
2037 | __cpu_name[cpu] = "Netlogic XLR"; | |
2038 | break; | |
2039 | ||
2040 | case PRID_IMP_NETLOGIC_XLS608: | |
2041 | case PRID_IMP_NETLOGIC_XLS408: | |
2042 | case PRID_IMP_NETLOGIC_XLS404: | |
2043 | case PRID_IMP_NETLOGIC_XLS208: | |
2044 | case PRID_IMP_NETLOGIC_XLS204: | |
2045 | case PRID_IMP_NETLOGIC_XLS108: | |
2046 | case PRID_IMP_NETLOGIC_XLS104: | |
2047 | case PRID_IMP_NETLOGIC_XLS616B: | |
2048 | case PRID_IMP_NETLOGIC_XLS608B: | |
2049 | case PRID_IMP_NETLOGIC_XLS416B: | |
2050 | case PRID_IMP_NETLOGIC_XLS412B: | |
2051 | case PRID_IMP_NETLOGIC_XLS408B: | |
2052 | case PRID_IMP_NETLOGIC_XLS404B: | |
2053 | c->cputype = CPU_XLR; | |
2054 | __cpu_name[cpu] = "Netlogic XLS"; | |
2055 | break; | |
2056 | ||
2057 | default: | |
2058 | pr_info("Unknown Netlogic chip id [%02x]!\n", | |
2059 | c->processor_id); | |
2060 | c->cputype = CPU_XLR; | |
2061 | break; | |
2062 | } | |
2063 | ||
2064 | if (c->cputype == CPU_XLP) { | |
2065 | set_isa(c, MIPS_CPU_ISA_M64R2); | |
2066 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); | |
2067 | /* This will be updated again after all threads are woken up */ | |
2068 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
2069 | } else { | |
2070 | set_isa(c, MIPS_CPU_ISA_M64R1); | |
2071 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; | |
2072 | } | |
2073 | c->kscratch_mask = 0xf; | |
2074 | } | |
2075 | ||
2076 | #ifdef CONFIG_64BIT | |
2077 | /* For use by uaccess.h */ | |
2078 | u64 __ua_limit; | |
2079 | EXPORT_SYMBOL(__ua_limit); | |
2080 | #endif | |
2081 | ||
2082 | const char *__cpu_name[NR_CPUS]; | |
2083 | const char *__elf_platform; | |
2084 | ||
2085 | void cpu_probe(void) | |
2086 | { | |
2087 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
2088 | unsigned int cpu = smp_processor_id(); | |
2089 | ||
2090 | /* | |
2091 | * Set a default elf platform, cpu probe may later | |
2092 | * overwrite it with a more precise value | |
2093 | */ | |
2094 | set_elf_platform(cpu, "mips"); | |
2095 | ||
2096 | c->processor_id = PRID_IMP_UNKNOWN; | |
2097 | c->fpu_id = FPIR_IMP_NONE; | |
2098 | c->cputype = CPU_UNKNOWN; | |
2099 | c->writecombine = _CACHE_UNCACHED; | |
2100 | ||
2101 | c->fpu_csr31 = FPU_CSR_RN; | |
2102 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
2103 | ||
2104 | c->processor_id = read_c0_prid(); | |
2105 | switch (c->processor_id & PRID_COMP_MASK) { | |
2106 | case PRID_COMP_LEGACY: | |
2107 | cpu_probe_legacy(c, cpu); | |
2108 | break; | |
2109 | case PRID_COMP_MIPS: | |
2110 | cpu_probe_mips(c, cpu); | |
2111 | break; | |
2112 | case PRID_COMP_ALCHEMY: | |
2113 | cpu_probe_alchemy(c, cpu); | |
2114 | break; | |
2115 | case PRID_COMP_SIBYTE: | |
2116 | cpu_probe_sibyte(c, cpu); | |
2117 | break; | |
2118 | case PRID_COMP_BROADCOM: | |
2119 | cpu_probe_broadcom(c, cpu); | |
2120 | break; | |
2121 | case PRID_COMP_SANDCRAFT: | |
2122 | cpu_probe_sandcraft(c, cpu); | |
2123 | break; | |
2124 | case PRID_COMP_NXP: | |
2125 | cpu_probe_nxp(c, cpu); | |
2126 | break; | |
2127 | case PRID_COMP_CAVIUM: | |
2128 | cpu_probe_cavium(c, cpu); | |
2129 | break; | |
2130 | case PRID_COMP_LOONGSON: | |
2131 | cpu_probe_loongson(c, cpu); | |
2132 | break; | |
2133 | case PRID_COMP_INGENIC_D0: | |
2134 | case PRID_COMP_INGENIC_D1: | |
2135 | case PRID_COMP_INGENIC_E1: | |
2136 | cpu_probe_ingenic(c, cpu); | |
2137 | break; | |
2138 | case PRID_COMP_NETLOGIC: | |
2139 | cpu_probe_netlogic(c, cpu); | |
2140 | break; | |
2141 | } | |
2142 | ||
2143 | BUG_ON(!__cpu_name[cpu]); | |
2144 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
2145 | ||
2146 | /* | |
2147 | * Platform code can force the cpu type to optimize code | |
2148 | * generation. In that case be sure the cpu type is correctly | |
2149 | * manually setup otherwise it could trigger some nasty bugs. | |
2150 | */ | |
2151 | BUG_ON(current_cpu_type() != c->cputype); | |
2152 | ||
2153 | if (cpu_has_rixi) { | |
2154 | /* Enable the RIXI exceptions */ | |
2155 | set_c0_pagegrain(PG_IEC); | |
2156 | back_to_back_c0_hazard(); | |
2157 | /* Verify the IEC bit is set */ | |
2158 | if (read_c0_pagegrain() & PG_IEC) | |
2159 | c->options |= MIPS_CPU_RIXIEX; | |
2160 | } | |
2161 | ||
2162 | if (mips_fpu_disabled) | |
2163 | c->options &= ~MIPS_CPU_FPU; | |
2164 | ||
2165 | if (mips_dsp_disabled) | |
2166 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); | |
2167 | ||
2168 | if (mips_htw_disabled) { | |
2169 | c->options &= ~MIPS_CPU_HTW; | |
2170 | write_c0_pwctl(read_c0_pwctl() & | |
2171 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
2172 | } | |
2173 | ||
2174 | if (c->options & MIPS_CPU_FPU) | |
2175 | cpu_set_fpu_opts(c); | |
2176 | else | |
2177 | cpu_set_nofpu_opts(c); | |
2178 | ||
2179 | if (cpu_has_bp_ghist) | |
2180 | write_c0_r10k_diag(read_c0_r10k_diag() | | |
2181 | R10K_DIAG_E_GHIST); | |
2182 | ||
2183 | if (cpu_has_mips_r2_r6) { | |
2184 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
2185 | /* R2 has Performance Counter Interrupt indicator */ | |
2186 | c->options |= MIPS_CPU_PCI; | |
2187 | } | |
2188 | else | |
2189 | c->srsets = 1; | |
2190 | ||
2191 | if (cpu_has_mips_r6) | |
2192 | elf_hwcap |= HWCAP_MIPS_R6; | |
2193 | ||
2194 | if (cpu_has_msa) { | |
2195 | c->msa_id = cpu_get_msa_id(); | |
2196 | WARN(c->msa_id & MSA_IR_WRPF, | |
2197 | "Vector register partitioning unimplemented!"); | |
2198 | elf_hwcap |= HWCAP_MIPS_MSA; | |
2199 | } | |
2200 | ||
2201 | if (cpu_has_mips16) | |
2202 | elf_hwcap |= HWCAP_MIPS_MIPS16; | |
2203 | ||
2204 | if (cpu_has_mdmx) | |
2205 | elf_hwcap |= HWCAP_MIPS_MDMX; | |
2206 | ||
2207 | if (cpu_has_mips3d) | |
2208 | elf_hwcap |= HWCAP_MIPS_MIPS3D; | |
2209 | ||
2210 | if (cpu_has_smartmips) | |
2211 | elf_hwcap |= HWCAP_MIPS_SMARTMIPS; | |
2212 | ||
2213 | if (cpu_has_dsp) | |
2214 | elf_hwcap |= HWCAP_MIPS_DSP; | |
2215 | ||
2216 | if (cpu_has_dsp2) | |
2217 | elf_hwcap |= HWCAP_MIPS_DSP2; | |
2218 | ||
2219 | if (cpu_has_dsp3) | |
2220 | elf_hwcap |= HWCAP_MIPS_DSP3; | |
2221 | ||
2222 | if (cpu_has_mips16e2) | |
2223 | elf_hwcap |= HWCAP_MIPS_MIPS16E2; | |
2224 | ||
2225 | if (cpu_has_loongson_mmi) | |
2226 | elf_hwcap |= HWCAP_LOONGSON_MMI; | |
2227 | ||
2228 | if (cpu_has_loongson_ext) | |
2229 | elf_hwcap |= HWCAP_LOONGSON_EXT; | |
2230 | ||
2231 | if (cpu_has_loongson_ext2) | |
2232 | elf_hwcap |= HWCAP_LOONGSON_EXT2; | |
2233 | ||
2234 | if (cpu_has_vz) | |
2235 | cpu_probe_vz(c); | |
2236 | ||
2237 | cpu_probe_vmbits(c); | |
2238 | ||
2239 | #ifdef CONFIG_64BIT | |
2240 | if (cpu == 0) | |
2241 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
2242 | #endif | |
2243 | } | |
2244 | ||
2245 | void cpu_report(void) | |
2246 | { | |
2247 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
2248 | ||
2249 | pr_info("CPU%d revision is: %08x (%s)\n", | |
2250 | smp_processor_id(), c->processor_id, cpu_name_string()); | |
2251 | if (c->options & MIPS_CPU_FPU) | |
2252 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); | |
2253 | if (cpu_has_msa) | |
2254 | pr_info("MSA revision is: %08x\n", c->msa_id); | |
2255 | } | |
2256 | ||
2257 | void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) | |
2258 | { | |
2259 | /* Ensure the core number fits in the field */ | |
2260 | WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> | |
2261 | MIPS_GLOBALNUMBER_CLUSTER_SHF)); | |
2262 | ||
2263 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; | |
2264 | cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; | |
2265 | } | |
2266 | ||
2267 | void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) | |
2268 | { | |
2269 | /* Ensure the core number fits in the field */ | |
2270 | WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); | |
2271 | ||
2272 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; | |
2273 | cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; | |
2274 | } | |
2275 | ||
2276 | void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) | |
2277 | { | |
2278 | /* Ensure the VP(E) ID fits in the field */ | |
2279 | WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); | |
2280 | ||
2281 | /* Ensure we're not using VP(E)s without support */ | |
2282 | WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && | |
2283 | !IS_ENABLED(CONFIG_CPU_MIPSR6)); | |
2284 | ||
2285 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; | |
2286 | cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; | |
2287 | } |