[mirror_ubuntu-zesty-kernel.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
 */

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0

enum opcode {
	insn_invalid,
	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
	insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
	insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
	insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
	insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv,
	insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr,
	insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield,
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

static inline u32 build_rs(u32 arg)
{
	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline u32 build_rt(u32 arg)
{
	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline u32 build_rd(u32 arg)
{
	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline u32 build_re(u32 arg)
{
	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline u32 build_simm(s32 arg)
{
	WARN(arg > 0x7fff || arg < -0x8000,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline u32 build_uimm(u32 arg)
{
	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline u32 build_scimm(u32 arg)
{
	WARN(arg & ~SCIMM_MASK,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline u32 build_func(u32 arg)
{
	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline u32 build_set(u32 arg)
{
	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

static void build_insn(u32 **buf, enum opcode opc, ...);

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u2u1(op)					\
Ip_u3u2u1(op)						\
{							\
	build_insn(buf, insn##op, c, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32u3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbdu3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u1u2(_divu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins)
I_u1(_j)
I_u1(_jal)
I_u2u1(_jalr)
I_u1(_jr)
I_u2s3u1(_ld)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u3u1u2(_or)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u3u2u1(_sllv)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u3u2u1(_srlv)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_u1(_sync)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u1(_wait);
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1(_yield)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
I_u3u1u2(_lwx)
I_u3u1u2(_ldx)

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#include <asm/octeon/octeon.h>
void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
			    unsigned int c)
{
	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
		/*
		 * As per erratum Core-14449, replace prefetches 0-4,
		 * 6-24 with 'pref 28'.
		 */
		build_insn(buf, insn_pref, c, 28, b);
	else
		build_insn(buf, insn_pref, c, a, b);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
#else
I_u2s3u1(_pref)
#endif

/* Handle labels. */
void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));

int ISAFUNC(uasm_in_compat_space_p)(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));

static int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int ISAFUNC(uasm_rel_hi)(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));

int ISAFUNC(uasm_rel_lo)(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));

void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
{
	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
		ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
		if (ISAFUNC(uasm_rel_hi(addr))) {
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_hi)(addr));
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
		} else
			ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
	} else
		ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));

void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
{
	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	if (ISAFUNC(uasm_rel_lo(addr))) {
		if (!ISAFUNC(uasm_in_compat_space_p)(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
		else
			ISAFUNC(uasm_i_addiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
	}
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));

/* Handle relocations. */
void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));

static inline void __resolve_relocs(struct uasm_reloc *rel,
				    struct uasm_label *lab);

void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
				  struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));

void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
			       long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));

void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
			       long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));

void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
				u32 *first, u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	ISAFUNC(uasm_move_relocs(rel, first, end, off));
	ISAFUNC(uasm_move_labels(lab, first, end, off));
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));

int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));

/* Convenience functions for labeled branches. */
void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bltz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));

void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_b)(p, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));

void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
			  unsigned int r2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));

void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));

void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));

void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
			  unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));

void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bnez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));

void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));

void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));

void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));

void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
Commit	Line	Data
	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
	13	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
	14	*/
	15
	16	enum fields {
	17	RS = 0x001,
	18	RT = 0x002,
	19	RD = 0x004,
	20	RE = 0x008,
	21	SIMM = 0x010,
	22	UIMM = 0x020,
	23	BIMM = 0x040,
	24	JIMM = 0x080,
	25	FUNC = 0x100,
	26	SET = 0x200,
	27	SCIMM = 0x400
	28	};
	29
	30	#define OP_MASK 0x3f
	31	#define OP_SH 26
	32	#define RD_MASK 0x1f
	33	#define RD_SH 11
	34	#define RE_MASK 0x1f
	35	#define RE_SH 6
	36	#define IMM_MASK 0xffff
	37	#define IMM_SH 0
	38	#define JIMM_MASK 0x3ffffff
	39	#define JIMM_SH 0
	40	#define FUNC_MASK 0x3f
	41	#define FUNC_SH 0
	42	#define SET_MASK 0x7
	43	#define SET_SH 0
	44
	45	enum opcode {
	46	insn_invalid,
	47	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	48	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	49	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
	50	insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
	51	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
	52	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
	53	insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
	54	insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
	55	insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv,
	56	insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr,
	57	insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield,
	58	};
	59
	60	struct insn {
	61	enum opcode opcode;
	62	u32 match;
	63	enum fields fields;
	64	};
	65
	66	static inline u32 build_rs(u32 arg)
	67	{
	68	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	69
	70	return (arg & RS_MASK) << RS_SH;
	71	}
	72
	73	static inline u32 build_rt(u32 arg)
	74	{
	75	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	76
	77	return (arg & RT_MASK) << RT_SH;
	78	}
	79
	80	static inline u32 build_rd(u32 arg)
	81	{
	82	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	83
	84	return (arg & RD_MASK) << RD_SH;
	85	}
	86
	87	static inline u32 build_re(u32 arg)
	88	{
	89	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	90
	91	return (arg & RE_MASK) << RE_SH;
	92	}
	93
	94	static inline u32 build_simm(s32 arg)
	95	{
	96	WARN(arg > 0x7fff \|\| arg < -0x8000,
	97	KERN_WARNING "Micro-assembler field overflow\n");
	98
	99	return arg & 0xffff;
	100	}
	101
	102	static inline u32 build_uimm(u32 arg)
	103	{
	104	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	105
	106	return arg & IMM_MASK;
	107	}
	108
	109	static inline u32 build_scimm(u32 arg)
	110	{
	111	WARN(arg & ~SCIMM_MASK,
	112	KERN_WARNING "Micro-assembler field overflow\n");
	113
	114	return (arg & SCIMM_MASK) << SCIMM_SH;
	115	}
	116
	117	static inline u32 build_func(u32 arg)
	118	{
	119	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	120
	121	return arg & FUNC_MASK;
	122	}
	123
	124	static inline u32 build_set(u32 arg)
	125	{
	126	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
	127
	128	return arg & SET_MASK;
	129	}
	130
	131	static void build_insn(u32 **buf, enum opcode opc, ...);
	132
	133	#define I_u1u2u3(op) \
	134	Ip_u1u2u3(op) \
	135	{ \
	136	build_insn(buf, insn##op, a, b, c); \
	137	} \
	138	UASM_EXPORT_SYMBOL(uasm_i##op);
	139
	140	#define I_u2u1u3(op) \
	141	Ip_u2u1u3(op) \
	142	{ \
	143	build_insn(buf, insn##op, b, a, c); \
	144	} \
	145	UASM_EXPORT_SYMBOL(uasm_i##op);
	146
	147	#define I_u3u2u1(op) \
	148	Ip_u3u2u1(op) \
	149	{ \
	150	build_insn(buf, insn##op, c, b, a); \
	151	} \
	152	UASM_EXPORT_SYMBOL(uasm_i##op);
	153
	154	#define I_u3u1u2(op) \
	155	Ip_u3u1u2(op) \
	156	{ \
	157	build_insn(buf, insn##op, b, c, a); \
	158	} \
	159	UASM_EXPORT_SYMBOL(uasm_i##op);
	160
	161	#define I_u1u2s3(op) \
	162	Ip_u1u2s3(op) \
	163	{ \
	164	build_insn(buf, insn##op, a, b, c); \
	165	} \
	166	UASM_EXPORT_SYMBOL(uasm_i##op);
	167
	168	#define I_u2s3u1(op) \
	169	Ip_u2s3u1(op) \
	170	{ \
	171	build_insn(buf, insn##op, c, a, b); \
	172	} \
	173	UASM_EXPORT_SYMBOL(uasm_i##op);
	174
	175	#define I_u2u1s3(op) \
	176	Ip_u2u1s3(op) \
	177	{ \
	178	build_insn(buf, insn##op, b, a, c); \
	179	} \
	180	UASM_EXPORT_SYMBOL(uasm_i##op);
	181
	182	#define I_u2u1msbu3(op) \
	183	Ip_u2u1msbu3(op) \
	184	{ \
	185	build_insn(buf, insn##op, b, a, c+d-1, c); \
	186	} \
	187	UASM_EXPORT_SYMBOL(uasm_i##op);
	188
	189	#define I_u2u1msb32u3(op) \
	190	Ip_u2u1msbu3(op) \
	191	{ \
	192	build_insn(buf, insn##op, b, a, c+d-33, c); \
	193	} \
	194	UASM_EXPORT_SYMBOL(uasm_i##op);
	195
	196	#define I_u2u1msbdu3(op) \
	197	Ip_u2u1msbu3(op) \
	198	{ \
	199	build_insn(buf, insn##op, b, a, d-1, c); \
	200	} \
	201	UASM_EXPORT_SYMBOL(uasm_i##op);
	202
	203	#define I_u1u2(op) \
	204	Ip_u1u2(op) \
	205	{ \
	206	build_insn(buf, insn##op, a, b); \
	207	} \
	208	UASM_EXPORT_SYMBOL(uasm_i##op);
	209
	210	#define I_u2u1(op) \
	211	Ip_u1u2(op) \
	212	{ \
	213	build_insn(buf, insn##op, b, a); \
	214	} \
	215	UASM_EXPORT_SYMBOL(uasm_i##op);
	216
	217	#define I_u1s2(op) \
	218	Ip_u1s2(op) \
	219	{ \
	220	build_insn(buf, insn##op, a, b); \
	221	} \
	222	UASM_EXPORT_SYMBOL(uasm_i##op);
	223
	224	#define I_u1(op) \
	225	Ip_u1(op) \
	226	{ \
	227	build_insn(buf, insn##op, a); \
	228	} \
	229	UASM_EXPORT_SYMBOL(uasm_i##op);
	230
	231	#define I_0(op) \
	232	Ip_0(op) \
	233	{ \
	234	build_insn(buf, insn##op); \
	235	} \
	236	UASM_EXPORT_SYMBOL(uasm_i##op);
	237
	238	I_u2u1s3(_addiu)
	239	I_u3u1u2(_addu)
	240	I_u2u1u3(_andi)
	241	I_u3u1u2(_and)
	242	I_u1u2s3(_beq)
	243	I_u1u2s3(_beql)
	244	I_u1s2(_bgez)
	245	I_u1s2(_bgezl)
	246	I_u1s2(_bltz)
	247	I_u1s2(_bltzl)
	248	I_u1u2s3(_bne)
	249	I_u2s3u1(_cache)
	250	I_u1u2u3(_dmfc0)
	251	I_u1u2u3(_dmtc0)
	252	I_u2u1s3(_daddiu)
	253	I_u3u1u2(_daddu)
	254	I_u1u2(_divu)
	255	I_u2u1u3(_dsll)
	256	I_u2u1u3(_dsll32)
	257	I_u2u1u3(_dsra)
	258	I_u2u1u3(_dsrl)
	259	I_u2u1u3(_dsrl32)
	260	I_u2u1u3(_drotr)
	261	I_u2u1u3(_drotr32)
	262	I_u3u1u2(_dsubu)
	263	I_0(_eret)
	264	I_u2u1msbdu3(_ext)
	265	I_u2u1msbu3(_ins)
	266	I_u1(_j)
	267	I_u1(_jal)
	268	I_u2u1(_jalr)
	269	I_u1(_jr)
	270	I_u2s3u1(_ld)
	271	I_u2s3u1(_ll)
	272	I_u2s3u1(_lld)
	273	I_u1s2(_lui)
	274	I_u2s3u1(_lw)
	275	I_u1u2u3(_mfc0)
	276	I_u1u2u3(_mtc0)
	277	I_u2u1u3(_ori)
	278	I_u3u1u2(_or)
	279	I_0(_rfe)
	280	I_u2s3u1(_sc)
	281	I_u2s3u1(_scd)
	282	I_u2s3u1(_sd)
	283	I_u2u1u3(_sll)
	284	I_u3u2u1(_sllv)
	285	I_u2u1u3(_sra)
	286	I_u2u1u3(_srl)
	287	I_u3u2u1(_srlv)
	288	I_u2u1u3(_rotr)
	289	I_u3u1u2(_subu)
	290	I_u2s3u1(_sw)
	291	I_u1(_sync)
	292	I_0(_tlbp)
	293	I_0(_tlbr)
	294	I_0(_tlbwi)
	295	I_0(_tlbwr)
	296	I_u1(_wait);
	297	I_u3u1u2(_xor)
	298	I_u2u1u3(_xori)
	299	I_u2u1(_yield)
	300	I_u2u1msbu3(_dins);
	301	I_u2u1msb32u3(_dinsm);
	302	I_u1(_syscall);
	303	I_u1u2s3(_bbit0);
	304	I_u1u2s3(_bbit1);
	305	I_u3u1u2(_lwx)
	306	I_u3u1u2(_ldx)
	307
	308	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	309	#include <asm/octeon/octeon.h>
	310	void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
	311	unsigned int c)
	312	{
	313	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
	314	/*
	315	* As per erratum Core-14449, replace prefetches 0-4,
	316	* 6-24 with 'pref 28'.
	317	*/
	318	build_insn(buf, insn_pref, c, 28, b);
	319	else
	320	build_insn(buf, insn_pref, c, a, b);
	321	}
	322	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
	323	#else
	324	I_u2s3u1(_pref)
	325	#endif
	326
	327	/* Handle labels. */
	328	void ISAFUNC(uasm_build_label)(struct uasm_label *lab, u32 addr, int lid)
	329	{
	330	(*lab)->addr = addr;
	331	(*lab)->lab = lid;
	332	(*lab)++;
	333	}
	334	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
	335
	336	int ISAFUNC(uasm_in_compat_space_p)(long addr)
	337	{
	338	/* Is this address in 32bit compat space? */
	339	#ifdef CONFIG_64BIT
	340	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	341	#else
	342	return 1;
	343	#endif
	344	}
	345	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
	346
	347	static int uasm_rel_highest(long val)
	348	{
	349	#ifdef CONFIG_64BIT
	350	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	351	#else
	352	return 0;
	353	#endif
	354	}
	355
	356	static int uasm_rel_higher(long val)
	357	{
	358	#ifdef CONFIG_64BIT
	359	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	360	#else
	361	return 0;
	362	#endif
	363	}
	364
	365	int ISAFUNC(uasm_rel_hi)(long val)
	366	{
	367	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	368	}
	369	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
	370
	371	int ISAFUNC(uasm_rel_lo)(long val)
	372	{
	373	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	374	}
	375	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
	376
	377	void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
	378	{
	379	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
	380	ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
	381	if (uasm_rel_higher(addr))
	382	ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
	383	if (ISAFUNC(uasm_rel_hi(addr))) {
	384	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
	385	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	386	ISAFUNC(uasm_rel_hi)(addr));
	387	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
	388	} else
	389	ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
	390	} else
	391	ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
	392	}
	393	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
	394
	395	void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
	396	{
	397	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	398	if (ISAFUNC(uasm_rel_lo(addr))) {
	399	if (!ISAFUNC(uasm_in_compat_space_p)(addr))
	400	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	401	ISAFUNC(uasm_rel_lo(addr)));
	402	else
	403	ISAFUNC(uasm_i_addiu)(buf, rs, rs,
	404	ISAFUNC(uasm_rel_lo(addr)));
	405	}
	406	}
	407	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
	408
	409	/* Handle relocations. */
	410	void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc *rel, u32 addr, int lid)
	411	{
	412	(*rel)->addr = addr;
	413	(*rel)->type = R_MIPS_PC16;
	414	(*rel)->lab = lid;
	415	(*rel)++;
	416	}
	417	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
	418
	419	static inline void __resolve_relocs(struct uasm_reloc *rel,
	420	struct uasm_label *lab);
	421
	422	void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
	423	struct uasm_label *lab)
	424	{
	425	struct uasm_label *l;
	426
	427	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	428	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	429	if (rel->lab == l->lab)
	430	__resolve_relocs(rel, l);
	431	}
	432	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
	433
	434	void ISAFUNC(uasm_move_relocs)(struct uasm_reloc rel, u32 first, u32 *end,
	435	long off)
	436	{
	437	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	438	if (rel->addr >= first && rel->addr < end)
	439	rel->addr += off;
	440	}
	441	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
	442
	443	void ISAFUNC(uasm_move_labels)(struct uasm_label lab, u32 first, u32 *end,
	444	long off)
	445	{
	446	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	447	if (lab->addr >= first && lab->addr < end)
	448	lab->addr += off;
	449	}
	450	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
	451
	452	void ISAFUNC(uasm_copy_handler)(struct uasm_reloc rel, struct uasm_label lab,
	453	u32 first, u32 end, u32 *target)
	454	{
	455	long off = (long)(target - first);
	456
	457	memcpy(target, first, (end - first) * sizeof(u32));
	458
	459	ISAFUNC(uasm_move_relocs(rel, first, end, off));
	460	ISAFUNC(uasm_move_labels(lab, first, end, off));
	461	}
	462	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
	463
	464	int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc rel, u32 addr)
	465	{
	466	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	467	if (rel->addr == addr
	468	&& (rel->type == R_MIPS_PC16
	469	\|\| rel->type == R_MIPS_26))
	470	return 1;
	471	}
	472
	473	return 0;
	474	}
	475	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
	476
	477	/* Convenience functions for labeled branches. */
	478	void ISAFUNC(uasm_il_bltz)(u32 p, struct uasm_reloc r, unsigned int reg,
	479	int lid)
	480	{
	481	uasm_r_mips_pc16(r, *p, lid);
	482	ISAFUNC(uasm_i_bltz)(p, reg, 0);
	483	}
	484	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
	485
	486	void ISAFUNC(uasm_il_b)(u32 p, struct uasm_reloc r, int lid)
	487	{
	488	uasm_r_mips_pc16(r, *p, lid);
	489	ISAFUNC(uasm_i_b)(p, 0);
	490	}
	491	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
	492
	493	void ISAFUNC(uasm_il_beq)(u32 p, struct uasm_reloc r, unsigned int r1,
	494	unsigned int r2, int lid)
	495	{
	496	uasm_r_mips_pc16(r, *p, lid);
	497	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
	498	}
	499	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
	500
	501	void ISAFUNC(uasm_il_beqz)(u32 p, struct uasm_reloc r, unsigned int reg,
	502	int lid)
	503	{
	504	uasm_r_mips_pc16(r, *p, lid);
	505	ISAFUNC(uasm_i_beqz)(p, reg, 0);
	506	}
	507	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
	508
	509	void ISAFUNC(uasm_il_beqzl)(u32 p, struct uasm_reloc r, unsigned int reg,
	510	int lid)
	511	{
	512	uasm_r_mips_pc16(r, *p, lid);
	513	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
	514	}
	515	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
	516
	517	void ISAFUNC(uasm_il_bne)(u32 p, struct uasm_reloc r, unsigned int reg1,
	518	unsigned int reg2, int lid)
	519	{
	520	uasm_r_mips_pc16(r, *p, lid);
	521	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
	522	}
	523	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
	524
	525	void ISAFUNC(uasm_il_bnez)(u32 p, struct uasm_reloc r, unsigned int reg,
	526	int lid)
	527	{
	528	uasm_r_mips_pc16(r, *p, lid);
	529	ISAFUNC(uasm_i_bnez)(p, reg, 0);
	530	}
	531	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
	532
	533	void ISAFUNC(uasm_il_bgezl)(u32 p, struct uasm_reloc r, unsigned int reg,
	534	int lid)
	535	{
	536	uasm_r_mips_pc16(r, *p, lid);
	537	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
	538	}
	539	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
	540
	541	void ISAFUNC(uasm_il_bgez)(u32 p, struct uasm_reloc r, unsigned int reg,
	542	int lid)
	543	{
	544	uasm_r_mips_pc16(r, *p, lid);
	545	ISAFUNC(uasm_i_bgez)(p, reg, 0);
	546	}
	547	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
	548
	549	void ISAFUNC(uasm_il_bbit0)(u32 p, struct uasm_reloc r, unsigned int reg,
	550	unsigned int bit, int lid)
	551	{
	552	uasm_r_mips_pc16(r, *p, lid);
	553	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
	554	}
	555	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
	556
	557	void ISAFUNC(uasm_il_bbit1)(u32 p, struct uasm_reloc r, unsigned int reg,
	558	unsigned int bit, int lid)
	559	{
	560	uasm_r_mips_pc16(r, *p, lid);
	561	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
	562	}
	563	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));