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1 | /* | |
2 | * Disassemble s390 instructions. | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
5 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), | |
6 | */ | |
7 | ||
8 | #include <linux/sched.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/string.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/timer.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/kallsyms.h> | |
21 | #include <linux/reboot.h> | |
22 | #include <linux/kprobes.h> | |
23 | #include <linux/kdebug.h> | |
24 | ||
25 | #include <linux/uaccess.h> | |
26 | #include <asm/dis.h> | |
27 | #include <asm/io.h> | |
28 | #include <linux/atomic.h> | |
29 | #include <asm/cpcmd.h> | |
30 | #include <asm/lowcore.h> | |
31 | #include <asm/debug.h> | |
32 | #include <asm/irq.h> | |
33 | ||
34 | enum { | |
35 | UNUSED, /* Indicates the end of the operand list */ | |
36 | R_8, /* GPR starting at position 8 */ | |
37 | R_12, /* GPR starting at position 12 */ | |
38 | R_16, /* GPR starting at position 16 */ | |
39 | R_20, /* GPR starting at position 20 */ | |
40 | R_24, /* GPR starting at position 24 */ | |
41 | R_28, /* GPR starting at position 28 */ | |
42 | R_32, /* GPR starting at position 32 */ | |
43 | F_8, /* FPR starting at position 8 */ | |
44 | F_12, /* FPR starting at position 12 */ | |
45 | F_16, /* FPR starting at position 16 */ | |
46 | F_20, /* FPR starting at position 16 */ | |
47 | F_24, /* FPR starting at position 24 */ | |
48 | F_28, /* FPR starting at position 28 */ | |
49 | F_32, /* FPR starting at position 32 */ | |
50 | A_8, /* Access reg. starting at position 8 */ | |
51 | A_12, /* Access reg. starting at position 12 */ | |
52 | A_24, /* Access reg. starting at position 24 */ | |
53 | A_28, /* Access reg. starting at position 28 */ | |
54 | C_8, /* Control reg. starting at position 8 */ | |
55 | C_12, /* Control reg. starting at position 12 */ | |
56 | V_8, /* Vector reg. starting at position 8, extension bit at 36 */ | |
57 | V_12, /* Vector reg. starting at position 12, extension bit at 37 */ | |
58 | V_16, /* Vector reg. starting at position 16, extension bit at 38 */ | |
59 | V_32, /* Vector reg. starting at position 32, extension bit at 39 */ | |
60 | W_12, /* Vector reg. at bit 12, extension at bit 37, used as index */ | |
61 | B_16, /* Base register starting at position 16 */ | |
62 | B_32, /* Base register starting at position 32 */ | |
63 | X_12, /* Index register starting at position 12 */ | |
64 | D_20, /* Displacement starting at position 20 */ | |
65 | D_36, /* Displacement starting at position 36 */ | |
66 | D20_20, /* 20 bit displacement starting at 20 */ | |
67 | L4_8, /* 4 bit length starting at position 8 */ | |
68 | L4_12, /* 4 bit length starting at position 12 */ | |
69 | L8_8, /* 8 bit length starting at position 8 */ | |
70 | U4_8, /* 4 bit unsigned value starting at 8 */ | |
71 | U4_12, /* 4 bit unsigned value starting at 12 */ | |
72 | U4_16, /* 4 bit unsigned value starting at 16 */ | |
73 | U4_20, /* 4 bit unsigned value starting at 20 */ | |
74 | U4_24, /* 4 bit unsigned value starting at 24 */ | |
75 | U4_28, /* 4 bit unsigned value starting at 28 */ | |
76 | U4_32, /* 4 bit unsigned value starting at 32 */ | |
77 | U4_36, /* 4 bit unsigned value starting at 36 */ | |
78 | U8_8, /* 8 bit unsigned value starting at 8 */ | |
79 | U8_16, /* 8 bit unsigned value starting at 16 */ | |
80 | U8_24, /* 8 bit unsigned value starting at 24 */ | |
81 | U8_32, /* 8 bit unsigned value starting at 32 */ | |
82 | I8_8, /* 8 bit signed value starting at 8 */ | |
83 | I8_16, /* 8 bit signed value starting at 16 */ | |
84 | I8_24, /* 8 bit signed value starting at 24 */ | |
85 | I8_32, /* 8 bit signed value starting at 32 */ | |
86 | J12_12, /* PC relative offset at 12 */ | |
87 | I16_16, /* 16 bit signed value starting at 16 */ | |
88 | I16_32, /* 32 bit signed value starting at 16 */ | |
89 | U16_16, /* 16 bit unsigned value starting at 16 */ | |
90 | U16_32, /* 32 bit unsigned value starting at 16 */ | |
91 | J16_16, /* PC relative jump offset at 16 */ | |
92 | J16_32, /* PC relative offset at 16 */ | |
93 | I24_24, /* 24 bit signed value starting at 24 */ | |
94 | J32_16, /* PC relative long offset at 16 */ | |
95 | I32_16, /* 32 bit signed value starting at 16 */ | |
96 | U32_16, /* 32 bit unsigned value starting at 16 */ | |
97 | M_16, /* 4 bit optional mask starting at 16 */ | |
98 | M_20, /* 4 bit optional mask starting at 20 */ | |
99 | M_24, /* 4 bit optional mask starting at 24 */ | |
100 | M_28, /* 4 bit optional mask starting at 28 */ | |
101 | M_32, /* 4 bit optional mask starting at 32 */ | |
102 | RO_28, /* optional GPR starting at position 28 */ | |
103 | }; | |
104 | ||
105 | /* | |
106 | * Enumeration of the different instruction formats. | |
107 | * For details consult the principles of operation. | |
108 | */ | |
109 | enum { | |
110 | INSTR_INVALID, | |
111 | INSTR_E, | |
112 | INSTR_IE_UU, | |
113 | INSTR_MII_UPI, | |
114 | INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, | |
115 | INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, | |
116 | INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, | |
117 | INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, | |
118 | INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, | |
119 | INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, | |
120 | INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, | |
121 | INSTR_RRE_RR, INSTR_RRE_RR_OPT, | |
122 | INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, | |
123 | INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR, | |
124 | INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR, | |
125 | INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF, | |
126 | INSTR_RRF_UUFR, INSTR_RRF_UURF, | |
127 | INSTR_RRR_F0FF, INSTR_RRS_RRRDU, | |
128 | INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, | |
129 | INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, | |
130 | INSTR_RSI_RRP, | |
131 | INSTR_RSL_LRDFU, INSTR_RSL_R0RD, | |
132 | INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, | |
133 | INSTR_RSY_RDRM, INSTR_RSY_RMRD, | |
134 | INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, | |
135 | INSTR_RS_RURD, | |
136 | INSTR_RXE_FRRD, INSTR_RXE_RRRD, INSTR_RXE_RRRDM, | |
137 | INSTR_RXF_FRRDF, | |
138 | INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, | |
139 | INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, | |
140 | INSTR_SIL_RDI, INSTR_SIL_RDU, | |
141 | INSTR_SIY_IRD, INSTR_SIY_URD, | |
142 | INSTR_SI_URD, | |
143 | INSTR_SMI_U0RDP, | |
144 | INSTR_SSE_RDRD, | |
145 | INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, | |
146 | INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, | |
147 | INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, | |
148 | INSTR_S_00, INSTR_S_RD, | |
149 | INSTR_VRI_V0IM, INSTR_VRI_V0I0, INSTR_VRI_V0IIM, INSTR_VRI_VVIM, | |
150 | INSTR_VRI_VVV0IM, INSTR_VRI_VVV0I0, INSTR_VRI_VVIMM, | |
151 | INSTR_VRR_VV00MMM, INSTR_VRR_VV000MM, INSTR_VRR_VV0000M, | |
152 | INSTR_VRR_VV00000, INSTR_VRR_VVV0M0M, INSTR_VRR_VV00M0M, | |
153 | INSTR_VRR_VVV000M, INSTR_VRR_VVV000V, INSTR_VRR_VVV0000, | |
154 | INSTR_VRR_VVV0MMM, INSTR_VRR_VVV00MM, INSTR_VRR_VVVMM0V, | |
155 | INSTR_VRR_VVVM0MV, INSTR_VRR_VVVM00V, INSTR_VRR_VRR0000, | |
156 | INSTR_VRS_VVRDM, INSTR_VRS_VVRD0, INSTR_VRS_VRRDM, INSTR_VRS_VRRD0, | |
157 | INSTR_VRS_RVRDM, | |
158 | INSTR_VRV_VVRDM, INSTR_VRV_VWRDM, | |
159 | INSTR_VRX_VRRDM, INSTR_VRX_VRRD0, | |
160 | }; | |
161 | ||
162 | static const struct s390_operand operands[] = | |
163 | { | |
164 | [UNUSED] = { 0, 0, 0 }, | |
165 | [R_8] = { 4, 8, OPERAND_GPR }, | |
166 | [R_12] = { 4, 12, OPERAND_GPR }, | |
167 | [R_16] = { 4, 16, OPERAND_GPR }, | |
168 | [R_20] = { 4, 20, OPERAND_GPR }, | |
169 | [R_24] = { 4, 24, OPERAND_GPR }, | |
170 | [R_28] = { 4, 28, OPERAND_GPR }, | |
171 | [R_32] = { 4, 32, OPERAND_GPR }, | |
172 | [F_8] = { 4, 8, OPERAND_FPR }, | |
173 | [F_12] = { 4, 12, OPERAND_FPR }, | |
174 | [F_16] = { 4, 16, OPERAND_FPR }, | |
175 | [F_20] = { 4, 16, OPERAND_FPR }, | |
176 | [F_24] = { 4, 24, OPERAND_FPR }, | |
177 | [F_28] = { 4, 28, OPERAND_FPR }, | |
178 | [F_32] = { 4, 32, OPERAND_FPR }, | |
179 | [A_8] = { 4, 8, OPERAND_AR }, | |
180 | [A_12] = { 4, 12, OPERAND_AR }, | |
181 | [A_24] = { 4, 24, OPERAND_AR }, | |
182 | [A_28] = { 4, 28, OPERAND_AR }, | |
183 | [C_8] = { 4, 8, OPERAND_CR }, | |
184 | [C_12] = { 4, 12, OPERAND_CR }, | |
185 | [V_8] = { 4, 8, OPERAND_VR }, | |
186 | [V_12] = { 4, 12, OPERAND_VR }, | |
187 | [V_16] = { 4, 16, OPERAND_VR }, | |
188 | [V_32] = { 4, 32, OPERAND_VR }, | |
189 | [W_12] = { 4, 12, OPERAND_INDEX | OPERAND_VR }, | |
190 | [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, | |
191 | [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, | |
192 | [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, | |
193 | [D_20] = { 12, 20, OPERAND_DISP }, | |
194 | [D_36] = { 12, 36, OPERAND_DISP }, | |
195 | [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, | |
196 | [L4_8] = { 4, 8, OPERAND_LENGTH }, | |
197 | [L4_12] = { 4, 12, OPERAND_LENGTH }, | |
198 | [L8_8] = { 8, 8, OPERAND_LENGTH }, | |
199 | [U4_8] = { 4, 8, 0 }, | |
200 | [U4_12] = { 4, 12, 0 }, | |
201 | [U4_16] = { 4, 16, 0 }, | |
202 | [U4_20] = { 4, 20, 0 }, | |
203 | [U4_24] = { 4, 24, 0 }, | |
204 | [U4_28] = { 4, 28, 0 }, | |
205 | [U4_32] = { 4, 32, 0 }, | |
206 | [U4_36] = { 4, 36, 0 }, | |
207 | [U8_8] = { 8, 8, 0 }, | |
208 | [U8_16] = { 8, 16, 0 }, | |
209 | [U8_24] = { 8, 24, 0 }, | |
210 | [U8_32] = { 8, 32, 0 }, | |
211 | [J12_12] = { 12, 12, OPERAND_PCREL }, | |
212 | [I8_8] = { 8, 8, OPERAND_SIGNED }, | |
213 | [I8_16] = { 8, 16, OPERAND_SIGNED }, | |
214 | [I8_24] = { 8, 24, OPERAND_SIGNED }, | |
215 | [I8_32] = { 8, 32, OPERAND_SIGNED }, | |
216 | [I16_32] = { 16, 32, OPERAND_SIGNED }, | |
217 | [I16_16] = { 16, 16, OPERAND_SIGNED }, | |
218 | [U16_16] = { 16, 16, 0 }, | |
219 | [U16_32] = { 16, 32, 0 }, | |
220 | [J16_16] = { 16, 16, OPERAND_PCREL }, | |
221 | [J16_32] = { 16, 32, OPERAND_PCREL }, | |
222 | [I24_24] = { 24, 24, OPERAND_SIGNED }, | |
223 | [J32_16] = { 32, 16, OPERAND_PCREL }, | |
224 | [I32_16] = { 32, 16, OPERAND_SIGNED }, | |
225 | [U32_16] = { 32, 16, 0 }, | |
226 | [M_16] = { 4, 16, 0 }, | |
227 | [M_20] = { 4, 20, 0 }, | |
228 | [M_24] = { 4, 24, 0 }, | |
229 | [M_28] = { 4, 28, 0 }, | |
230 | [M_32] = { 4, 32, 0 }, | |
231 | [RO_28] = { 4, 28, OPERAND_GPR } | |
232 | }; | |
233 | ||
234 | static const unsigned char formats[][7] = { | |
235 | [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, | |
236 | [INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 }, | |
237 | [INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 }, | |
238 | [INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 }, | |
239 | [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, | |
240 | [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, | |
241 | [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, | |
242 | [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, | |
243 | [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, | |
244 | [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, | |
245 | [INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 }, | |
246 | [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, | |
247 | [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, | |
248 | [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, | |
249 | [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, | |
250 | [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, | |
251 | [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, | |
252 | [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, | |
253 | [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, | |
254 | [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, | |
255 | [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, | |
256 | [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, | |
257 | [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, | |
258 | [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, | |
259 | [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, | |
260 | [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, | |
261 | [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, | |
262 | [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, | |
263 | [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, | |
264 | [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, | |
265 | [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, | |
266 | [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, | |
267 | [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, | |
268 | [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, | |
269 | [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, | |
270 | [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, | |
271 | [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, | |
272 | [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, | |
273 | [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, | |
274 | [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, | |
275 | [INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 }, | |
276 | [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, | |
277 | [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, | |
278 | [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, | |
279 | [INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 }, | |
280 | [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, | |
281 | [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, | |
282 | [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, | |
283 | [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, | |
284 | [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, | |
285 | [INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 }, | |
286 | [INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 }, | |
287 | [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, | |
288 | [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, | |
289 | [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, | |
290 | [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, | |
291 | [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, | |
292 | [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, | |
293 | [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, | |
294 | [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, | |
295 | [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, | |
296 | [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, | |
297 | [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, | |
298 | [INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L4_8,B_16,U4_36,0 }, | |
299 | [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, | |
300 | [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, | |
301 | [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, | |
302 | [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 }, | |
303 | [INSTR_RSY_RMRD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, | |
304 | [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, | |
305 | [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, | |
306 | [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, | |
307 | [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, | |
308 | [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, | |
309 | [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, | |
310 | [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, | |
311 | [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, | |
312 | [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, | |
313 | [INSTR_RXE_RRRDM] = { 0xff, R_8,D_20,X_12,B_16,M_32,0 }, | |
314 | [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, | |
315 | [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, | |
316 | [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, | |
317 | [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, | |
318 | [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, | |
319 | [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, | |
320 | [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, | |
321 | [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, | |
322 | [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, | |
323 | [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, | |
324 | [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, | |
325 | [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, | |
326 | [INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 }, | |
327 | [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, | |
328 | [INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 }, | |
329 | [INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 }, | |
330 | [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, | |
331 | [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, | |
332 | [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, | |
333 | [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, | |
334 | [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, | |
335 | [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, | |
336 | [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, | |
337 | [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, | |
338 | [INSTR_VRI_V0IM] = { 0xff, V_8,I16_16,M_32,0,0,0 }, | |
339 | [INSTR_VRI_V0I0] = { 0xff, V_8,I16_16,0,0,0,0 }, | |
340 | [INSTR_VRI_V0IIM] = { 0xff, V_8,I8_16,I8_24,M_32,0,0 }, | |
341 | [INSTR_VRI_VVIM] = { 0xff, V_8,I16_16,V_12,M_32,0,0 }, | |
342 | [INSTR_VRI_VVV0IM]= { 0xff, V_8,V_12,V_16,I8_24,M_32,0 }, | |
343 | [INSTR_VRI_VVV0I0]= { 0xff, V_8,V_12,V_16,I8_24,0,0 }, | |
344 | [INSTR_VRI_VVIMM] = { 0xff, V_8,V_12,I16_16,M_32,M_28,0 }, | |
345 | [INSTR_VRR_VV00MMM]={ 0xff, V_8,V_12,M_32,M_28,M_24,0 }, | |
346 | [INSTR_VRR_VV000MM]={ 0xff, V_8,V_12,M_32,M_28,0,0 }, | |
347 | [INSTR_VRR_VV0000M]={ 0xff, V_8,V_12,M_32,0,0,0 }, | |
348 | [INSTR_VRR_VV00000]={ 0xff, V_8,V_12,0,0,0,0 }, | |
349 | [INSTR_VRR_VVV0M0M]={ 0xff, V_8,V_12,V_16,M_32,M_24,0 }, | |
350 | [INSTR_VRR_VV00M0M]={ 0xff, V_8,V_12,M_32,M_24,0,0 }, | |
351 | [INSTR_VRR_VVV000M]={ 0xff, V_8,V_12,V_16,M_32,0,0 }, | |
352 | [INSTR_VRR_VVV000V]={ 0xff, V_8,V_12,V_16,V_32,0,0 }, | |
353 | [INSTR_VRR_VVV0000]={ 0xff, V_8,V_12,V_16,0,0,0 }, | |
354 | [INSTR_VRR_VVV0MMM]={ 0xff, V_8,V_12,V_16,M_32,M_28,M_24 }, | |
355 | [INSTR_VRR_VVV00MM]={ 0xff, V_8,V_12,V_16,M_32,M_28,0 }, | |
356 | [INSTR_VRR_VVVMM0V]={ 0xff, V_8,V_12,V_16,V_32,M_20,M_24 }, | |
357 | [INSTR_VRR_VVVM0MV]={ 0xff, V_8,V_12,V_16,V_32,M_28,M_20 }, | |
358 | [INSTR_VRR_VVVM00V]={ 0xff, V_8,V_12,V_16,V_32,M_20,0 }, | |
359 | [INSTR_VRR_VRR0000]={ 0xff, V_8,R_12,R_16,0,0,0 }, | |
360 | [INSTR_VRS_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, | |
361 | [INSTR_VRS_VVRD0] = { 0xff, V_8,V_12,D_20,B_16,0,0 }, | |
362 | [INSTR_VRS_VRRDM] = { 0xff, V_8,R_12,D_20,B_16,M_32,0 }, | |
363 | [INSTR_VRS_VRRD0] = { 0xff, V_8,R_12,D_20,B_16,0,0 }, | |
364 | [INSTR_VRS_RVRDM] = { 0xff, R_8,V_12,D_20,B_16,M_32,0 }, | |
365 | [INSTR_VRV_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, | |
366 | [INSTR_VRV_VWRDM] = { 0xff, V_8,D_20,W_12,B_16,M_32,0 }, | |
367 | [INSTR_VRX_VRRDM] = { 0xff, V_8,D_20,X_12,B_16,M_32,0 }, | |
368 | [INSTR_VRX_VRRD0] = { 0xff, V_8,D_20,X_12,B_16,0,0 }, | |
369 | }; | |
370 | ||
371 | enum { | |
372 | LONG_INSN_ALGHSIK, | |
373 | LONG_INSN_ALHHHR, | |
374 | LONG_INSN_ALHHLR, | |
375 | LONG_INSN_ALHSIK, | |
376 | LONG_INSN_ALSIHN, | |
377 | LONG_INSN_CDFBRA, | |
378 | LONG_INSN_CDGBRA, | |
379 | LONG_INSN_CDGTRA, | |
380 | LONG_INSN_CDLFBR, | |
381 | LONG_INSN_CDLFTR, | |
382 | LONG_INSN_CDLGBR, | |
383 | LONG_INSN_CDLGTR, | |
384 | LONG_INSN_CEFBRA, | |
385 | LONG_INSN_CEGBRA, | |
386 | LONG_INSN_CELFBR, | |
387 | LONG_INSN_CELGBR, | |
388 | LONG_INSN_CFDBRA, | |
389 | LONG_INSN_CFEBRA, | |
390 | LONG_INSN_CFXBRA, | |
391 | LONG_INSN_CGDBRA, | |
392 | LONG_INSN_CGDTRA, | |
393 | LONG_INSN_CGEBRA, | |
394 | LONG_INSN_CGXBRA, | |
395 | LONG_INSN_CGXTRA, | |
396 | LONG_INSN_CLFDBR, | |
397 | LONG_INSN_CLFDTR, | |
398 | LONG_INSN_CLFEBR, | |
399 | LONG_INSN_CLFHSI, | |
400 | LONG_INSN_CLFXBR, | |
401 | LONG_INSN_CLFXTR, | |
402 | LONG_INSN_CLGDBR, | |
403 | LONG_INSN_CLGDTR, | |
404 | LONG_INSN_CLGEBR, | |
405 | LONG_INSN_CLGFRL, | |
406 | LONG_INSN_CLGHRL, | |
407 | LONG_INSN_CLGHSI, | |
408 | LONG_INSN_CLGXBR, | |
409 | LONG_INSN_CLGXTR, | |
410 | LONG_INSN_CLHHSI, | |
411 | LONG_INSN_CXFBRA, | |
412 | LONG_INSN_CXGBRA, | |
413 | LONG_INSN_CXGTRA, | |
414 | LONG_INSN_CXLFBR, | |
415 | LONG_INSN_CXLFTR, | |
416 | LONG_INSN_CXLGBR, | |
417 | LONG_INSN_CXLGTR, | |
418 | LONG_INSN_FIDBRA, | |
419 | LONG_INSN_FIEBRA, | |
420 | LONG_INSN_FIXBRA, | |
421 | LONG_INSN_LDXBRA, | |
422 | LONG_INSN_LEDBRA, | |
423 | LONG_INSN_LEXBRA, | |
424 | LONG_INSN_LLGFAT, | |
425 | LONG_INSN_LLGFRL, | |
426 | LONG_INSN_LLGHRL, | |
427 | LONG_INSN_LLGTAT, | |
428 | LONG_INSN_POPCNT, | |
429 | LONG_INSN_RIEMIT, | |
430 | LONG_INSN_RINEXT, | |
431 | LONG_INSN_RISBGN, | |
432 | LONG_INSN_RISBHG, | |
433 | LONG_INSN_RISBLG, | |
434 | LONG_INSN_SLHHHR, | |
435 | LONG_INSN_SLHHLR, | |
436 | LONG_INSN_TABORT, | |
437 | LONG_INSN_TBEGIN, | |
438 | LONG_INSN_TBEGINC, | |
439 | LONG_INSN_PCISTG, | |
440 | LONG_INSN_MPCIFC, | |
441 | LONG_INSN_STPCIFC, | |
442 | LONG_INSN_PCISTB, | |
443 | LONG_INSN_VPOPCT, | |
444 | LONG_INSN_VERLLV, | |
445 | LONG_INSN_VESRAV, | |
446 | LONG_INSN_VESRLV, | |
447 | LONG_INSN_VSBCBI, | |
448 | LONG_INSN_STCCTM | |
449 | }; | |
450 | ||
451 | static char *long_insn_name[] = { | |
452 | [LONG_INSN_ALGHSIK] = "alghsik", | |
453 | [LONG_INSN_ALHHHR] = "alhhhr", | |
454 | [LONG_INSN_ALHHLR] = "alhhlr", | |
455 | [LONG_INSN_ALHSIK] = "alhsik", | |
456 | [LONG_INSN_ALSIHN] = "alsihn", | |
457 | [LONG_INSN_CDFBRA] = "cdfbra", | |
458 | [LONG_INSN_CDGBRA] = "cdgbra", | |
459 | [LONG_INSN_CDGTRA] = "cdgtra", | |
460 | [LONG_INSN_CDLFBR] = "cdlfbr", | |
461 | [LONG_INSN_CDLFTR] = "cdlftr", | |
462 | [LONG_INSN_CDLGBR] = "cdlgbr", | |
463 | [LONG_INSN_CDLGTR] = "cdlgtr", | |
464 | [LONG_INSN_CEFBRA] = "cefbra", | |
465 | [LONG_INSN_CEGBRA] = "cegbra", | |
466 | [LONG_INSN_CELFBR] = "celfbr", | |
467 | [LONG_INSN_CELGBR] = "celgbr", | |
468 | [LONG_INSN_CFDBRA] = "cfdbra", | |
469 | [LONG_INSN_CFEBRA] = "cfebra", | |
470 | [LONG_INSN_CFXBRA] = "cfxbra", | |
471 | [LONG_INSN_CGDBRA] = "cgdbra", | |
472 | [LONG_INSN_CGDTRA] = "cgdtra", | |
473 | [LONG_INSN_CGEBRA] = "cgebra", | |
474 | [LONG_INSN_CGXBRA] = "cgxbra", | |
475 | [LONG_INSN_CGXTRA] = "cgxtra", | |
476 | [LONG_INSN_CLFDBR] = "clfdbr", | |
477 | [LONG_INSN_CLFDTR] = "clfdtr", | |
478 | [LONG_INSN_CLFEBR] = "clfebr", | |
479 | [LONG_INSN_CLFHSI] = "clfhsi", | |
480 | [LONG_INSN_CLFXBR] = "clfxbr", | |
481 | [LONG_INSN_CLFXTR] = "clfxtr", | |
482 | [LONG_INSN_CLGDBR] = "clgdbr", | |
483 | [LONG_INSN_CLGDTR] = "clgdtr", | |
484 | [LONG_INSN_CLGEBR] = "clgebr", | |
485 | [LONG_INSN_CLGFRL] = "clgfrl", | |
486 | [LONG_INSN_CLGHRL] = "clghrl", | |
487 | [LONG_INSN_CLGHSI] = "clghsi", | |
488 | [LONG_INSN_CLGXBR] = "clgxbr", | |
489 | [LONG_INSN_CLGXTR] = "clgxtr", | |
490 | [LONG_INSN_CLHHSI] = "clhhsi", | |
491 | [LONG_INSN_CXFBRA] = "cxfbra", | |
492 | [LONG_INSN_CXGBRA] = "cxgbra", | |
493 | [LONG_INSN_CXGTRA] = "cxgtra", | |
494 | [LONG_INSN_CXLFBR] = "cxlfbr", | |
495 | [LONG_INSN_CXLFTR] = "cxlftr", | |
496 | [LONG_INSN_CXLGBR] = "cxlgbr", | |
497 | [LONG_INSN_CXLGTR] = "cxlgtr", | |
498 | [LONG_INSN_FIDBRA] = "fidbra", | |
499 | [LONG_INSN_FIEBRA] = "fiebra", | |
500 | [LONG_INSN_FIXBRA] = "fixbra", | |
501 | [LONG_INSN_LDXBRA] = "ldxbra", | |
502 | [LONG_INSN_LEDBRA] = "ledbra", | |
503 | [LONG_INSN_LEXBRA] = "lexbra", | |
504 | [LONG_INSN_LLGFAT] = "llgfat", | |
505 | [LONG_INSN_LLGFRL] = "llgfrl", | |
506 | [LONG_INSN_LLGHRL] = "llghrl", | |
507 | [LONG_INSN_LLGTAT] = "llgtat", | |
508 | [LONG_INSN_POPCNT] = "popcnt", | |
509 | [LONG_INSN_RIEMIT] = "riemit", | |
510 | [LONG_INSN_RINEXT] = "rinext", | |
511 | [LONG_INSN_RISBGN] = "risbgn", | |
512 | [LONG_INSN_RISBHG] = "risbhg", | |
513 | [LONG_INSN_RISBLG] = "risblg", | |
514 | [LONG_INSN_SLHHHR] = "slhhhr", | |
515 | [LONG_INSN_SLHHLR] = "slhhlr", | |
516 | [LONG_INSN_TABORT] = "tabort", | |
517 | [LONG_INSN_TBEGIN] = "tbegin", | |
518 | [LONG_INSN_TBEGINC] = "tbeginc", | |
519 | [LONG_INSN_PCISTG] = "pcistg", | |
520 | [LONG_INSN_MPCIFC] = "mpcifc", | |
521 | [LONG_INSN_STPCIFC] = "stpcifc", | |
522 | [LONG_INSN_PCISTB] = "pcistb", | |
523 | [LONG_INSN_VPOPCT] = "vpopct", | |
524 | [LONG_INSN_VERLLV] = "verllv", | |
525 | [LONG_INSN_VESRAV] = "vesrav", | |
526 | [LONG_INSN_VESRLV] = "vesrlv", | |
527 | [LONG_INSN_VSBCBI] = "vsbcbi", | |
528 | [LONG_INSN_STCCTM] = "stcctm", | |
529 | }; | |
530 | ||
531 | static struct s390_insn opcode[] = { | |
532 | { "bprp", 0xc5, INSTR_MII_UPI }, | |
533 | { "bpp", 0xc7, INSTR_SMI_U0RDP }, | |
534 | { "trtr", 0xd0, INSTR_SS_L0RDRD }, | |
535 | { "lmd", 0xef, INSTR_SS_RRRDRD3 }, | |
536 | { "spm", 0x04, INSTR_RR_R0 }, | |
537 | { "balr", 0x05, INSTR_RR_RR }, | |
538 | { "bctr", 0x06, INSTR_RR_RR }, | |
539 | { "bcr", 0x07, INSTR_RR_UR }, | |
540 | { "svc", 0x0a, INSTR_RR_U0 }, | |
541 | { "bsm", 0x0b, INSTR_RR_RR }, | |
542 | { "bassm", 0x0c, INSTR_RR_RR }, | |
543 | { "basr", 0x0d, INSTR_RR_RR }, | |
544 | { "mvcl", 0x0e, INSTR_RR_RR }, | |
545 | { "clcl", 0x0f, INSTR_RR_RR }, | |
546 | { "lpr", 0x10, INSTR_RR_RR }, | |
547 | { "lnr", 0x11, INSTR_RR_RR }, | |
548 | { "ltr", 0x12, INSTR_RR_RR }, | |
549 | { "lcr", 0x13, INSTR_RR_RR }, | |
550 | { "nr", 0x14, INSTR_RR_RR }, | |
551 | { "clr", 0x15, INSTR_RR_RR }, | |
552 | { "or", 0x16, INSTR_RR_RR }, | |
553 | { "xr", 0x17, INSTR_RR_RR }, | |
554 | { "lr", 0x18, INSTR_RR_RR }, | |
555 | { "cr", 0x19, INSTR_RR_RR }, | |
556 | { "ar", 0x1a, INSTR_RR_RR }, | |
557 | { "sr", 0x1b, INSTR_RR_RR }, | |
558 | { "mr", 0x1c, INSTR_RR_RR }, | |
559 | { "dr", 0x1d, INSTR_RR_RR }, | |
560 | { "alr", 0x1e, INSTR_RR_RR }, | |
561 | { "slr", 0x1f, INSTR_RR_RR }, | |
562 | { "lpdr", 0x20, INSTR_RR_FF }, | |
563 | { "lndr", 0x21, INSTR_RR_FF }, | |
564 | { "ltdr", 0x22, INSTR_RR_FF }, | |
565 | { "lcdr", 0x23, INSTR_RR_FF }, | |
566 | { "hdr", 0x24, INSTR_RR_FF }, | |
567 | { "ldxr", 0x25, INSTR_RR_FF }, | |
568 | { "mxr", 0x26, INSTR_RR_FF }, | |
569 | { "mxdr", 0x27, INSTR_RR_FF }, | |
570 | { "ldr", 0x28, INSTR_RR_FF }, | |
571 | { "cdr", 0x29, INSTR_RR_FF }, | |
572 | { "adr", 0x2a, INSTR_RR_FF }, | |
573 | { "sdr", 0x2b, INSTR_RR_FF }, | |
574 | { "mdr", 0x2c, INSTR_RR_FF }, | |
575 | { "ddr", 0x2d, INSTR_RR_FF }, | |
576 | { "awr", 0x2e, INSTR_RR_FF }, | |
577 | { "swr", 0x2f, INSTR_RR_FF }, | |
578 | { "lper", 0x30, INSTR_RR_FF }, | |
579 | { "lner", 0x31, INSTR_RR_FF }, | |
580 | { "lter", 0x32, INSTR_RR_FF }, | |
581 | { "lcer", 0x33, INSTR_RR_FF }, | |
582 | { "her", 0x34, INSTR_RR_FF }, | |
583 | { "ledr", 0x35, INSTR_RR_FF }, | |
584 | { "axr", 0x36, INSTR_RR_FF }, | |
585 | { "sxr", 0x37, INSTR_RR_FF }, | |
586 | { "ler", 0x38, INSTR_RR_FF }, | |
587 | { "cer", 0x39, INSTR_RR_FF }, | |
588 | { "aer", 0x3a, INSTR_RR_FF }, | |
589 | { "ser", 0x3b, INSTR_RR_FF }, | |
590 | { "mder", 0x3c, INSTR_RR_FF }, | |
591 | { "der", 0x3d, INSTR_RR_FF }, | |
592 | { "aur", 0x3e, INSTR_RR_FF }, | |
593 | { "sur", 0x3f, INSTR_RR_FF }, | |
594 | { "sth", 0x40, INSTR_RX_RRRD }, | |
595 | { "la", 0x41, INSTR_RX_RRRD }, | |
596 | { "stc", 0x42, INSTR_RX_RRRD }, | |
597 | { "ic", 0x43, INSTR_RX_RRRD }, | |
598 | { "ex", 0x44, INSTR_RX_RRRD }, | |
599 | { "bal", 0x45, INSTR_RX_RRRD }, | |
600 | { "bct", 0x46, INSTR_RX_RRRD }, | |
601 | { "bc", 0x47, INSTR_RX_URRD }, | |
602 | { "lh", 0x48, INSTR_RX_RRRD }, | |
603 | { "ch", 0x49, INSTR_RX_RRRD }, | |
604 | { "ah", 0x4a, INSTR_RX_RRRD }, | |
605 | { "sh", 0x4b, INSTR_RX_RRRD }, | |
606 | { "mh", 0x4c, INSTR_RX_RRRD }, | |
607 | { "bas", 0x4d, INSTR_RX_RRRD }, | |
608 | { "cvd", 0x4e, INSTR_RX_RRRD }, | |
609 | { "cvb", 0x4f, INSTR_RX_RRRD }, | |
610 | { "st", 0x50, INSTR_RX_RRRD }, | |
611 | { "lae", 0x51, INSTR_RX_RRRD }, | |
612 | { "n", 0x54, INSTR_RX_RRRD }, | |
613 | { "cl", 0x55, INSTR_RX_RRRD }, | |
614 | { "o", 0x56, INSTR_RX_RRRD }, | |
615 | { "x", 0x57, INSTR_RX_RRRD }, | |
616 | { "l", 0x58, INSTR_RX_RRRD }, | |
617 | { "c", 0x59, INSTR_RX_RRRD }, | |
618 | { "a", 0x5a, INSTR_RX_RRRD }, | |
619 | { "s", 0x5b, INSTR_RX_RRRD }, | |
620 | { "m", 0x5c, INSTR_RX_RRRD }, | |
621 | { "d", 0x5d, INSTR_RX_RRRD }, | |
622 | { "al", 0x5e, INSTR_RX_RRRD }, | |
623 | { "sl", 0x5f, INSTR_RX_RRRD }, | |
624 | { "std", 0x60, INSTR_RX_FRRD }, | |
625 | { "mxd", 0x67, INSTR_RX_FRRD }, | |
626 | { "ld", 0x68, INSTR_RX_FRRD }, | |
627 | { "cd", 0x69, INSTR_RX_FRRD }, | |
628 | { "ad", 0x6a, INSTR_RX_FRRD }, | |
629 | { "sd", 0x6b, INSTR_RX_FRRD }, | |
630 | { "md", 0x6c, INSTR_RX_FRRD }, | |
631 | { "dd", 0x6d, INSTR_RX_FRRD }, | |
632 | { "aw", 0x6e, INSTR_RX_FRRD }, | |
633 | { "sw", 0x6f, INSTR_RX_FRRD }, | |
634 | { "ste", 0x70, INSTR_RX_FRRD }, | |
635 | { "ms", 0x71, INSTR_RX_RRRD }, | |
636 | { "le", 0x78, INSTR_RX_FRRD }, | |
637 | { "ce", 0x79, INSTR_RX_FRRD }, | |
638 | { "ae", 0x7a, INSTR_RX_FRRD }, | |
639 | { "se", 0x7b, INSTR_RX_FRRD }, | |
640 | { "mde", 0x7c, INSTR_RX_FRRD }, | |
641 | { "de", 0x7d, INSTR_RX_FRRD }, | |
642 | { "au", 0x7e, INSTR_RX_FRRD }, | |
643 | { "su", 0x7f, INSTR_RX_FRRD }, | |
644 | { "ssm", 0x80, INSTR_S_RD }, | |
645 | { "lpsw", 0x82, INSTR_S_RD }, | |
646 | { "diag", 0x83, INSTR_RS_RRRD }, | |
647 | { "brxh", 0x84, INSTR_RSI_RRP }, | |
648 | { "brxle", 0x85, INSTR_RSI_RRP }, | |
649 | { "bxh", 0x86, INSTR_RS_RRRD }, | |
650 | { "bxle", 0x87, INSTR_RS_RRRD }, | |
651 | { "srl", 0x88, INSTR_RS_R0RD }, | |
652 | { "sll", 0x89, INSTR_RS_R0RD }, | |
653 | { "sra", 0x8a, INSTR_RS_R0RD }, | |
654 | { "sla", 0x8b, INSTR_RS_R0RD }, | |
655 | { "srdl", 0x8c, INSTR_RS_R0RD }, | |
656 | { "sldl", 0x8d, INSTR_RS_R0RD }, | |
657 | { "srda", 0x8e, INSTR_RS_R0RD }, | |
658 | { "slda", 0x8f, INSTR_RS_R0RD }, | |
659 | { "stm", 0x90, INSTR_RS_RRRD }, | |
660 | { "tm", 0x91, INSTR_SI_URD }, | |
661 | { "mvi", 0x92, INSTR_SI_URD }, | |
662 | { "ts", 0x93, INSTR_S_RD }, | |
663 | { "ni", 0x94, INSTR_SI_URD }, | |
664 | { "cli", 0x95, INSTR_SI_URD }, | |
665 | { "oi", 0x96, INSTR_SI_URD }, | |
666 | { "xi", 0x97, INSTR_SI_URD }, | |
667 | { "lm", 0x98, INSTR_RS_RRRD }, | |
668 | { "trace", 0x99, INSTR_RS_RRRD }, | |
669 | { "lam", 0x9a, INSTR_RS_AARD }, | |
670 | { "stam", 0x9b, INSTR_RS_AARD }, | |
671 | { "mvcle", 0xa8, INSTR_RS_RRRD }, | |
672 | { "clcle", 0xa9, INSTR_RS_RRRD }, | |
673 | { "stnsm", 0xac, INSTR_SI_URD }, | |
674 | { "stosm", 0xad, INSTR_SI_URD }, | |
675 | { "sigp", 0xae, INSTR_RS_RRRD }, | |
676 | { "mc", 0xaf, INSTR_SI_URD }, | |
677 | { "lra", 0xb1, INSTR_RX_RRRD }, | |
678 | { "stctl", 0xb6, INSTR_RS_CCRD }, | |
679 | { "lctl", 0xb7, INSTR_RS_CCRD }, | |
680 | { "cs", 0xba, INSTR_RS_RRRD }, | |
681 | { "cds", 0xbb, INSTR_RS_RRRD }, | |
682 | { "clm", 0xbd, INSTR_RS_RURD }, | |
683 | { "stcm", 0xbe, INSTR_RS_RURD }, | |
684 | { "icm", 0xbf, INSTR_RS_RURD }, | |
685 | { "mvn", 0xd1, INSTR_SS_L0RDRD }, | |
686 | { "mvc", 0xd2, INSTR_SS_L0RDRD }, | |
687 | { "mvz", 0xd3, INSTR_SS_L0RDRD }, | |
688 | { "nc", 0xd4, INSTR_SS_L0RDRD }, | |
689 | { "clc", 0xd5, INSTR_SS_L0RDRD }, | |
690 | { "oc", 0xd6, INSTR_SS_L0RDRD }, | |
691 | { "xc", 0xd7, INSTR_SS_L0RDRD }, | |
692 | { "mvck", 0xd9, INSTR_SS_RRRDRD }, | |
693 | { "mvcp", 0xda, INSTR_SS_RRRDRD }, | |
694 | { "mvcs", 0xdb, INSTR_SS_RRRDRD }, | |
695 | { "tr", 0xdc, INSTR_SS_L0RDRD }, | |
696 | { "trt", 0xdd, INSTR_SS_L0RDRD }, | |
697 | { "ed", 0xde, INSTR_SS_L0RDRD }, | |
698 | { "edmk", 0xdf, INSTR_SS_L0RDRD }, | |
699 | { "pku", 0xe1, INSTR_SS_L0RDRD }, | |
700 | { "unpku", 0xe2, INSTR_SS_L0RDRD }, | |
701 | { "mvcin", 0xe8, INSTR_SS_L0RDRD }, | |
702 | { "pka", 0xe9, INSTR_SS_L0RDRD }, | |
703 | { "unpka", 0xea, INSTR_SS_L0RDRD }, | |
704 | { "plo", 0xee, INSTR_SS_RRRDRD2 }, | |
705 | { "srp", 0xf0, INSTR_SS_LIRDRD }, | |
706 | { "mvo", 0xf1, INSTR_SS_LLRDRD }, | |
707 | { "pack", 0xf2, INSTR_SS_LLRDRD }, | |
708 | { "unpk", 0xf3, INSTR_SS_LLRDRD }, | |
709 | { "zap", 0xf8, INSTR_SS_LLRDRD }, | |
710 | { "cp", 0xf9, INSTR_SS_LLRDRD }, | |
711 | { "ap", 0xfa, INSTR_SS_LLRDRD }, | |
712 | { "sp", 0xfb, INSTR_SS_LLRDRD }, | |
713 | { "mp", 0xfc, INSTR_SS_LLRDRD }, | |
714 | { "dp", 0xfd, INSTR_SS_LLRDRD }, | |
715 | { "", 0, INSTR_INVALID } | |
716 | }; | |
717 | ||
718 | static struct s390_insn opcode_01[] = { | |
719 | { "ptff", 0x04, INSTR_E }, | |
720 | { "pfpo", 0x0a, INSTR_E }, | |
721 | { "sam64", 0x0e, INSTR_E }, | |
722 | { "pr", 0x01, INSTR_E }, | |
723 | { "upt", 0x02, INSTR_E }, | |
724 | { "sckpf", 0x07, INSTR_E }, | |
725 | { "tam", 0x0b, INSTR_E }, | |
726 | { "sam24", 0x0c, INSTR_E }, | |
727 | { "sam31", 0x0d, INSTR_E }, | |
728 | { "trap2", 0xff, INSTR_E }, | |
729 | { "", 0, INSTR_INVALID } | |
730 | }; | |
731 | ||
732 | static struct s390_insn opcode_a5[] = { | |
733 | { "iihh", 0x00, INSTR_RI_RU }, | |
734 | { "iihl", 0x01, INSTR_RI_RU }, | |
735 | { "iilh", 0x02, INSTR_RI_RU }, | |
736 | { "iill", 0x03, INSTR_RI_RU }, | |
737 | { "nihh", 0x04, INSTR_RI_RU }, | |
738 | { "nihl", 0x05, INSTR_RI_RU }, | |
739 | { "nilh", 0x06, INSTR_RI_RU }, | |
740 | { "nill", 0x07, INSTR_RI_RU }, | |
741 | { "oihh", 0x08, INSTR_RI_RU }, | |
742 | { "oihl", 0x09, INSTR_RI_RU }, | |
743 | { "oilh", 0x0a, INSTR_RI_RU }, | |
744 | { "oill", 0x0b, INSTR_RI_RU }, | |
745 | { "llihh", 0x0c, INSTR_RI_RU }, | |
746 | { "llihl", 0x0d, INSTR_RI_RU }, | |
747 | { "llilh", 0x0e, INSTR_RI_RU }, | |
748 | { "llill", 0x0f, INSTR_RI_RU }, | |
749 | { "", 0, INSTR_INVALID } | |
750 | }; | |
751 | ||
752 | static struct s390_insn opcode_a7[] = { | |
753 | { "tmhh", 0x02, INSTR_RI_RU }, | |
754 | { "tmhl", 0x03, INSTR_RI_RU }, | |
755 | { "brctg", 0x07, INSTR_RI_RP }, | |
756 | { "lghi", 0x09, INSTR_RI_RI }, | |
757 | { "aghi", 0x0b, INSTR_RI_RI }, | |
758 | { "mghi", 0x0d, INSTR_RI_RI }, | |
759 | { "cghi", 0x0f, INSTR_RI_RI }, | |
760 | { "tmlh", 0x00, INSTR_RI_RU }, | |
761 | { "tmll", 0x01, INSTR_RI_RU }, | |
762 | { "brc", 0x04, INSTR_RI_UP }, | |
763 | { "bras", 0x05, INSTR_RI_RP }, | |
764 | { "brct", 0x06, INSTR_RI_RP }, | |
765 | { "lhi", 0x08, INSTR_RI_RI }, | |
766 | { "ahi", 0x0a, INSTR_RI_RI }, | |
767 | { "mhi", 0x0c, INSTR_RI_RI }, | |
768 | { "chi", 0x0e, INSTR_RI_RI }, | |
769 | { "", 0, INSTR_INVALID } | |
770 | }; | |
771 | ||
772 | static struct s390_insn opcode_aa[] = { | |
773 | { { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI }, | |
774 | { "rion", 0x01, INSTR_RI_RI }, | |
775 | { "tric", 0x02, INSTR_RI_RI }, | |
776 | { "rioff", 0x03, INSTR_RI_RI }, | |
777 | { { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI }, | |
778 | { "", 0, INSTR_INVALID } | |
779 | }; | |
780 | ||
781 | static struct s390_insn opcode_b2[] = { | |
782 | { "stckf", 0x7c, INSTR_S_RD }, | |
783 | { "lpp", 0x80, INSTR_S_RD }, | |
784 | { "lcctl", 0x84, INSTR_S_RD }, | |
785 | { "lpctl", 0x85, INSTR_S_RD }, | |
786 | { "qsi", 0x86, INSTR_S_RD }, | |
787 | { "lsctl", 0x87, INSTR_S_RD }, | |
788 | { "qctri", 0x8e, INSTR_S_RD }, | |
789 | { "stfle", 0xb0, INSTR_S_RD }, | |
790 | { "lpswe", 0xb2, INSTR_S_RD }, | |
791 | { "srnmb", 0xb8, INSTR_S_RD }, | |
792 | { "srnmt", 0xb9, INSTR_S_RD }, | |
793 | { "lfas", 0xbd, INSTR_S_RD }, | |
794 | { "scctr", 0xe0, INSTR_RRE_RR }, | |
795 | { "spctr", 0xe1, INSTR_RRE_RR }, | |
796 | { "ecctr", 0xe4, INSTR_RRE_RR }, | |
797 | { "epctr", 0xe5, INSTR_RRE_RR }, | |
798 | { "ppa", 0xe8, INSTR_RRF_U0RR }, | |
799 | { "etnd", 0xec, INSTR_RRE_R0 }, | |
800 | { "ecpga", 0xed, INSTR_RRE_RR }, | |
801 | { "tend", 0xf8, INSTR_S_00 }, | |
802 | { "niai", 0xfa, INSTR_IE_UU }, | |
803 | { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD }, | |
804 | { "stidp", 0x02, INSTR_S_RD }, | |
805 | { "sck", 0x04, INSTR_S_RD }, | |
806 | { "stck", 0x05, INSTR_S_RD }, | |
807 | { "sckc", 0x06, INSTR_S_RD }, | |
808 | { "stckc", 0x07, INSTR_S_RD }, | |
809 | { "spt", 0x08, INSTR_S_RD }, | |
810 | { "stpt", 0x09, INSTR_S_RD }, | |
811 | { "spka", 0x0a, INSTR_S_RD }, | |
812 | { "ipk", 0x0b, INSTR_S_00 }, | |
813 | { "ptlb", 0x0d, INSTR_S_00 }, | |
814 | { "spx", 0x10, INSTR_S_RD }, | |
815 | { "stpx", 0x11, INSTR_S_RD }, | |
816 | { "stap", 0x12, INSTR_S_RD }, | |
817 | { "sie", 0x14, INSTR_S_RD }, | |
818 | { "pc", 0x18, INSTR_S_RD }, | |
819 | { "sac", 0x19, INSTR_S_RD }, | |
820 | { "cfc", 0x1a, INSTR_S_RD }, | |
821 | { "servc", 0x20, INSTR_RRE_RR }, | |
822 | { "ipte", 0x21, INSTR_RRE_RR }, | |
823 | { "ipm", 0x22, INSTR_RRE_R0 }, | |
824 | { "ivsk", 0x23, INSTR_RRE_RR }, | |
825 | { "iac", 0x24, INSTR_RRE_R0 }, | |
826 | { "ssar", 0x25, INSTR_RRE_R0 }, | |
827 | { "epar", 0x26, INSTR_RRE_R0 }, | |
828 | { "esar", 0x27, INSTR_RRE_R0 }, | |
829 | { "pt", 0x28, INSTR_RRE_RR }, | |
830 | { "iske", 0x29, INSTR_RRE_RR }, | |
831 | { "rrbe", 0x2a, INSTR_RRE_RR }, | |
832 | { "sske", 0x2b, INSTR_RRF_M0RR }, | |
833 | { "tb", 0x2c, INSTR_RRE_0R }, | |
834 | { "dxr", 0x2d, INSTR_RRE_FF }, | |
835 | { "pgin", 0x2e, INSTR_RRE_RR }, | |
836 | { "pgout", 0x2f, INSTR_RRE_RR }, | |
837 | { "csch", 0x30, INSTR_S_00 }, | |
838 | { "hsch", 0x31, INSTR_S_00 }, | |
839 | { "msch", 0x32, INSTR_S_RD }, | |
840 | { "ssch", 0x33, INSTR_S_RD }, | |
841 | { "stsch", 0x34, INSTR_S_RD }, | |
842 | { "tsch", 0x35, INSTR_S_RD }, | |
843 | { "tpi", 0x36, INSTR_S_RD }, | |
844 | { "sal", 0x37, INSTR_S_00 }, | |
845 | { "rsch", 0x38, INSTR_S_00 }, | |
846 | { "stcrw", 0x39, INSTR_S_RD }, | |
847 | { "stcps", 0x3a, INSTR_S_RD }, | |
848 | { "rchp", 0x3b, INSTR_S_00 }, | |
849 | { "schm", 0x3c, INSTR_S_00 }, | |
850 | { "bakr", 0x40, INSTR_RRE_RR }, | |
851 | { "cksm", 0x41, INSTR_RRE_RR }, | |
852 | { "sqdr", 0x44, INSTR_RRE_FF }, | |
853 | { "sqer", 0x45, INSTR_RRE_FF }, | |
854 | { "stura", 0x46, INSTR_RRE_RR }, | |
855 | { "msta", 0x47, INSTR_RRE_R0 }, | |
856 | { "palb", 0x48, INSTR_RRE_00 }, | |
857 | { "ereg", 0x49, INSTR_RRE_RR }, | |
858 | { "esta", 0x4a, INSTR_RRE_RR }, | |
859 | { "lura", 0x4b, INSTR_RRE_RR }, | |
860 | { "tar", 0x4c, INSTR_RRE_AR }, | |
861 | { "cpya", 0x4d, INSTR_RRE_AA }, | |
862 | { "sar", 0x4e, INSTR_RRE_AR }, | |
863 | { "ear", 0x4f, INSTR_RRE_RA }, | |
864 | { "csp", 0x50, INSTR_RRE_RR }, | |
865 | { "msr", 0x52, INSTR_RRE_RR }, | |
866 | { "mvpg", 0x54, INSTR_RRE_RR }, | |
867 | { "mvst", 0x55, INSTR_RRE_RR }, | |
868 | { "cuse", 0x57, INSTR_RRE_RR }, | |
869 | { "bsg", 0x58, INSTR_RRE_RR }, | |
870 | { "bsa", 0x5a, INSTR_RRE_RR }, | |
871 | { "clst", 0x5d, INSTR_RRE_RR }, | |
872 | { "srst", 0x5e, INSTR_RRE_RR }, | |
873 | { "cmpsc", 0x63, INSTR_RRE_RR }, | |
874 | { "siga", 0x74, INSTR_S_RD }, | |
875 | { "xsch", 0x76, INSTR_S_00 }, | |
876 | { "rp", 0x77, INSTR_S_RD }, | |
877 | { "stcke", 0x78, INSTR_S_RD }, | |
878 | { "sacf", 0x79, INSTR_S_RD }, | |
879 | { "stsi", 0x7d, INSTR_S_RD }, | |
880 | { "srnm", 0x99, INSTR_S_RD }, | |
881 | { "stfpc", 0x9c, INSTR_S_RD }, | |
882 | { "lfpc", 0x9d, INSTR_S_RD }, | |
883 | { "tre", 0xa5, INSTR_RRE_RR }, | |
884 | { "cuutf", 0xa6, INSTR_RRF_M0RR }, | |
885 | { "cutfu", 0xa7, INSTR_RRF_M0RR }, | |
886 | { "stfl", 0xb1, INSTR_S_RD }, | |
887 | { "trap4", 0xff, INSTR_S_RD }, | |
888 | { "", 0, INSTR_INVALID } | |
889 | }; | |
890 | ||
891 | static struct s390_insn opcode_b3[] = { | |
892 | { "maylr", 0x38, INSTR_RRF_F0FF }, | |
893 | { "mylr", 0x39, INSTR_RRF_F0FF }, | |
894 | { "mayr", 0x3a, INSTR_RRF_F0FF }, | |
895 | { "myr", 0x3b, INSTR_RRF_F0FF }, | |
896 | { "mayhr", 0x3c, INSTR_RRF_F0FF }, | |
897 | { "myhr", 0x3d, INSTR_RRF_F0FF }, | |
898 | { "lpdfr", 0x70, INSTR_RRE_FF }, | |
899 | { "lndfr", 0x71, INSTR_RRE_FF }, | |
900 | { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, | |
901 | { "lcdfr", 0x73, INSTR_RRE_FF }, | |
902 | { "sfasr", 0x85, INSTR_RRE_R0 }, | |
903 | { { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR }, | |
904 | { { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR }, | |
905 | { { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF }, | |
906 | { { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR }, | |
907 | { { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR }, | |
908 | { { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF }, | |
909 | { { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF }, | |
910 | { { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF }, | |
911 | { { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR }, | |
912 | { { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF }, | |
913 | { { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF }, | |
914 | { { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR }, | |
915 | { { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR }, | |
916 | { { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR }, | |
917 | { { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF }, | |
918 | { { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR }, | |
919 | { { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR }, | |
920 | { { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF }, | |
921 | { { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF }, | |
922 | { { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF }, | |
923 | { { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR }, | |
924 | { { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF }, | |
925 | { { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF }, | |
926 | { { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR }, | |
927 | { "ldgr", 0xc1, INSTR_RRE_FR }, | |
928 | { "cegr", 0xc4, INSTR_RRE_FR }, | |
929 | { "cdgr", 0xc5, INSTR_RRE_FR }, | |
930 | { "cxgr", 0xc6, INSTR_RRE_FR }, | |
931 | { "cger", 0xc8, INSTR_RRF_U0RF }, | |
932 | { "cgdr", 0xc9, INSTR_RRF_U0RF }, | |
933 | { "cgxr", 0xca, INSTR_RRF_U0RF }, | |
934 | { "lgdr", 0xcd, INSTR_RRE_RF }, | |
935 | { "mdtra", 0xd0, INSTR_RRF_FUFF2 }, | |
936 | { "ddtra", 0xd1, INSTR_RRF_FUFF2 }, | |
937 | { "adtra", 0xd2, INSTR_RRF_FUFF2 }, | |
938 | { "sdtra", 0xd3, INSTR_RRF_FUFF2 }, | |
939 | { "ldetr", 0xd4, INSTR_RRF_0UFF }, | |
940 | { "ledtr", 0xd5, INSTR_RRF_UUFF }, | |
941 | { "ltdtr", 0xd6, INSTR_RRE_FF }, | |
942 | { "fidtr", 0xd7, INSTR_RRF_UUFF }, | |
943 | { "mxtra", 0xd8, INSTR_RRF_FUFF2 }, | |
944 | { "dxtra", 0xd9, INSTR_RRF_FUFF2 }, | |
945 | { "axtra", 0xda, INSTR_RRF_FUFF2 }, | |
946 | { "sxtra", 0xdb, INSTR_RRF_FUFF2 }, | |
947 | { "lxdtr", 0xdc, INSTR_RRF_0UFF }, | |
948 | { "ldxtr", 0xdd, INSTR_RRF_UUFF }, | |
949 | { "ltxtr", 0xde, INSTR_RRE_FF }, | |
950 | { "fixtr", 0xdf, INSTR_RRF_UUFF }, | |
951 | { "kdtr", 0xe0, INSTR_RRE_FF }, | |
952 | { { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF }, | |
953 | { "cudtr", 0xe2, INSTR_RRE_RF }, | |
954 | { "csdtr", 0xe3, INSTR_RRE_RF }, | |
955 | { "cdtr", 0xe4, INSTR_RRE_FF }, | |
956 | { "eedtr", 0xe5, INSTR_RRE_RF }, | |
957 | { "esdtr", 0xe7, INSTR_RRE_RF }, | |
958 | { "kxtr", 0xe8, INSTR_RRE_FF }, | |
959 | { { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR }, | |
960 | { "cuxtr", 0xea, INSTR_RRE_RF }, | |
961 | { "csxtr", 0xeb, INSTR_RRE_RF }, | |
962 | { "cxtr", 0xec, INSTR_RRE_FF }, | |
963 | { "eextr", 0xed, INSTR_RRE_RF }, | |
964 | { "esxtr", 0xef, INSTR_RRE_RF }, | |
965 | { { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR }, | |
966 | { "cdutr", 0xf2, INSTR_RRE_FR }, | |
967 | { "cdstr", 0xf3, INSTR_RRE_FR }, | |
968 | { "cedtr", 0xf4, INSTR_RRE_FF }, | |
969 | { "qadtr", 0xf5, INSTR_RRF_FUFF }, | |
970 | { "iedtr", 0xf6, INSTR_RRF_F0FR }, | |
971 | { "rrdtr", 0xf7, INSTR_RRF_FFRU }, | |
972 | { { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF }, | |
973 | { "cxutr", 0xfa, INSTR_RRE_FR }, | |
974 | { "cxstr", 0xfb, INSTR_RRE_FR }, | |
975 | { "cextr", 0xfc, INSTR_RRE_FF }, | |
976 | { "qaxtr", 0xfd, INSTR_RRF_FUFF }, | |
977 | { "iextr", 0xfe, INSTR_RRF_F0FR }, | |
978 | { "rrxtr", 0xff, INSTR_RRF_FFRU }, | |
979 | { "lpebr", 0x00, INSTR_RRE_FF }, | |
980 | { "lnebr", 0x01, INSTR_RRE_FF }, | |
981 | { "ltebr", 0x02, INSTR_RRE_FF }, | |
982 | { "lcebr", 0x03, INSTR_RRE_FF }, | |
983 | { "ldebr", 0x04, INSTR_RRE_FF }, | |
984 | { "lxdbr", 0x05, INSTR_RRE_FF }, | |
985 | { "lxebr", 0x06, INSTR_RRE_FF }, | |
986 | { "mxdbr", 0x07, INSTR_RRE_FF }, | |
987 | { "kebr", 0x08, INSTR_RRE_FF }, | |
988 | { "cebr", 0x09, INSTR_RRE_FF }, | |
989 | { "aebr", 0x0a, INSTR_RRE_FF }, | |
990 | { "sebr", 0x0b, INSTR_RRE_FF }, | |
991 | { "mdebr", 0x0c, INSTR_RRE_FF }, | |
992 | { "debr", 0x0d, INSTR_RRE_FF }, | |
993 | { "maebr", 0x0e, INSTR_RRF_F0FF }, | |
994 | { "msebr", 0x0f, INSTR_RRF_F0FF }, | |
995 | { "lpdbr", 0x10, INSTR_RRE_FF }, | |
996 | { "lndbr", 0x11, INSTR_RRE_FF }, | |
997 | { "ltdbr", 0x12, INSTR_RRE_FF }, | |
998 | { "lcdbr", 0x13, INSTR_RRE_FF }, | |
999 | { "sqebr", 0x14, INSTR_RRE_FF }, | |
1000 | { "sqdbr", 0x15, INSTR_RRE_FF }, | |
1001 | { "sqxbr", 0x16, INSTR_RRE_FF }, | |
1002 | { "meebr", 0x17, INSTR_RRE_FF }, | |
1003 | { "kdbr", 0x18, INSTR_RRE_FF }, | |
1004 | { "cdbr", 0x19, INSTR_RRE_FF }, | |
1005 | { "adbr", 0x1a, INSTR_RRE_FF }, | |
1006 | { "sdbr", 0x1b, INSTR_RRE_FF }, | |
1007 | { "mdbr", 0x1c, INSTR_RRE_FF }, | |
1008 | { "ddbr", 0x1d, INSTR_RRE_FF }, | |
1009 | { "madbr", 0x1e, INSTR_RRF_F0FF }, | |
1010 | { "msdbr", 0x1f, INSTR_RRF_F0FF }, | |
1011 | { "lder", 0x24, INSTR_RRE_FF }, | |
1012 | { "lxdr", 0x25, INSTR_RRE_FF }, | |
1013 | { "lxer", 0x26, INSTR_RRE_FF }, | |
1014 | { "maer", 0x2e, INSTR_RRF_F0FF }, | |
1015 | { "mser", 0x2f, INSTR_RRF_F0FF }, | |
1016 | { "sqxr", 0x36, INSTR_RRE_FF }, | |
1017 | { "meer", 0x37, INSTR_RRE_FF }, | |
1018 | { "madr", 0x3e, INSTR_RRF_F0FF }, | |
1019 | { "msdr", 0x3f, INSTR_RRF_F0FF }, | |
1020 | { "lpxbr", 0x40, INSTR_RRE_FF }, | |
1021 | { "lnxbr", 0x41, INSTR_RRE_FF }, | |
1022 | { "ltxbr", 0x42, INSTR_RRE_FF }, | |
1023 | { "lcxbr", 0x43, INSTR_RRE_FF }, | |
1024 | { { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF }, | |
1025 | { { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF }, | |
1026 | { { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF }, | |
1027 | { { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF }, | |
1028 | { "kxbr", 0x48, INSTR_RRE_FF }, | |
1029 | { "cxbr", 0x49, INSTR_RRE_FF }, | |
1030 | { "axbr", 0x4a, INSTR_RRE_FF }, | |
1031 | { "sxbr", 0x4b, INSTR_RRE_FF }, | |
1032 | { "mxbr", 0x4c, INSTR_RRE_FF }, | |
1033 | { "dxbr", 0x4d, INSTR_RRE_FF }, | |
1034 | { "tbedr", 0x50, INSTR_RRF_U0FF }, | |
1035 | { "tbdr", 0x51, INSTR_RRF_U0FF }, | |
1036 | { "diebr", 0x53, INSTR_RRF_FUFF }, | |
1037 | { { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF }, | |
1038 | { "thder", 0x58, INSTR_RRE_FF }, | |
1039 | { "thdr", 0x59, INSTR_RRE_FF }, | |
1040 | { "didbr", 0x5b, INSTR_RRF_FUFF }, | |
1041 | { { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF }, | |
1042 | { "lpxr", 0x60, INSTR_RRE_FF }, | |
1043 | { "lnxr", 0x61, INSTR_RRE_FF }, | |
1044 | { "ltxr", 0x62, INSTR_RRE_FF }, | |
1045 | { "lcxr", 0x63, INSTR_RRE_FF }, | |
1046 | { "lxr", 0x65, INSTR_RRE_FF }, | |
1047 | { "lexr", 0x66, INSTR_RRE_FF }, | |
1048 | { "fixr", 0x67, INSTR_RRE_FF }, | |
1049 | { "cxr", 0x69, INSTR_RRE_FF }, | |
1050 | { "lzer", 0x74, INSTR_RRE_F0 }, | |
1051 | { "lzdr", 0x75, INSTR_RRE_F0 }, | |
1052 | { "lzxr", 0x76, INSTR_RRE_F0 }, | |
1053 | { "fier", 0x77, INSTR_RRE_FF }, | |
1054 | { "fidr", 0x7f, INSTR_RRE_FF }, | |
1055 | { "sfpc", 0x84, INSTR_RRE_RR_OPT }, | |
1056 | { "efpc", 0x8c, INSTR_RRE_RR_OPT }, | |
1057 | { "cefbr", 0x94, INSTR_RRE_RF }, | |
1058 | { "cdfbr", 0x95, INSTR_RRE_RF }, | |
1059 | { "cxfbr", 0x96, INSTR_RRE_RF }, | |
1060 | { "cfebr", 0x98, INSTR_RRF_U0RF }, | |
1061 | { "cfdbr", 0x99, INSTR_RRF_U0RF }, | |
1062 | { "cfxbr", 0x9a, INSTR_RRF_U0RF }, | |
1063 | { "cefr", 0xb4, INSTR_RRE_FR }, | |
1064 | { "cdfr", 0xb5, INSTR_RRE_FR }, | |
1065 | { "cxfr", 0xb6, INSTR_RRE_FR }, | |
1066 | { "cfer", 0xb8, INSTR_RRF_U0RF }, | |
1067 | { "cfdr", 0xb9, INSTR_RRF_U0RF }, | |
1068 | { "cfxr", 0xba, INSTR_RRF_U0RF }, | |
1069 | { "", 0, INSTR_INVALID } | |
1070 | }; | |
1071 | ||
1072 | static struct s390_insn opcode_b9[] = { | |
1073 | { "lpgr", 0x00, INSTR_RRE_RR }, | |
1074 | { "lngr", 0x01, INSTR_RRE_RR }, | |
1075 | { "ltgr", 0x02, INSTR_RRE_RR }, | |
1076 | { "lcgr", 0x03, INSTR_RRE_RR }, | |
1077 | { "lgr", 0x04, INSTR_RRE_RR }, | |
1078 | { "lurag", 0x05, INSTR_RRE_RR }, | |
1079 | { "lgbr", 0x06, INSTR_RRE_RR }, | |
1080 | { "lghr", 0x07, INSTR_RRE_RR }, | |
1081 | { "agr", 0x08, INSTR_RRE_RR }, | |
1082 | { "sgr", 0x09, INSTR_RRE_RR }, | |
1083 | { "algr", 0x0a, INSTR_RRE_RR }, | |
1084 | { "slgr", 0x0b, INSTR_RRE_RR }, | |
1085 | { "msgr", 0x0c, INSTR_RRE_RR }, | |
1086 | { "dsgr", 0x0d, INSTR_RRE_RR }, | |
1087 | { "eregg", 0x0e, INSTR_RRE_RR }, | |
1088 | { "lrvgr", 0x0f, INSTR_RRE_RR }, | |
1089 | { "lpgfr", 0x10, INSTR_RRE_RR }, | |
1090 | { "lngfr", 0x11, INSTR_RRE_RR }, | |
1091 | { "ltgfr", 0x12, INSTR_RRE_RR }, | |
1092 | { "lcgfr", 0x13, INSTR_RRE_RR }, | |
1093 | { "lgfr", 0x14, INSTR_RRE_RR }, | |
1094 | { "llgfr", 0x16, INSTR_RRE_RR }, | |
1095 | { "llgtr", 0x17, INSTR_RRE_RR }, | |
1096 | { "agfr", 0x18, INSTR_RRE_RR }, | |
1097 | { "sgfr", 0x19, INSTR_RRE_RR }, | |
1098 | { "algfr", 0x1a, INSTR_RRE_RR }, | |
1099 | { "slgfr", 0x1b, INSTR_RRE_RR }, | |
1100 | { "msgfr", 0x1c, INSTR_RRE_RR }, | |
1101 | { "dsgfr", 0x1d, INSTR_RRE_RR }, | |
1102 | { "cgr", 0x20, INSTR_RRE_RR }, | |
1103 | { "clgr", 0x21, INSTR_RRE_RR }, | |
1104 | { "sturg", 0x25, INSTR_RRE_RR }, | |
1105 | { "lbr", 0x26, INSTR_RRE_RR }, | |
1106 | { "lhr", 0x27, INSTR_RRE_RR }, | |
1107 | { "cgfr", 0x30, INSTR_RRE_RR }, | |
1108 | { "clgfr", 0x31, INSTR_RRE_RR }, | |
1109 | { "cfdtr", 0x41, INSTR_RRF_UURF }, | |
1110 | { { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF }, | |
1111 | { { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF }, | |
1112 | { "bctgr", 0x46, INSTR_RRE_RR }, | |
1113 | { "cfxtr", 0x49, INSTR_RRF_UURF }, | |
1114 | { { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR }, | |
1115 | { { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR }, | |
1116 | { "cdftr", 0x51, INSTR_RRF_UUFR }, | |
1117 | { { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR }, | |
1118 | { { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR }, | |
1119 | { "cxftr", 0x59, INSTR_RRF_UURF }, | |
1120 | { { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF }, | |
1121 | { { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR }, | |
1122 | { "cgrt", 0x60, INSTR_RRF_U0RR }, | |
1123 | { "clgrt", 0x61, INSTR_RRF_U0RR }, | |
1124 | { "crt", 0x72, INSTR_RRF_U0RR }, | |
1125 | { "clrt", 0x73, INSTR_RRF_U0RR }, | |
1126 | { "ngr", 0x80, INSTR_RRE_RR }, | |
1127 | { "ogr", 0x81, INSTR_RRE_RR }, | |
1128 | { "xgr", 0x82, INSTR_RRE_RR }, | |
1129 | { "flogr", 0x83, INSTR_RRE_RR }, | |
1130 | { "llgcr", 0x84, INSTR_RRE_RR }, | |
1131 | { "llghr", 0x85, INSTR_RRE_RR }, | |
1132 | { "mlgr", 0x86, INSTR_RRE_RR }, | |
1133 | { "dlgr", 0x87, INSTR_RRE_RR }, | |
1134 | { "alcgr", 0x88, INSTR_RRE_RR }, | |
1135 | { "slbgr", 0x89, INSTR_RRE_RR }, | |
1136 | { "cspg", 0x8a, INSTR_RRE_RR }, | |
1137 | { "idte", 0x8e, INSTR_RRF_R0RR }, | |
1138 | { "crdte", 0x8f, INSTR_RRF_RMRR }, | |
1139 | { "llcr", 0x94, INSTR_RRE_RR }, | |
1140 | { "llhr", 0x95, INSTR_RRE_RR }, | |
1141 | { "esea", 0x9d, INSTR_RRE_R0 }, | |
1142 | { "ptf", 0xa2, INSTR_RRE_R0 }, | |
1143 | { "lptea", 0xaa, INSTR_RRF_RURR }, | |
1144 | { "rrbm", 0xae, INSTR_RRE_RR }, | |
1145 | { "pfmf", 0xaf, INSTR_RRE_RR }, | |
1146 | { "cu14", 0xb0, INSTR_RRF_M0RR }, | |
1147 | { "cu24", 0xb1, INSTR_RRF_M0RR }, | |
1148 | { "cu41", 0xb2, INSTR_RRE_RR }, | |
1149 | { "cu42", 0xb3, INSTR_RRE_RR }, | |
1150 | { "trtre", 0xbd, INSTR_RRF_M0RR }, | |
1151 | { "srstu", 0xbe, INSTR_RRE_RR }, | |
1152 | { "trte", 0xbf, INSTR_RRF_M0RR }, | |
1153 | { "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, | |
1154 | { "shhhr", 0xc9, INSTR_RRF_R0RR2 }, | |
1155 | { { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 }, | |
1156 | { { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 }, | |
1157 | { "chhr", 0xcd, INSTR_RRE_RR }, | |
1158 | { "clhhr", 0xcf, INSTR_RRE_RR }, | |
1159 | { { 0, LONG_INSN_PCISTG }, 0xd0, INSTR_RRE_RR }, | |
1160 | { "pcilg", 0xd2, INSTR_RRE_RR }, | |
1161 | { "rpcit", 0xd3, INSTR_RRE_RR }, | |
1162 | { "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, | |
1163 | { "shhlr", 0xd9, INSTR_RRF_R0RR2 }, | |
1164 | { { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 }, | |
1165 | { { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 }, | |
1166 | { "chlr", 0xdd, INSTR_RRE_RR }, | |
1167 | { "clhlr", 0xdf, INSTR_RRE_RR }, | |
1168 | { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, | |
1169 | { "locgr", 0xe2, INSTR_RRF_M0RR }, | |
1170 | { "ngrk", 0xe4, INSTR_RRF_R0RR2 }, | |
1171 | { "ogrk", 0xe6, INSTR_RRF_R0RR2 }, | |
1172 | { "xgrk", 0xe7, INSTR_RRF_R0RR2 }, | |
1173 | { "agrk", 0xe8, INSTR_RRF_R0RR2 }, | |
1174 | { "sgrk", 0xe9, INSTR_RRF_R0RR2 }, | |
1175 | { "algrk", 0xea, INSTR_RRF_R0RR2 }, | |
1176 | { "slgrk", 0xeb, INSTR_RRF_R0RR2 }, | |
1177 | { "locr", 0xf2, INSTR_RRF_M0RR }, | |
1178 | { "nrk", 0xf4, INSTR_RRF_R0RR2 }, | |
1179 | { "ork", 0xf6, INSTR_RRF_R0RR2 }, | |
1180 | { "xrk", 0xf7, INSTR_RRF_R0RR2 }, | |
1181 | { "ark", 0xf8, INSTR_RRF_R0RR2 }, | |
1182 | { "srk", 0xf9, INSTR_RRF_R0RR2 }, | |
1183 | { "alrk", 0xfa, INSTR_RRF_R0RR2 }, | |
1184 | { "slrk", 0xfb, INSTR_RRF_R0RR2 }, | |
1185 | { "kmac", 0x1e, INSTR_RRE_RR }, | |
1186 | { "lrvr", 0x1f, INSTR_RRE_RR }, | |
1187 | { "km", 0x2e, INSTR_RRE_RR }, | |
1188 | { "kmc", 0x2f, INSTR_RRE_RR }, | |
1189 | { "kimd", 0x3e, INSTR_RRE_RR }, | |
1190 | { "klmd", 0x3f, INSTR_RRE_RR }, | |
1191 | { "epsw", 0x8d, INSTR_RRE_RR }, | |
1192 | { "trtt", 0x90, INSTR_RRF_M0RR }, | |
1193 | { "trto", 0x91, INSTR_RRF_M0RR }, | |
1194 | { "trot", 0x92, INSTR_RRF_M0RR }, | |
1195 | { "troo", 0x93, INSTR_RRF_M0RR }, | |
1196 | { "mlr", 0x96, INSTR_RRE_RR }, | |
1197 | { "dlr", 0x97, INSTR_RRE_RR }, | |
1198 | { "alcr", 0x98, INSTR_RRE_RR }, | |
1199 | { "slbr", 0x99, INSTR_RRE_RR }, | |
1200 | { "", 0, INSTR_INVALID } | |
1201 | }; | |
1202 | ||
1203 | static struct s390_insn opcode_c0[] = { | |
1204 | { "lgfi", 0x01, INSTR_RIL_RI }, | |
1205 | { "xihf", 0x06, INSTR_RIL_RU }, | |
1206 | { "xilf", 0x07, INSTR_RIL_RU }, | |
1207 | { "iihf", 0x08, INSTR_RIL_RU }, | |
1208 | { "iilf", 0x09, INSTR_RIL_RU }, | |
1209 | { "nihf", 0x0a, INSTR_RIL_RU }, | |
1210 | { "nilf", 0x0b, INSTR_RIL_RU }, | |
1211 | { "oihf", 0x0c, INSTR_RIL_RU }, | |
1212 | { "oilf", 0x0d, INSTR_RIL_RU }, | |
1213 | { "llihf", 0x0e, INSTR_RIL_RU }, | |
1214 | { "llilf", 0x0f, INSTR_RIL_RU }, | |
1215 | { "larl", 0x00, INSTR_RIL_RP }, | |
1216 | { "brcl", 0x04, INSTR_RIL_UP }, | |
1217 | { "brasl", 0x05, INSTR_RIL_RP }, | |
1218 | { "", 0, INSTR_INVALID } | |
1219 | }; | |
1220 | ||
1221 | static struct s390_insn opcode_c2[] = { | |
1222 | { "msgfi", 0x00, INSTR_RIL_RI }, | |
1223 | { "msfi", 0x01, INSTR_RIL_RI }, | |
1224 | { "slgfi", 0x04, INSTR_RIL_RU }, | |
1225 | { "slfi", 0x05, INSTR_RIL_RU }, | |
1226 | { "agfi", 0x08, INSTR_RIL_RI }, | |
1227 | { "afi", 0x09, INSTR_RIL_RI }, | |
1228 | { "algfi", 0x0a, INSTR_RIL_RU }, | |
1229 | { "alfi", 0x0b, INSTR_RIL_RU }, | |
1230 | { "cgfi", 0x0c, INSTR_RIL_RI }, | |
1231 | { "cfi", 0x0d, INSTR_RIL_RI }, | |
1232 | { "clgfi", 0x0e, INSTR_RIL_RU }, | |
1233 | { "clfi", 0x0f, INSTR_RIL_RU }, | |
1234 | { "", 0, INSTR_INVALID } | |
1235 | }; | |
1236 | ||
1237 | static struct s390_insn opcode_c4[] = { | |
1238 | { "llhrl", 0x02, INSTR_RIL_RP }, | |
1239 | { "lghrl", 0x04, INSTR_RIL_RP }, | |
1240 | { "lhrl", 0x05, INSTR_RIL_RP }, | |
1241 | { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP }, | |
1242 | { "sthrl", 0x07, INSTR_RIL_RP }, | |
1243 | { "lgrl", 0x08, INSTR_RIL_RP }, | |
1244 | { "stgrl", 0x0b, INSTR_RIL_RP }, | |
1245 | { "lgfrl", 0x0c, INSTR_RIL_RP }, | |
1246 | { "lrl", 0x0d, INSTR_RIL_RP }, | |
1247 | { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, | |
1248 | { "strl", 0x0f, INSTR_RIL_RP }, | |
1249 | { "", 0, INSTR_INVALID } | |
1250 | }; | |
1251 | ||
1252 | static struct s390_insn opcode_c6[] = { | |
1253 | { "exrl", 0x00, INSTR_RIL_RP }, | |
1254 | { "pfdrl", 0x02, INSTR_RIL_UP }, | |
1255 | { "cghrl", 0x04, INSTR_RIL_RP }, | |
1256 | { "chrl", 0x05, INSTR_RIL_RP }, | |
1257 | { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP }, | |
1258 | { "clhrl", 0x07, INSTR_RIL_RP }, | |
1259 | { "cgrl", 0x08, INSTR_RIL_RP }, | |
1260 | { "clgrl", 0x0a, INSTR_RIL_RP }, | |
1261 | { "cgfrl", 0x0c, INSTR_RIL_RP }, | |
1262 | { "crl", 0x0d, INSTR_RIL_RP }, | |
1263 | { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, | |
1264 | { "clrl", 0x0f, INSTR_RIL_RP }, | |
1265 | { "", 0, INSTR_INVALID } | |
1266 | }; | |
1267 | ||
1268 | static struct s390_insn opcode_c8[] = { | |
1269 | { "mvcos", 0x00, INSTR_SSF_RRDRD }, | |
1270 | { "ectg", 0x01, INSTR_SSF_RRDRD }, | |
1271 | { "csst", 0x02, INSTR_SSF_RRDRD }, | |
1272 | { "lpd", 0x04, INSTR_SSF_RRDRD2 }, | |
1273 | { "lpdg", 0x05, INSTR_SSF_RRDRD2 }, | |
1274 | { "", 0, INSTR_INVALID } | |
1275 | }; | |
1276 | ||
1277 | static struct s390_insn opcode_cc[] = { | |
1278 | { "brcth", 0x06, INSTR_RIL_RP }, | |
1279 | { "aih", 0x08, INSTR_RIL_RI }, | |
1280 | { "alsih", 0x0a, INSTR_RIL_RI }, | |
1281 | { { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI }, | |
1282 | { "cih", 0x0d, INSTR_RIL_RI }, | |
1283 | { "clih", 0x0f, INSTR_RIL_RI }, | |
1284 | { "", 0, INSTR_INVALID } | |
1285 | }; | |
1286 | ||
1287 | static struct s390_insn opcode_e3[] = { | |
1288 | { "ltg", 0x02, INSTR_RXY_RRRD }, | |
1289 | { "lrag", 0x03, INSTR_RXY_RRRD }, | |
1290 | { "lg", 0x04, INSTR_RXY_RRRD }, | |
1291 | { "cvby", 0x06, INSTR_RXY_RRRD }, | |
1292 | { "ag", 0x08, INSTR_RXY_RRRD }, | |
1293 | { "sg", 0x09, INSTR_RXY_RRRD }, | |
1294 | { "alg", 0x0a, INSTR_RXY_RRRD }, | |
1295 | { "slg", 0x0b, INSTR_RXY_RRRD }, | |
1296 | { "msg", 0x0c, INSTR_RXY_RRRD }, | |
1297 | { "dsg", 0x0d, INSTR_RXY_RRRD }, | |
1298 | { "cvbg", 0x0e, INSTR_RXY_RRRD }, | |
1299 | { "lrvg", 0x0f, INSTR_RXY_RRRD }, | |
1300 | { "lt", 0x12, INSTR_RXY_RRRD }, | |
1301 | { "lray", 0x13, INSTR_RXY_RRRD }, | |
1302 | { "lgf", 0x14, INSTR_RXY_RRRD }, | |
1303 | { "lgh", 0x15, INSTR_RXY_RRRD }, | |
1304 | { "llgf", 0x16, INSTR_RXY_RRRD }, | |
1305 | { "llgt", 0x17, INSTR_RXY_RRRD }, | |
1306 | { "agf", 0x18, INSTR_RXY_RRRD }, | |
1307 | { "sgf", 0x19, INSTR_RXY_RRRD }, | |
1308 | { "algf", 0x1a, INSTR_RXY_RRRD }, | |
1309 | { "slgf", 0x1b, INSTR_RXY_RRRD }, | |
1310 | { "msgf", 0x1c, INSTR_RXY_RRRD }, | |
1311 | { "dsgf", 0x1d, INSTR_RXY_RRRD }, | |
1312 | { "cg", 0x20, INSTR_RXY_RRRD }, | |
1313 | { "clg", 0x21, INSTR_RXY_RRRD }, | |
1314 | { "stg", 0x24, INSTR_RXY_RRRD }, | |
1315 | { "ntstg", 0x25, INSTR_RXY_RRRD }, | |
1316 | { "cvdy", 0x26, INSTR_RXY_RRRD }, | |
1317 | { "cvdg", 0x2e, INSTR_RXY_RRRD }, | |
1318 | { "strvg", 0x2f, INSTR_RXY_RRRD }, | |
1319 | { "cgf", 0x30, INSTR_RXY_RRRD }, | |
1320 | { "clgf", 0x31, INSTR_RXY_RRRD }, | |
1321 | { "ltgf", 0x32, INSTR_RXY_RRRD }, | |
1322 | { "cgh", 0x34, INSTR_RXY_RRRD }, | |
1323 | { "pfd", 0x36, INSTR_RXY_URRD }, | |
1324 | { "strvh", 0x3f, INSTR_RXY_RRRD }, | |
1325 | { "bctg", 0x46, INSTR_RXY_RRRD }, | |
1326 | { "sty", 0x50, INSTR_RXY_RRRD }, | |
1327 | { "msy", 0x51, INSTR_RXY_RRRD }, | |
1328 | { "ny", 0x54, INSTR_RXY_RRRD }, | |
1329 | { "cly", 0x55, INSTR_RXY_RRRD }, | |
1330 | { "oy", 0x56, INSTR_RXY_RRRD }, | |
1331 | { "xy", 0x57, INSTR_RXY_RRRD }, | |
1332 | { "ly", 0x58, INSTR_RXY_RRRD }, | |
1333 | { "cy", 0x59, INSTR_RXY_RRRD }, | |
1334 | { "ay", 0x5a, INSTR_RXY_RRRD }, | |
1335 | { "sy", 0x5b, INSTR_RXY_RRRD }, | |
1336 | { "mfy", 0x5c, INSTR_RXY_RRRD }, | |
1337 | { "aly", 0x5e, INSTR_RXY_RRRD }, | |
1338 | { "sly", 0x5f, INSTR_RXY_RRRD }, | |
1339 | { "sthy", 0x70, INSTR_RXY_RRRD }, | |
1340 | { "lay", 0x71, INSTR_RXY_RRRD }, | |
1341 | { "stcy", 0x72, INSTR_RXY_RRRD }, | |
1342 | { "icy", 0x73, INSTR_RXY_RRRD }, | |
1343 | { "laey", 0x75, INSTR_RXY_RRRD }, | |
1344 | { "lb", 0x76, INSTR_RXY_RRRD }, | |
1345 | { "lgb", 0x77, INSTR_RXY_RRRD }, | |
1346 | { "lhy", 0x78, INSTR_RXY_RRRD }, | |
1347 | { "chy", 0x79, INSTR_RXY_RRRD }, | |
1348 | { "ahy", 0x7a, INSTR_RXY_RRRD }, | |
1349 | { "shy", 0x7b, INSTR_RXY_RRRD }, | |
1350 | { "mhy", 0x7c, INSTR_RXY_RRRD }, | |
1351 | { "ng", 0x80, INSTR_RXY_RRRD }, | |
1352 | { "og", 0x81, INSTR_RXY_RRRD }, | |
1353 | { "xg", 0x82, INSTR_RXY_RRRD }, | |
1354 | { "lgat", 0x85, INSTR_RXY_RRRD }, | |
1355 | { "mlg", 0x86, INSTR_RXY_RRRD }, | |
1356 | { "dlg", 0x87, INSTR_RXY_RRRD }, | |
1357 | { "alcg", 0x88, INSTR_RXY_RRRD }, | |
1358 | { "slbg", 0x89, INSTR_RXY_RRRD }, | |
1359 | { "stpq", 0x8e, INSTR_RXY_RRRD }, | |
1360 | { "lpq", 0x8f, INSTR_RXY_RRRD }, | |
1361 | { "llgc", 0x90, INSTR_RXY_RRRD }, | |
1362 | { "llgh", 0x91, INSTR_RXY_RRRD }, | |
1363 | { "llc", 0x94, INSTR_RXY_RRRD }, | |
1364 | { "llh", 0x95, INSTR_RXY_RRRD }, | |
1365 | { { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD }, | |
1366 | { { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD }, | |
1367 | { "lat", 0x9f, INSTR_RXY_RRRD }, | |
1368 | { "lbh", 0xc0, INSTR_RXY_RRRD }, | |
1369 | { "llch", 0xc2, INSTR_RXY_RRRD }, | |
1370 | { "stch", 0xc3, INSTR_RXY_RRRD }, | |
1371 | { "lhh", 0xc4, INSTR_RXY_RRRD }, | |
1372 | { "llhh", 0xc6, INSTR_RXY_RRRD }, | |
1373 | { "sthh", 0xc7, INSTR_RXY_RRRD }, | |
1374 | { "lfhat", 0xc8, INSTR_RXY_RRRD }, | |
1375 | { "lfh", 0xca, INSTR_RXY_RRRD }, | |
1376 | { "stfh", 0xcb, INSTR_RXY_RRRD }, | |
1377 | { "chf", 0xcd, INSTR_RXY_RRRD }, | |
1378 | { "clhf", 0xcf, INSTR_RXY_RRRD }, | |
1379 | { { 0, LONG_INSN_MPCIFC }, 0xd0, INSTR_RXY_RRRD }, | |
1380 | { { 0, LONG_INSN_STPCIFC }, 0xd4, INSTR_RXY_RRRD }, | |
1381 | { "lrv", 0x1e, INSTR_RXY_RRRD }, | |
1382 | { "lrvh", 0x1f, INSTR_RXY_RRRD }, | |
1383 | { "strv", 0x3e, INSTR_RXY_RRRD }, | |
1384 | { "ml", 0x96, INSTR_RXY_RRRD }, | |
1385 | { "dl", 0x97, INSTR_RXY_RRRD }, | |
1386 | { "alc", 0x98, INSTR_RXY_RRRD }, | |
1387 | { "slb", 0x99, INSTR_RXY_RRRD }, | |
1388 | { "", 0, INSTR_INVALID } | |
1389 | }; | |
1390 | ||
1391 | static struct s390_insn opcode_e5[] = { | |
1392 | { "strag", 0x02, INSTR_SSE_RDRD }, | |
1393 | { "mvhhi", 0x44, INSTR_SIL_RDI }, | |
1394 | { "mvghi", 0x48, INSTR_SIL_RDI }, | |
1395 | { "mvhi", 0x4c, INSTR_SIL_RDI }, | |
1396 | { "chhsi", 0x54, INSTR_SIL_RDI }, | |
1397 | { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, | |
1398 | { "cghsi", 0x58, INSTR_SIL_RDI }, | |
1399 | { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, | |
1400 | { "chsi", 0x5c, INSTR_SIL_RDI }, | |
1401 | { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, | |
1402 | { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU }, | |
1403 | { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU }, | |
1404 | { "lasp", 0x00, INSTR_SSE_RDRD }, | |
1405 | { "tprot", 0x01, INSTR_SSE_RDRD }, | |
1406 | { "mvcsk", 0x0e, INSTR_SSE_RDRD }, | |
1407 | { "mvcdk", 0x0f, INSTR_SSE_RDRD }, | |
1408 | { "", 0, INSTR_INVALID } | |
1409 | }; | |
1410 | ||
1411 | static struct s390_insn opcode_e7[] = { | |
1412 | { "lcbb", 0x27, INSTR_RXE_RRRDM }, | |
1413 | { "vgef", 0x13, INSTR_VRV_VVRDM }, | |
1414 | { "vgeg", 0x12, INSTR_VRV_VVRDM }, | |
1415 | { "vgbm", 0x44, INSTR_VRI_V0I0 }, | |
1416 | { "vgm", 0x46, INSTR_VRI_V0IIM }, | |
1417 | { "vl", 0x06, INSTR_VRX_VRRD0 }, | |
1418 | { "vlr", 0x56, INSTR_VRR_VV00000 }, | |
1419 | { "vlrp", 0x05, INSTR_VRX_VRRDM }, | |
1420 | { "vleb", 0x00, INSTR_VRX_VRRDM }, | |
1421 | { "vleh", 0x01, INSTR_VRX_VRRDM }, | |
1422 | { "vlef", 0x03, INSTR_VRX_VRRDM }, | |
1423 | { "vleg", 0x02, INSTR_VRX_VRRDM }, | |
1424 | { "vleib", 0x40, INSTR_VRI_V0IM }, | |
1425 | { "vleih", 0x41, INSTR_VRI_V0IM }, | |
1426 | { "vleif", 0x43, INSTR_VRI_V0IM }, | |
1427 | { "vleig", 0x42, INSTR_VRI_V0IM }, | |
1428 | { "vlgv", 0x21, INSTR_VRS_RVRDM }, | |
1429 | { "vllez", 0x04, INSTR_VRX_VRRDM }, | |
1430 | { "vlm", 0x36, INSTR_VRS_VVRD0 }, | |
1431 | { "vlbb", 0x07, INSTR_VRX_VRRDM }, | |
1432 | { "vlvg", 0x22, INSTR_VRS_VRRDM }, | |
1433 | { "vlvgp", 0x62, INSTR_VRR_VRR0000 }, | |
1434 | { "vll", 0x37, INSTR_VRS_VRRD0 }, | |
1435 | { "vmrh", 0x61, INSTR_VRR_VVV000M }, | |
1436 | { "vmrl", 0x60, INSTR_VRR_VVV000M }, | |
1437 | { "vpk", 0x94, INSTR_VRR_VVV000M }, | |
1438 | { "vpks", 0x97, INSTR_VRR_VVV0M0M }, | |
1439 | { "vpkls", 0x95, INSTR_VRR_VVV0M0M }, | |
1440 | { "vperm", 0x8c, INSTR_VRR_VVV000V }, | |
1441 | { "vpdi", 0x84, INSTR_VRR_VVV000M }, | |
1442 | { "vrep", 0x4d, INSTR_VRI_VVIM }, | |
1443 | { "vrepi", 0x45, INSTR_VRI_V0IM }, | |
1444 | { "vscef", 0x1b, INSTR_VRV_VWRDM }, | |
1445 | { "vsceg", 0x1a, INSTR_VRV_VWRDM }, | |
1446 | { "vsel", 0x8d, INSTR_VRR_VVV000V }, | |
1447 | { "vseg", 0x5f, INSTR_VRR_VV0000M }, | |
1448 | { "vst", 0x0e, INSTR_VRX_VRRD0 }, | |
1449 | { "vsteb", 0x08, INSTR_VRX_VRRDM }, | |
1450 | { "vsteh", 0x09, INSTR_VRX_VRRDM }, | |
1451 | { "vstef", 0x0b, INSTR_VRX_VRRDM }, | |
1452 | { "vsteg", 0x0a, INSTR_VRX_VRRDM }, | |
1453 | { "vstm", 0x3e, INSTR_VRS_VVRD0 }, | |
1454 | { "vstl", 0x3f, INSTR_VRS_VRRD0 }, | |
1455 | { "vuph", 0xd7, INSTR_VRR_VV0000M }, | |
1456 | { "vuplh", 0xd5, INSTR_VRR_VV0000M }, | |
1457 | { "vupl", 0xd6, INSTR_VRR_VV0000M }, | |
1458 | { "vupll", 0xd4, INSTR_VRR_VV0000M }, | |
1459 | { "va", 0xf3, INSTR_VRR_VVV000M }, | |
1460 | { "vacc", 0xf1, INSTR_VRR_VVV000M }, | |
1461 | { "vac", 0xbb, INSTR_VRR_VVVM00V }, | |
1462 | { "vaccc", 0xb9, INSTR_VRR_VVVM00V }, | |
1463 | { "vn", 0x68, INSTR_VRR_VVV0000 }, | |
1464 | { "vnc", 0x69, INSTR_VRR_VVV0000 }, | |
1465 | { "vavg", 0xf2, INSTR_VRR_VVV000M }, | |
1466 | { "vavgl", 0xf0, INSTR_VRR_VVV000M }, | |
1467 | { "vcksm", 0x66, INSTR_VRR_VVV0000 }, | |
1468 | { "vec", 0xdb, INSTR_VRR_VV0000M }, | |
1469 | { "vecl", 0xd9, INSTR_VRR_VV0000M }, | |
1470 | { "vceq", 0xf8, INSTR_VRR_VVV0M0M }, | |
1471 | { "vch", 0xfb, INSTR_VRR_VVV0M0M }, | |
1472 | { "vchl", 0xf9, INSTR_VRR_VVV0M0M }, | |
1473 | { "vclz", 0x53, INSTR_VRR_VV0000M }, | |
1474 | { "vctz", 0x52, INSTR_VRR_VV0000M }, | |
1475 | { "vx", 0x6d, INSTR_VRR_VVV0000 }, | |
1476 | { "vgfm", 0xb4, INSTR_VRR_VVV000M }, | |
1477 | { "vgfma", 0xbc, INSTR_VRR_VVVM00V }, | |
1478 | { "vlc", 0xde, INSTR_VRR_VV0000M }, | |
1479 | { "vlp", 0xdf, INSTR_VRR_VV0000M }, | |
1480 | { "vmx", 0xff, INSTR_VRR_VVV000M }, | |
1481 | { "vmxl", 0xfd, INSTR_VRR_VVV000M }, | |
1482 | { "vmn", 0xfe, INSTR_VRR_VVV000M }, | |
1483 | { "vmnl", 0xfc, INSTR_VRR_VVV000M }, | |
1484 | { "vmal", 0xaa, INSTR_VRR_VVVM00V }, | |
1485 | { "vmae", 0xae, INSTR_VRR_VVVM00V }, | |
1486 | { "vmale", 0xac, INSTR_VRR_VVVM00V }, | |
1487 | { "vmah", 0xab, INSTR_VRR_VVVM00V }, | |
1488 | { "vmalh", 0xa9, INSTR_VRR_VVVM00V }, | |
1489 | { "vmao", 0xaf, INSTR_VRR_VVVM00V }, | |
1490 | { "vmalo", 0xad, INSTR_VRR_VVVM00V }, | |
1491 | { "vmh", 0xa3, INSTR_VRR_VVV000M }, | |
1492 | { "vmlh", 0xa1, INSTR_VRR_VVV000M }, | |
1493 | { "vml", 0xa2, INSTR_VRR_VVV000M }, | |
1494 | { "vme", 0xa6, INSTR_VRR_VVV000M }, | |
1495 | { "vmle", 0xa4, INSTR_VRR_VVV000M }, | |
1496 | { "vmo", 0xa7, INSTR_VRR_VVV000M }, | |
1497 | { "vmlo", 0xa5, INSTR_VRR_VVV000M }, | |
1498 | { "vno", 0x6b, INSTR_VRR_VVV0000 }, | |
1499 | { "vo", 0x6a, INSTR_VRR_VVV0000 }, | |
1500 | { { 0, LONG_INSN_VPOPCT }, 0x50, INSTR_VRR_VV0000M }, | |
1501 | { { 0, LONG_INSN_VERLLV }, 0x73, INSTR_VRR_VVV000M }, | |
1502 | { "verll", 0x33, INSTR_VRS_VVRDM }, | |
1503 | { "verim", 0x72, INSTR_VRI_VVV0IM }, | |
1504 | { "veslv", 0x70, INSTR_VRR_VVV000M }, | |
1505 | { "vesl", 0x30, INSTR_VRS_VVRDM }, | |
1506 | { { 0, LONG_INSN_VESRAV }, 0x7a, INSTR_VRR_VVV000M }, | |
1507 | { "vesra", 0x3a, INSTR_VRS_VVRDM }, | |
1508 | { { 0, LONG_INSN_VESRLV }, 0x78, INSTR_VRR_VVV000M }, | |
1509 | { "vesrl", 0x38, INSTR_VRS_VVRDM }, | |
1510 | { "vsl", 0x74, INSTR_VRR_VVV0000 }, | |
1511 | { "vslb", 0x75, INSTR_VRR_VVV0000 }, | |
1512 | { "vsldb", 0x77, INSTR_VRI_VVV0I0 }, | |
1513 | { "vsra", 0x7e, INSTR_VRR_VVV0000 }, | |
1514 | { "vsrab", 0x7f, INSTR_VRR_VVV0000 }, | |
1515 | { "vsrl", 0x7c, INSTR_VRR_VVV0000 }, | |
1516 | { "vsrlb", 0x7d, INSTR_VRR_VVV0000 }, | |
1517 | { "vs", 0xf7, INSTR_VRR_VVV000M }, | |
1518 | { "vscb", 0xf5, INSTR_VRR_VVV000M }, | |
1519 | { "vsb", 0xbf, INSTR_VRR_VVVM00V }, | |
1520 | { { 0, LONG_INSN_VSBCBI }, 0xbd, INSTR_VRR_VVVM00V }, | |
1521 | { "vsumg", 0x65, INSTR_VRR_VVV000M }, | |
1522 | { "vsumq", 0x67, INSTR_VRR_VVV000M }, | |
1523 | { "vsum", 0x64, INSTR_VRR_VVV000M }, | |
1524 | { "vtm", 0xd8, INSTR_VRR_VV00000 }, | |
1525 | { "vfae", 0x82, INSTR_VRR_VVV0M0M }, | |
1526 | { "vfee", 0x80, INSTR_VRR_VVV0M0M }, | |
1527 | { "vfene", 0x81, INSTR_VRR_VVV0M0M }, | |
1528 | { "vistr", 0x5c, INSTR_VRR_VV00M0M }, | |
1529 | { "vstrc", 0x8a, INSTR_VRR_VVVMM0V }, | |
1530 | { "vfa", 0xe3, INSTR_VRR_VVV00MM }, | |
1531 | { "wfc", 0xcb, INSTR_VRR_VV000MM }, | |
1532 | { "wfk", 0xca, INSTR_VRR_VV000MM }, | |
1533 | { "vfce", 0xe8, INSTR_VRR_VVV0MMM }, | |
1534 | { "vfch", 0xeb, INSTR_VRR_VVV0MMM }, | |
1535 | { "vfche", 0xea, INSTR_VRR_VVV0MMM }, | |
1536 | { "vcdg", 0xc3, INSTR_VRR_VV00MMM }, | |
1537 | { "vcdlg", 0xc1, INSTR_VRR_VV00MMM }, | |
1538 | { "vcgd", 0xc2, INSTR_VRR_VV00MMM }, | |
1539 | { "vclgd", 0xc0, INSTR_VRR_VV00MMM }, | |
1540 | { "vfd", 0xe5, INSTR_VRR_VVV00MM }, | |
1541 | { "vfi", 0xc7, INSTR_VRR_VV00MMM }, | |
1542 | { "vlde", 0xc4, INSTR_VRR_VV000MM }, | |
1543 | { "vled", 0xc5, INSTR_VRR_VV00MMM }, | |
1544 | { "vfm", 0xe7, INSTR_VRR_VVV00MM }, | |
1545 | { "vfma", 0x8f, INSTR_VRR_VVVM0MV }, | |
1546 | { "vfms", 0x8e, INSTR_VRR_VVVM0MV }, | |
1547 | { "vfpso", 0xcc, INSTR_VRR_VV00MMM }, | |
1548 | { "vfsq", 0xce, INSTR_VRR_VV000MM }, | |
1549 | { "vfs", 0xe2, INSTR_VRR_VVV00MM }, | |
1550 | { "vftci", 0x4a, INSTR_VRI_VVIMM }, | |
1551 | }; | |
1552 | ||
1553 | static struct s390_insn opcode_eb[] = { | |
1554 | { "lmg", 0x04, INSTR_RSY_RRRD }, | |
1555 | { "srag", 0x0a, INSTR_RSY_RRRD }, | |
1556 | { "slag", 0x0b, INSTR_RSY_RRRD }, | |
1557 | { "srlg", 0x0c, INSTR_RSY_RRRD }, | |
1558 | { "sllg", 0x0d, INSTR_RSY_RRRD }, | |
1559 | { "tracg", 0x0f, INSTR_RSY_RRRD }, | |
1560 | { "csy", 0x14, INSTR_RSY_RRRD }, | |
1561 | { "rllg", 0x1c, INSTR_RSY_RRRD }, | |
1562 | { "clmh", 0x20, INSTR_RSY_RURD }, | |
1563 | { "clmy", 0x21, INSTR_RSY_RURD }, | |
1564 | { "clt", 0x23, INSTR_RSY_RURD }, | |
1565 | { "stmg", 0x24, INSTR_RSY_RRRD }, | |
1566 | { "stctg", 0x25, INSTR_RSY_CCRD }, | |
1567 | { "stmh", 0x26, INSTR_RSY_RRRD }, | |
1568 | { "clgt", 0x2b, INSTR_RSY_RURD }, | |
1569 | { "stcmh", 0x2c, INSTR_RSY_RURD }, | |
1570 | { "stcmy", 0x2d, INSTR_RSY_RURD }, | |
1571 | { "lctlg", 0x2f, INSTR_RSY_CCRD }, | |
1572 | { "csg", 0x30, INSTR_RSY_RRRD }, | |
1573 | { "cdsy", 0x31, INSTR_RSY_RRRD }, | |
1574 | { "cdsg", 0x3e, INSTR_RSY_RRRD }, | |
1575 | { "bxhg", 0x44, INSTR_RSY_RRRD }, | |
1576 | { "bxleg", 0x45, INSTR_RSY_RRRD }, | |
1577 | { "ecag", 0x4c, INSTR_RSY_RRRD }, | |
1578 | { "tmy", 0x51, INSTR_SIY_URD }, | |
1579 | { "mviy", 0x52, INSTR_SIY_URD }, | |
1580 | { "niy", 0x54, INSTR_SIY_URD }, | |
1581 | { "cliy", 0x55, INSTR_SIY_URD }, | |
1582 | { "oiy", 0x56, INSTR_SIY_URD }, | |
1583 | { "xiy", 0x57, INSTR_SIY_URD }, | |
1584 | { "asi", 0x6a, INSTR_SIY_IRD }, | |
1585 | { "alsi", 0x6e, INSTR_SIY_IRD }, | |
1586 | { "agsi", 0x7a, INSTR_SIY_IRD }, | |
1587 | { "algsi", 0x7e, INSTR_SIY_IRD }, | |
1588 | { "icmh", 0x80, INSTR_RSY_RURD }, | |
1589 | { "icmy", 0x81, INSTR_RSY_RURD }, | |
1590 | { "clclu", 0x8f, INSTR_RSY_RRRD }, | |
1591 | { "stmy", 0x90, INSTR_RSY_RRRD }, | |
1592 | { "lmh", 0x96, INSTR_RSY_RRRD }, | |
1593 | { "lmy", 0x98, INSTR_RSY_RRRD }, | |
1594 | { "lamy", 0x9a, INSTR_RSY_AARD }, | |
1595 | { "stamy", 0x9b, INSTR_RSY_AARD }, | |
1596 | { { 0, LONG_INSN_PCISTB }, 0xd0, INSTR_RSY_RRRD }, | |
1597 | { "sic", 0xd1, INSTR_RSY_RRRD }, | |
1598 | { "srak", 0xdc, INSTR_RSY_RRRD }, | |
1599 | { "slak", 0xdd, INSTR_RSY_RRRD }, | |
1600 | { "srlk", 0xde, INSTR_RSY_RRRD }, | |
1601 | { "sllk", 0xdf, INSTR_RSY_RRRD }, | |
1602 | { "locg", 0xe2, INSTR_RSY_RDRM }, | |
1603 | { "stocg", 0xe3, INSTR_RSY_RDRM }, | |
1604 | { "lang", 0xe4, INSTR_RSY_RRRD }, | |
1605 | { "laog", 0xe6, INSTR_RSY_RRRD }, | |
1606 | { "laxg", 0xe7, INSTR_RSY_RRRD }, | |
1607 | { "laag", 0xe8, INSTR_RSY_RRRD }, | |
1608 | { "laalg", 0xea, INSTR_RSY_RRRD }, | |
1609 | { "loc", 0xf2, INSTR_RSY_RDRM }, | |
1610 | { "stoc", 0xf3, INSTR_RSY_RDRM }, | |
1611 | { "lan", 0xf4, INSTR_RSY_RRRD }, | |
1612 | { "lao", 0xf6, INSTR_RSY_RRRD }, | |
1613 | { "lax", 0xf7, INSTR_RSY_RRRD }, | |
1614 | { "laa", 0xf8, INSTR_RSY_RRRD }, | |
1615 | { "laal", 0xfa, INSTR_RSY_RRRD }, | |
1616 | { "lric", 0x60, INSTR_RSY_RDRM }, | |
1617 | { "stric", 0x61, INSTR_RSY_RDRM }, | |
1618 | { "mric", 0x62, INSTR_RSY_RDRM }, | |
1619 | { { 0, LONG_INSN_STCCTM }, 0x17, INSTR_RSY_RMRD }, | |
1620 | { "rll", 0x1d, INSTR_RSY_RRRD }, | |
1621 | { "mvclu", 0x8e, INSTR_RSY_RRRD }, | |
1622 | { "tp", 0xc0, INSTR_RSL_R0RD }, | |
1623 | { "", 0, INSTR_INVALID } | |
1624 | }; | |
1625 | ||
1626 | static struct s390_insn opcode_ec[] = { | |
1627 | { "brxhg", 0x44, INSTR_RIE_RRP }, | |
1628 | { "brxlg", 0x45, INSTR_RIE_RRP }, | |
1629 | { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU }, | |
1630 | { "rnsbg", 0x54, INSTR_RIE_RRUUU }, | |
1631 | { "risbg", 0x55, INSTR_RIE_RRUUU }, | |
1632 | { "rosbg", 0x56, INSTR_RIE_RRUUU }, | |
1633 | { "rxsbg", 0x57, INSTR_RIE_RRUUU }, | |
1634 | { { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU }, | |
1635 | { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU }, | |
1636 | { "cgrj", 0x64, INSTR_RIE_RRPU }, | |
1637 | { "clgrj", 0x65, INSTR_RIE_RRPU }, | |
1638 | { "cgit", 0x70, INSTR_RIE_R0IU }, | |
1639 | { "clgit", 0x71, INSTR_RIE_R0UU }, | |
1640 | { "cit", 0x72, INSTR_RIE_R0IU }, | |
1641 | { "clfit", 0x73, INSTR_RIE_R0UU }, | |
1642 | { "crj", 0x76, INSTR_RIE_RRPU }, | |
1643 | { "clrj", 0x77, INSTR_RIE_RRPU }, | |
1644 | { "cgij", 0x7c, INSTR_RIE_RUPI }, | |
1645 | { "clgij", 0x7d, INSTR_RIE_RUPU }, | |
1646 | { "cij", 0x7e, INSTR_RIE_RUPI }, | |
1647 | { "clij", 0x7f, INSTR_RIE_RUPU }, | |
1648 | { "ahik", 0xd8, INSTR_RIE_RRI0 }, | |
1649 | { "aghik", 0xd9, INSTR_RIE_RRI0 }, | |
1650 | { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, | |
1651 | { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, | |
1652 | { "cgrb", 0xe4, INSTR_RRS_RRRDU }, | |
1653 | { "clgrb", 0xe5, INSTR_RRS_RRRDU }, | |
1654 | { "crb", 0xf6, INSTR_RRS_RRRDU }, | |
1655 | { "clrb", 0xf7, INSTR_RRS_RRRDU }, | |
1656 | { "cgib", 0xfc, INSTR_RIS_RURDI }, | |
1657 | { "clgib", 0xfd, INSTR_RIS_RURDU }, | |
1658 | { "cib", 0xfe, INSTR_RIS_RURDI }, | |
1659 | { "clib", 0xff, INSTR_RIS_RURDU }, | |
1660 | { "", 0, INSTR_INVALID } | |
1661 | }; | |
1662 | ||
1663 | static struct s390_insn opcode_ed[] = { | |
1664 | { "mayl", 0x38, INSTR_RXF_FRRDF }, | |
1665 | { "myl", 0x39, INSTR_RXF_FRRDF }, | |
1666 | { "may", 0x3a, INSTR_RXF_FRRDF }, | |
1667 | { "my", 0x3b, INSTR_RXF_FRRDF }, | |
1668 | { "mayh", 0x3c, INSTR_RXF_FRRDF }, | |
1669 | { "myh", 0x3d, INSTR_RXF_FRRDF }, | |
1670 | { "sldt", 0x40, INSTR_RXF_FRRDF }, | |
1671 | { "srdt", 0x41, INSTR_RXF_FRRDF }, | |
1672 | { "slxt", 0x48, INSTR_RXF_FRRDF }, | |
1673 | { "srxt", 0x49, INSTR_RXF_FRRDF }, | |
1674 | { "tdcet", 0x50, INSTR_RXE_FRRD }, | |
1675 | { "tdget", 0x51, INSTR_RXE_FRRD }, | |
1676 | { "tdcdt", 0x54, INSTR_RXE_FRRD }, | |
1677 | { "tdgdt", 0x55, INSTR_RXE_FRRD }, | |
1678 | { "tdcxt", 0x58, INSTR_RXE_FRRD }, | |
1679 | { "tdgxt", 0x59, INSTR_RXE_FRRD }, | |
1680 | { "ley", 0x64, INSTR_RXY_FRRD }, | |
1681 | { "ldy", 0x65, INSTR_RXY_FRRD }, | |
1682 | { "stey", 0x66, INSTR_RXY_FRRD }, | |
1683 | { "stdy", 0x67, INSTR_RXY_FRRD }, | |
1684 | { "czdt", 0xa8, INSTR_RSL_LRDFU }, | |
1685 | { "czxt", 0xa9, INSTR_RSL_LRDFU }, | |
1686 | { "cdzt", 0xaa, INSTR_RSL_LRDFU }, | |
1687 | { "cxzt", 0xab, INSTR_RSL_LRDFU }, | |
1688 | { "ldeb", 0x04, INSTR_RXE_FRRD }, | |
1689 | { "lxdb", 0x05, INSTR_RXE_FRRD }, | |
1690 | { "lxeb", 0x06, INSTR_RXE_FRRD }, | |
1691 | { "mxdb", 0x07, INSTR_RXE_FRRD }, | |
1692 | { "keb", 0x08, INSTR_RXE_FRRD }, | |
1693 | { "ceb", 0x09, INSTR_RXE_FRRD }, | |
1694 | { "aeb", 0x0a, INSTR_RXE_FRRD }, | |
1695 | { "seb", 0x0b, INSTR_RXE_FRRD }, | |
1696 | { "mdeb", 0x0c, INSTR_RXE_FRRD }, | |
1697 | { "deb", 0x0d, INSTR_RXE_FRRD }, | |
1698 | { "maeb", 0x0e, INSTR_RXF_FRRDF }, | |
1699 | { "mseb", 0x0f, INSTR_RXF_FRRDF }, | |
1700 | { "tceb", 0x10, INSTR_RXE_FRRD }, | |
1701 | { "tcdb", 0x11, INSTR_RXE_FRRD }, | |
1702 | { "tcxb", 0x12, INSTR_RXE_FRRD }, | |
1703 | { "sqeb", 0x14, INSTR_RXE_FRRD }, | |
1704 | { "sqdb", 0x15, INSTR_RXE_FRRD }, | |
1705 | { "meeb", 0x17, INSTR_RXE_FRRD }, | |
1706 | { "kdb", 0x18, INSTR_RXE_FRRD }, | |
1707 | { "cdb", 0x19, INSTR_RXE_FRRD }, | |
1708 | { "adb", 0x1a, INSTR_RXE_FRRD }, | |
1709 | { "sdb", 0x1b, INSTR_RXE_FRRD }, | |
1710 | { "mdb", 0x1c, INSTR_RXE_FRRD }, | |
1711 | { "ddb", 0x1d, INSTR_RXE_FRRD }, | |
1712 | { "madb", 0x1e, INSTR_RXF_FRRDF }, | |
1713 | { "msdb", 0x1f, INSTR_RXF_FRRDF }, | |
1714 | { "lde", 0x24, INSTR_RXE_FRRD }, | |
1715 | { "lxd", 0x25, INSTR_RXE_FRRD }, | |
1716 | { "lxe", 0x26, INSTR_RXE_FRRD }, | |
1717 | { "mae", 0x2e, INSTR_RXF_FRRDF }, | |
1718 | { "mse", 0x2f, INSTR_RXF_FRRDF }, | |
1719 | { "sqe", 0x34, INSTR_RXE_FRRD }, | |
1720 | { "sqd", 0x35, INSTR_RXE_FRRD }, | |
1721 | { "mee", 0x37, INSTR_RXE_FRRD }, | |
1722 | { "mad", 0x3e, INSTR_RXF_FRRDF }, | |
1723 | { "msd", 0x3f, INSTR_RXF_FRRDF }, | |
1724 | { "", 0, INSTR_INVALID } | |
1725 | }; | |
1726 | ||
1727 | /* Extracts an operand value from an instruction. */ | |
1728 | static unsigned int extract_operand(unsigned char *code, | |
1729 | const struct s390_operand *operand) | |
1730 | { | |
1731 | unsigned char *cp; | |
1732 | unsigned int val; | |
1733 | int bits; | |
1734 | ||
1735 | /* Extract fragments of the operand byte for byte. */ | |
1736 | cp = code + operand->shift / 8; | |
1737 | bits = (operand->shift & 7) + operand->bits; | |
1738 | val = 0; | |
1739 | do { | |
1740 | val <<= 8; | |
1741 | val |= (unsigned int) *cp++; | |
1742 | bits -= 8; | |
1743 | } while (bits > 0); | |
1744 | val >>= -bits; | |
1745 | val &= ((1U << (operand->bits - 1)) << 1) - 1; | |
1746 | ||
1747 | /* Check for special long displacement case. */ | |
1748 | if (operand->bits == 20 && operand->shift == 20) | |
1749 | val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; | |
1750 | ||
1751 | /* Check for register extensions bits for vector registers. */ | |
1752 | if (operand->flags & OPERAND_VR) { | |
1753 | if (operand->shift == 8) | |
1754 | val |= (code[4] & 8) << 1; | |
1755 | else if (operand->shift == 12) | |
1756 | val |= (code[4] & 4) << 2; | |
1757 | else if (operand->shift == 16) | |
1758 | val |= (code[4] & 2) << 3; | |
1759 | else if (operand->shift == 32) | |
1760 | val |= (code[4] & 1) << 4; | |
1761 | } | |
1762 | ||
1763 | /* Sign extend value if the operand is signed or pc relative. */ | |
1764 | if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && | |
1765 | (val & (1U << (operand->bits - 1)))) | |
1766 | val |= (-1U << (operand->bits - 1)) << 1; | |
1767 | ||
1768 | /* Double value if the operand is pc relative. */ | |
1769 | if (operand->flags & OPERAND_PCREL) | |
1770 | val <<= 1; | |
1771 | ||
1772 | /* Length x in an instructions has real length x + 1. */ | |
1773 | if (operand->flags & OPERAND_LENGTH) | |
1774 | val++; | |
1775 | return val; | |
1776 | } | |
1777 | ||
1778 | struct s390_insn *find_insn(unsigned char *code) | |
1779 | { | |
1780 | unsigned char opfrag = code[1]; | |
1781 | unsigned char opmask; | |
1782 | struct s390_insn *table; | |
1783 | ||
1784 | switch (code[0]) { | |
1785 | case 0x01: | |
1786 | table = opcode_01; | |
1787 | break; | |
1788 | case 0xa5: | |
1789 | table = opcode_a5; | |
1790 | break; | |
1791 | case 0xa7: | |
1792 | table = opcode_a7; | |
1793 | break; | |
1794 | case 0xaa: | |
1795 | table = opcode_aa; | |
1796 | break; | |
1797 | case 0xb2: | |
1798 | table = opcode_b2; | |
1799 | break; | |
1800 | case 0xb3: | |
1801 | table = opcode_b3; | |
1802 | break; | |
1803 | case 0xb9: | |
1804 | table = opcode_b9; | |
1805 | break; | |
1806 | case 0xc0: | |
1807 | table = opcode_c0; | |
1808 | break; | |
1809 | case 0xc2: | |
1810 | table = opcode_c2; | |
1811 | break; | |
1812 | case 0xc4: | |
1813 | table = opcode_c4; | |
1814 | break; | |
1815 | case 0xc6: | |
1816 | table = opcode_c6; | |
1817 | break; | |
1818 | case 0xc8: | |
1819 | table = opcode_c8; | |
1820 | break; | |
1821 | case 0xcc: | |
1822 | table = opcode_cc; | |
1823 | break; | |
1824 | case 0xe3: | |
1825 | table = opcode_e3; | |
1826 | opfrag = code[5]; | |
1827 | break; | |
1828 | case 0xe5: | |
1829 | table = opcode_e5; | |
1830 | break; | |
1831 | case 0xe7: | |
1832 | table = opcode_e7; | |
1833 | opfrag = code[5]; | |
1834 | break; | |
1835 | case 0xeb: | |
1836 | table = opcode_eb; | |
1837 | opfrag = code[5]; | |
1838 | break; | |
1839 | case 0xec: | |
1840 | table = opcode_ec; | |
1841 | opfrag = code[5]; | |
1842 | break; | |
1843 | case 0xed: | |
1844 | table = opcode_ed; | |
1845 | opfrag = code[5]; | |
1846 | break; | |
1847 | default: | |
1848 | table = opcode; | |
1849 | opfrag = code[0]; | |
1850 | break; | |
1851 | } | |
1852 | while (table->format != INSTR_INVALID) { | |
1853 | opmask = formats[table->format][0]; | |
1854 | if (table->opfrag == (opfrag & opmask)) | |
1855 | return table; | |
1856 | table++; | |
1857 | } | |
1858 | return NULL; | |
1859 | } | |
1860 | ||
1861 | /** | |
1862 | * insn_to_mnemonic - decode an s390 instruction | |
1863 | * @instruction: instruction to decode | |
1864 | * @buf: buffer to fill with mnemonic | |
1865 | * @len: length of buffer | |
1866 | * | |
1867 | * Decode the instruction at @instruction and store the corresponding | |
1868 | * mnemonic into @buf of length @len. | |
1869 | * @buf is left unchanged if the instruction could not be decoded. | |
1870 | * Returns: | |
1871 | * %0 on success, %-ENOENT if the instruction was not found. | |
1872 | */ | |
1873 | int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len) | |
1874 | { | |
1875 | struct s390_insn *insn; | |
1876 | ||
1877 | insn = find_insn(instruction); | |
1878 | if (!insn) | |
1879 | return -ENOENT; | |
1880 | if (insn->name[0] == '\0') | |
1881 | snprintf(buf, len, "%s", | |
1882 | long_insn_name[(int) insn->name[1]]); | |
1883 | else | |
1884 | snprintf(buf, len, "%.5s", insn->name); | |
1885 | return 0; | |
1886 | } | |
1887 | EXPORT_SYMBOL_GPL(insn_to_mnemonic); | |
1888 | ||
1889 | static int print_insn(char *buffer, unsigned char *code, unsigned long addr) | |
1890 | { | |
1891 | struct s390_insn *insn; | |
1892 | const unsigned char *ops; | |
1893 | const struct s390_operand *operand; | |
1894 | unsigned int value; | |
1895 | char separator; | |
1896 | char *ptr; | |
1897 | int i; | |
1898 | ||
1899 | ptr = buffer; | |
1900 | insn = find_insn(code); | |
1901 | if (insn) { | |
1902 | if (insn->name[0] == '\0') | |
1903 | ptr += sprintf(ptr, "%s\t", | |
1904 | long_insn_name[(int) insn->name[1]]); | |
1905 | else | |
1906 | ptr += sprintf(ptr, "%.5s\t", insn->name); | |
1907 | /* Extract the operands. */ | |
1908 | separator = 0; | |
1909 | for (ops = formats[insn->format] + 1, i = 0; | |
1910 | *ops != 0 && i < 6; ops++, i++) { | |
1911 | operand = operands + *ops; | |
1912 | value = extract_operand(code, operand); | |
1913 | if ((operand->flags & OPERAND_INDEX) && value == 0) | |
1914 | continue; | |
1915 | if ((operand->flags & OPERAND_BASE) && | |
1916 | value == 0 && separator == '(') { | |
1917 | separator = ','; | |
1918 | continue; | |
1919 | } | |
1920 | if (separator) | |
1921 | ptr += sprintf(ptr, "%c", separator); | |
1922 | if (operand->flags & OPERAND_GPR) | |
1923 | ptr += sprintf(ptr, "%%r%i", value); | |
1924 | else if (operand->flags & OPERAND_FPR) | |
1925 | ptr += sprintf(ptr, "%%f%i", value); | |
1926 | else if (operand->flags & OPERAND_AR) | |
1927 | ptr += sprintf(ptr, "%%a%i", value); | |
1928 | else if (operand->flags & OPERAND_CR) | |
1929 | ptr += sprintf(ptr, "%%c%i", value); | |
1930 | else if (operand->flags & OPERAND_VR) | |
1931 | ptr += sprintf(ptr, "%%v%i", value); | |
1932 | else if (operand->flags & OPERAND_PCREL) | |
1933 | ptr += sprintf(ptr, "%lx", (signed int) value | |
1934 | + addr); | |
1935 | else if (operand->flags & OPERAND_SIGNED) | |
1936 | ptr += sprintf(ptr, "%i", value); | |
1937 | else | |
1938 | ptr += sprintf(ptr, "%u", value); | |
1939 | if (operand->flags & OPERAND_DISP) | |
1940 | separator = '('; | |
1941 | else if (operand->flags & OPERAND_BASE) { | |
1942 | ptr += sprintf(ptr, ")"); | |
1943 | separator = ','; | |
1944 | } else | |
1945 | separator = ','; | |
1946 | } | |
1947 | } else | |
1948 | ptr += sprintf(ptr, "unknown"); | |
1949 | return (int) (ptr - buffer); | |
1950 | } | |
1951 | ||
1952 | void show_code(struct pt_regs *regs) | |
1953 | { | |
1954 | char *mode = user_mode(regs) ? "User" : "Krnl"; | |
1955 | unsigned char code[64]; | |
1956 | char buffer[64], *ptr; | |
1957 | mm_segment_t old_fs; | |
1958 | unsigned long addr; | |
1959 | int start, end, opsize, hops, i; | |
1960 | ||
1961 | /* Get a snapshot of the 64 bytes surrounding the fault address. */ | |
1962 | old_fs = get_fs(); | |
1963 | set_fs(user_mode(regs) ? USER_DS : KERNEL_DS); | |
1964 | for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { | |
1965 | addr = regs->psw.addr - 34 + start; | |
1966 | if (__copy_from_user(code + start - 2, | |
1967 | (char __user *) addr, 2)) | |
1968 | break; | |
1969 | } | |
1970 | for (end = 32; end < 64; end += 2) { | |
1971 | addr = regs->psw.addr + end - 32; | |
1972 | if (__copy_from_user(code + end, | |
1973 | (char __user *) addr, 2)) | |
1974 | break; | |
1975 | } | |
1976 | set_fs(old_fs); | |
1977 | /* Code snapshot useable ? */ | |
1978 | if ((regs->psw.addr & 1) || start >= end) { | |
1979 | printk("%s Code: Bad PSW.\n", mode); | |
1980 | return; | |
1981 | } | |
1982 | /* Find a starting point for the disassembly. */ | |
1983 | while (start < 32) { | |
1984 | for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { | |
1985 | if (!find_insn(code + start + i)) | |
1986 | break; | |
1987 | i += insn_length(code[start + i]); | |
1988 | } | |
1989 | if (start + i == 32) | |
1990 | /* Looks good, sequence ends at PSW. */ | |
1991 | break; | |
1992 | start += 2; | |
1993 | } | |
1994 | /* Decode the instructions. */ | |
1995 | ptr = buffer; | |
1996 | ptr += sprintf(ptr, "%s Code:", mode); | |
1997 | hops = 0; | |
1998 | while (start < end && hops < 8) { | |
1999 | opsize = insn_length(code[start]); | |
2000 | if (start + opsize == 32) | |
2001 | *ptr++ = '#'; | |
2002 | else if (start == 32) | |
2003 | *ptr++ = '>'; | |
2004 | else | |
2005 | *ptr++ = ' '; | |
2006 | addr = regs->psw.addr + start - 32; | |
2007 | ptr += sprintf(ptr, "%016lx: ", addr); | |
2008 | if (start + opsize >= end) | |
2009 | break; | |
2010 | for (i = 0; i < opsize; i++) | |
2011 | ptr += sprintf(ptr, "%02x", code[start + i]); | |
2012 | *ptr++ = '\t'; | |
2013 | if (i < 6) | |
2014 | *ptr++ = '\t'; | |
2015 | ptr += print_insn(ptr, code + start, addr); | |
2016 | start += opsize; | |
2017 | pr_cont("%s", buffer); | |
2018 | ptr = buffer; | |
2019 | ptr += sprintf(ptr, "\n "); | |
2020 | hops++; | |
2021 | } | |
2022 | pr_cont("\n"); | |
2023 | } | |
2024 | ||
2025 | void print_fn_code(unsigned char *code, unsigned long len) | |
2026 | { | |
2027 | char buffer[64], *ptr; | |
2028 | int opsize, i; | |
2029 | ||
2030 | while (len) { | |
2031 | ptr = buffer; | |
2032 | opsize = insn_length(*code); | |
2033 | if (opsize > len) | |
2034 | break; | |
2035 | ptr += sprintf(ptr, "%p: ", code); | |
2036 | for (i = 0; i < opsize; i++) | |
2037 | ptr += sprintf(ptr, "%02x", code[i]); | |
2038 | *ptr++ = '\t'; | |
2039 | if (i < 4) | |
2040 | *ptr++ = '\t'; | |
2041 | ptr += print_insn(ptr, code, (unsigned long) code); | |
2042 | *ptr++ = '\n'; | |
2043 | *ptr++ = 0; | |
2044 | printk("%s", buffer); | |
2045 | code += opsize; | |
2046 | len -= opsize; | |
2047 | } | |
2048 | } |