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1 | /* | |
2 | * SH7757 Setup | |
3 | * | |
4 | * Copyright (C) 2009, 2011 Renesas Solutions Corp. | |
5 | * | |
6 | * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/serial.h> | |
15 | #include <linux/serial_sci.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/sh_timer.h> | |
20 | #include <linux/sh_dma.h> | |
21 | #include <linux/sh_intc.h> | |
22 | #include <linux/usb/ohci_pdriver.h> | |
23 | #include <cpu/dma-register.h> | |
24 | #include <cpu/sh7757.h> | |
25 | ||
26 | static struct plat_sci_port scif2_platform_data = { | |
27 | .flags = UPF_BOOT_AUTOCONF, | |
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | |
29 | .type = PORT_SCIF, | |
30 | }; | |
31 | ||
32 | static struct resource scif2_resources[] = { | |
33 | DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ | |
34 | DEFINE_RES_IRQ(evt2irq(0x700)), | |
35 | }; | |
36 | ||
37 | static struct platform_device scif2_device = { | |
38 | .name = "sh-sci", | |
39 | .id = 0, | |
40 | .resource = scif2_resources, | |
41 | .num_resources = ARRAY_SIZE(scif2_resources), | |
42 | .dev = { | |
43 | .platform_data = &scif2_platform_data, | |
44 | }, | |
45 | }; | |
46 | ||
47 | static struct plat_sci_port scif3_platform_data = { | |
48 | .flags = UPF_BOOT_AUTOCONF, | |
49 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | |
50 | .type = PORT_SCIF, | |
51 | }; | |
52 | ||
53 | static struct resource scif3_resources[] = { | |
54 | DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ | |
55 | DEFINE_RES_IRQ(evt2irq(0xb80)), | |
56 | }; | |
57 | ||
58 | static struct platform_device scif3_device = { | |
59 | .name = "sh-sci", | |
60 | .id = 1, | |
61 | .resource = scif3_resources, | |
62 | .num_resources = ARRAY_SIZE(scif3_resources), | |
63 | .dev = { | |
64 | .platform_data = &scif3_platform_data, | |
65 | }, | |
66 | }; | |
67 | ||
68 | static struct plat_sci_port scif4_platform_data = { | |
69 | .flags = UPF_BOOT_AUTOCONF, | |
70 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | |
71 | .type = PORT_SCIF, | |
72 | }; | |
73 | ||
74 | static struct resource scif4_resources[] = { | |
75 | DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ | |
76 | DEFINE_RES_IRQ(evt2irq(0xf00)), | |
77 | }; | |
78 | ||
79 | static struct platform_device scif4_device = { | |
80 | .name = "sh-sci", | |
81 | .id = 2, | |
82 | .resource = scif4_resources, | |
83 | .num_resources = ARRAY_SIZE(scif4_resources), | |
84 | .dev = { | |
85 | .platform_data = &scif4_platform_data, | |
86 | }, | |
87 | }; | |
88 | ||
89 | static struct sh_timer_config tmu0_platform_data = { | |
90 | .channels_mask = 3, | |
91 | }; | |
92 | ||
93 | static struct resource tmu0_resources[] = { | |
94 | DEFINE_RES_MEM(0xfe430000, 0x20), | |
95 | DEFINE_RES_IRQ(evt2irq(0x580)), | |
96 | DEFINE_RES_IRQ(evt2irq(0x5a0)), | |
97 | }; | |
98 | ||
99 | static struct platform_device tmu0_device = { | |
100 | .name = "sh-tmu", | |
101 | .id = 0, | |
102 | .dev = { | |
103 | .platform_data = &tmu0_platform_data, | |
104 | }, | |
105 | .resource = tmu0_resources, | |
106 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
107 | }; | |
108 | ||
109 | static struct resource spi0_resources[] = { | |
110 | [0] = { | |
111 | .start = 0xfe002000, | |
112 | .end = 0xfe0020ff, | |
113 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, | |
114 | }, | |
115 | [1] = { | |
116 | .start = evt2irq(0xcc0), | |
117 | .flags = IORESOURCE_IRQ, | |
118 | }, | |
119 | }; | |
120 | ||
121 | /* DMA */ | |
122 | static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { | |
123 | { | |
124 | .slave_id = SHDMA_SLAVE_SDHI_TX, | |
125 | .addr = 0x1fe50030, | |
126 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
127 | TS_INDEX2VAL(XMIT_SZ_16BIT), | |
128 | .mid_rid = 0xc5, | |
129 | }, | |
130 | { | |
131 | .slave_id = SHDMA_SLAVE_SDHI_RX, | |
132 | .addr = 0x1fe50030, | |
133 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
134 | TS_INDEX2VAL(XMIT_SZ_16BIT), | |
135 | .mid_rid = 0xc6, | |
136 | }, | |
137 | { | |
138 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
139 | .addr = 0x1fcb0034, | |
140 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
141 | TS_INDEX2VAL(XMIT_SZ_32BIT), | |
142 | .mid_rid = 0xd3, | |
143 | }, | |
144 | { | |
145 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
146 | .addr = 0x1fcb0034, | |
147 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
148 | TS_INDEX2VAL(XMIT_SZ_32BIT), | |
149 | .mid_rid = 0xd7, | |
150 | }, | |
151 | }; | |
152 | ||
153 | static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { | |
154 | { | |
155 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
156 | .addr = 0x1f4b000c, | |
157 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
158 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
159 | .mid_rid = 0x21, | |
160 | }, | |
161 | { | |
162 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
163 | .addr = 0x1f4b0014, | |
164 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
165 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
166 | .mid_rid = 0x22, | |
167 | }, | |
168 | { | |
169 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | |
170 | .addr = 0x1f4c000c, | |
171 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
172 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
173 | .mid_rid = 0x29, | |
174 | }, | |
175 | { | |
176 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | |
177 | .addr = 0x1f4c0014, | |
178 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
179 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
180 | .mid_rid = 0x2a, | |
181 | }, | |
182 | { | |
183 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | |
184 | .addr = 0x1f4d000c, | |
185 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
186 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
187 | .mid_rid = 0x41, | |
188 | }, | |
189 | { | |
190 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | |
191 | .addr = 0x1f4d0014, | |
192 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
193 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
194 | .mid_rid = 0x42, | |
195 | }, | |
196 | { | |
197 | .slave_id = SHDMA_SLAVE_RSPI_TX, | |
198 | .addr = 0xfe480004, | |
199 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
200 | TS_INDEX2VAL(XMIT_SZ_16BIT), | |
201 | .mid_rid = 0xc1, | |
202 | }, | |
203 | { | |
204 | .slave_id = SHDMA_SLAVE_RSPI_RX, | |
205 | .addr = 0xfe480004, | |
206 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
207 | TS_INDEX2VAL(XMIT_SZ_16BIT), | |
208 | .mid_rid = 0xc2, | |
209 | }, | |
210 | }; | |
211 | ||
212 | static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { | |
213 | { | |
214 | .slave_id = SHDMA_SLAVE_RIIC0_TX, | |
215 | .addr = 0x1e500012, | |
216 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
217 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
218 | .mid_rid = 0x21, | |
219 | }, | |
220 | { | |
221 | .slave_id = SHDMA_SLAVE_RIIC0_RX, | |
222 | .addr = 0x1e500013, | |
223 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
224 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
225 | .mid_rid = 0x22, | |
226 | }, | |
227 | { | |
228 | .slave_id = SHDMA_SLAVE_RIIC1_TX, | |
229 | .addr = 0x1e510012, | |
230 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
231 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
232 | .mid_rid = 0x29, | |
233 | }, | |
234 | { | |
235 | .slave_id = SHDMA_SLAVE_RIIC1_RX, | |
236 | .addr = 0x1e510013, | |
237 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
238 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
239 | .mid_rid = 0x2a, | |
240 | }, | |
241 | { | |
242 | .slave_id = SHDMA_SLAVE_RIIC2_TX, | |
243 | .addr = 0x1e520012, | |
244 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
245 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
246 | .mid_rid = 0xa1, | |
247 | }, | |
248 | { | |
249 | .slave_id = SHDMA_SLAVE_RIIC2_RX, | |
250 | .addr = 0x1e520013, | |
251 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
252 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
253 | .mid_rid = 0xa2, | |
254 | }, | |
255 | { | |
256 | .slave_id = SHDMA_SLAVE_RIIC3_TX, | |
257 | .addr = 0x1e530012, | |
258 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
259 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
260 | .mid_rid = 0xa9, | |
261 | }, | |
262 | { | |
263 | .slave_id = SHDMA_SLAVE_RIIC3_RX, | |
264 | .addr = 0x1e530013, | |
265 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
266 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
267 | .mid_rid = 0xaf, | |
268 | }, | |
269 | { | |
270 | .slave_id = SHDMA_SLAVE_RIIC4_TX, | |
271 | .addr = 0x1e540012, | |
272 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
273 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
274 | .mid_rid = 0xc5, | |
275 | }, | |
276 | { | |
277 | .slave_id = SHDMA_SLAVE_RIIC4_RX, | |
278 | .addr = 0x1e540013, | |
279 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
280 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
281 | .mid_rid = 0xc6, | |
282 | }, | |
283 | }; | |
284 | ||
285 | static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { | |
286 | { | |
287 | .slave_id = SHDMA_SLAVE_RIIC5_TX, | |
288 | .addr = 0x1e550012, | |
289 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
290 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
291 | .mid_rid = 0x21, | |
292 | }, | |
293 | { | |
294 | .slave_id = SHDMA_SLAVE_RIIC5_RX, | |
295 | .addr = 0x1e550013, | |
296 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
297 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
298 | .mid_rid = 0x22, | |
299 | }, | |
300 | { | |
301 | .slave_id = SHDMA_SLAVE_RIIC6_TX, | |
302 | .addr = 0x1e560012, | |
303 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
304 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
305 | .mid_rid = 0x29, | |
306 | }, | |
307 | { | |
308 | .slave_id = SHDMA_SLAVE_RIIC6_RX, | |
309 | .addr = 0x1e560013, | |
310 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
311 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
312 | .mid_rid = 0x2a, | |
313 | }, | |
314 | { | |
315 | .slave_id = SHDMA_SLAVE_RIIC7_TX, | |
316 | .addr = 0x1e570012, | |
317 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
318 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
319 | .mid_rid = 0x41, | |
320 | }, | |
321 | { | |
322 | .slave_id = SHDMA_SLAVE_RIIC7_RX, | |
323 | .addr = 0x1e570013, | |
324 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
325 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
326 | .mid_rid = 0x42, | |
327 | }, | |
328 | { | |
329 | .slave_id = SHDMA_SLAVE_RIIC8_TX, | |
330 | .addr = 0x1e580012, | |
331 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
332 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
333 | .mid_rid = 0x45, | |
334 | }, | |
335 | { | |
336 | .slave_id = SHDMA_SLAVE_RIIC8_RX, | |
337 | .addr = 0x1e580013, | |
338 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
339 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
340 | .mid_rid = 0x46, | |
341 | }, | |
342 | { | |
343 | .slave_id = SHDMA_SLAVE_RIIC9_TX, | |
344 | .addr = 0x1e590012, | |
345 | .chcr = SM_INC | RS_ERS | 0x40000000 | | |
346 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
347 | .mid_rid = 0x51, | |
348 | }, | |
349 | { | |
350 | .slave_id = SHDMA_SLAVE_RIIC9_RX, | |
351 | .addr = 0x1e590013, | |
352 | .chcr = DM_INC | RS_ERS | 0x40000000 | | |
353 | TS_INDEX2VAL(XMIT_SZ_8BIT), | |
354 | .mid_rid = 0x52, | |
355 | }, | |
356 | }; | |
357 | ||
358 | static const struct sh_dmae_channel sh7757_dmae_channels[] = { | |
359 | { | |
360 | .offset = 0, | |
361 | .dmars = 0, | |
362 | .dmars_bit = 0, | |
363 | }, { | |
364 | .offset = 0x10, | |
365 | .dmars = 0, | |
366 | .dmars_bit = 8, | |
367 | }, { | |
368 | .offset = 0x20, | |
369 | .dmars = 4, | |
370 | .dmars_bit = 0, | |
371 | }, { | |
372 | .offset = 0x30, | |
373 | .dmars = 4, | |
374 | .dmars_bit = 8, | |
375 | }, { | |
376 | .offset = 0x50, | |
377 | .dmars = 8, | |
378 | .dmars_bit = 0, | |
379 | }, { | |
380 | .offset = 0x60, | |
381 | .dmars = 8, | |
382 | .dmars_bit = 8, | |
383 | } | |
384 | }; | |
385 | ||
386 | static const unsigned int ts_shift[] = TS_SHIFT; | |
387 | ||
388 | static struct sh_dmae_pdata dma0_platform_data = { | |
389 | .slave = sh7757_dmae0_slaves, | |
390 | .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), | |
391 | .channel = sh7757_dmae_channels, | |
392 | .channel_num = ARRAY_SIZE(sh7757_dmae_channels), | |
393 | .ts_low_shift = CHCR_TS_LOW_SHIFT, | |
394 | .ts_low_mask = CHCR_TS_LOW_MASK, | |
395 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | |
396 | .ts_high_mask = CHCR_TS_HIGH_MASK, | |
397 | .ts_shift = ts_shift, | |
398 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
399 | .dmaor_init = DMAOR_INIT, | |
400 | }; | |
401 | ||
402 | static struct sh_dmae_pdata dma1_platform_data = { | |
403 | .slave = sh7757_dmae1_slaves, | |
404 | .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), | |
405 | .channel = sh7757_dmae_channels, | |
406 | .channel_num = ARRAY_SIZE(sh7757_dmae_channels), | |
407 | .ts_low_shift = CHCR_TS_LOW_SHIFT, | |
408 | .ts_low_mask = CHCR_TS_LOW_MASK, | |
409 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | |
410 | .ts_high_mask = CHCR_TS_HIGH_MASK, | |
411 | .ts_shift = ts_shift, | |
412 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
413 | .dmaor_init = DMAOR_INIT, | |
414 | }; | |
415 | ||
416 | static struct sh_dmae_pdata dma2_platform_data = { | |
417 | .slave = sh7757_dmae2_slaves, | |
418 | .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), | |
419 | .channel = sh7757_dmae_channels, | |
420 | .channel_num = ARRAY_SIZE(sh7757_dmae_channels), | |
421 | .ts_low_shift = CHCR_TS_LOW_SHIFT, | |
422 | .ts_low_mask = CHCR_TS_LOW_MASK, | |
423 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | |
424 | .ts_high_mask = CHCR_TS_HIGH_MASK, | |
425 | .ts_shift = ts_shift, | |
426 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
427 | .dmaor_init = DMAOR_INIT, | |
428 | }; | |
429 | ||
430 | static struct sh_dmae_pdata dma3_platform_data = { | |
431 | .slave = sh7757_dmae3_slaves, | |
432 | .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), | |
433 | .channel = sh7757_dmae_channels, | |
434 | .channel_num = ARRAY_SIZE(sh7757_dmae_channels), | |
435 | .ts_low_shift = CHCR_TS_LOW_SHIFT, | |
436 | .ts_low_mask = CHCR_TS_LOW_MASK, | |
437 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | |
438 | .ts_high_mask = CHCR_TS_HIGH_MASK, | |
439 | .ts_shift = ts_shift, | |
440 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
441 | .dmaor_init = DMAOR_INIT, | |
442 | }; | |
443 | ||
444 | /* channel 0 to 5 */ | |
445 | static struct resource sh7757_dmae0_resources[] = { | |
446 | [0] = { | |
447 | /* Channel registers and DMAOR */ | |
448 | .start = 0xff608020, | |
449 | .end = 0xff60808f, | |
450 | .flags = IORESOURCE_MEM, | |
451 | }, | |
452 | [1] = { | |
453 | /* DMARSx */ | |
454 | .start = 0xff609000, | |
455 | .end = 0xff60900b, | |
456 | .flags = IORESOURCE_MEM, | |
457 | }, | |
458 | { | |
459 | .name = "error_irq", | |
460 | .start = evt2irq(0x640), | |
461 | .end = evt2irq(0x640), | |
462 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
463 | }, | |
464 | }; | |
465 | ||
466 | /* channel 6 to 11 */ | |
467 | static struct resource sh7757_dmae1_resources[] = { | |
468 | [0] = { | |
469 | /* Channel registers and DMAOR */ | |
470 | .start = 0xff618020, | |
471 | .end = 0xff61808f, | |
472 | .flags = IORESOURCE_MEM, | |
473 | }, | |
474 | [1] = { | |
475 | /* DMARSx */ | |
476 | .start = 0xff619000, | |
477 | .end = 0xff61900b, | |
478 | .flags = IORESOURCE_MEM, | |
479 | }, | |
480 | { | |
481 | .name = "error_irq", | |
482 | .start = evt2irq(0x640), | |
483 | .end = evt2irq(0x640), | |
484 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
485 | }, | |
486 | { | |
487 | /* IRQ for channels 4 */ | |
488 | .start = evt2irq(0x7c0), | |
489 | .end = evt2irq(0x7c0), | |
490 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
491 | }, | |
492 | { | |
493 | /* IRQ for channels 5 */ | |
494 | .start = evt2irq(0x7c0), | |
495 | .end = evt2irq(0x7c0), | |
496 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
497 | }, | |
498 | { | |
499 | /* IRQ for channels 6 */ | |
500 | .start = evt2irq(0xd00), | |
501 | .end = evt2irq(0xd00), | |
502 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
503 | }, | |
504 | { | |
505 | /* IRQ for channels 7 */ | |
506 | .start = evt2irq(0xd00), | |
507 | .end = evt2irq(0xd00), | |
508 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
509 | }, | |
510 | { | |
511 | /* IRQ for channels 8 */ | |
512 | .start = evt2irq(0xd00), | |
513 | .end = evt2irq(0xd00), | |
514 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
515 | }, | |
516 | { | |
517 | /* IRQ for channels 9 */ | |
518 | .start = evt2irq(0xd00), | |
519 | .end = evt2irq(0xd00), | |
520 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
521 | }, | |
522 | { | |
523 | /* IRQ for channels 10 */ | |
524 | .start = evt2irq(0xd00), | |
525 | .end = evt2irq(0xd00), | |
526 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
527 | }, | |
528 | { | |
529 | /* IRQ for channels 11 */ | |
530 | .start = evt2irq(0xd00), | |
531 | .end = evt2irq(0xd00), | |
532 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, | |
533 | }, | |
534 | }; | |
535 | ||
536 | /* channel 12 to 17 */ | |
537 | static struct resource sh7757_dmae2_resources[] = { | |
538 | [0] = { | |
539 | /* Channel registers and DMAOR */ | |
540 | .start = 0xff708020, | |
541 | .end = 0xff70808f, | |
542 | .flags = IORESOURCE_MEM, | |
543 | }, | |
544 | [1] = { | |
545 | /* DMARSx */ | |
546 | .start = 0xff709000, | |
547 | .end = 0xff70900b, | |
548 | .flags = IORESOURCE_MEM, | |
549 | }, | |
550 | { | |
551 | .name = "error_irq", | |
552 | .start = evt2irq(0x2a60), | |
553 | .end = evt2irq(0x2a60), | |
554 | .flags = IORESOURCE_IRQ, | |
555 | }, | |
556 | { | |
557 | /* IRQ for channels 12 to 16 */ | |
558 | .start = evt2irq(0x2400), | |
559 | .end = evt2irq(0x2480), | |
560 | .flags = IORESOURCE_IRQ, | |
561 | }, | |
562 | { | |
563 | /* IRQ for channel 17 */ | |
564 | .start = evt2irq(0x24e0), | |
565 | .end = evt2irq(0x24e0), | |
566 | .flags = IORESOURCE_IRQ, | |
567 | }, | |
568 | }; | |
569 | ||
570 | /* channel 18 to 23 */ | |
571 | static struct resource sh7757_dmae3_resources[] = { | |
572 | [0] = { | |
573 | /* Channel registers and DMAOR */ | |
574 | .start = 0xff718020, | |
575 | .end = 0xff71808f, | |
576 | .flags = IORESOURCE_MEM, | |
577 | }, | |
578 | [1] = { | |
579 | /* DMARSx */ | |
580 | .start = 0xff719000, | |
581 | .end = 0xff71900b, | |
582 | .flags = IORESOURCE_MEM, | |
583 | }, | |
584 | { | |
585 | .name = "error_irq", | |
586 | .start = evt2irq(0x2a80), | |
587 | .end = evt2irq(0x2a80), | |
588 | .flags = IORESOURCE_IRQ, | |
589 | }, | |
590 | { | |
591 | /* IRQ for channels 18 to 22 */ | |
592 | .start = evt2irq(0x2500), | |
593 | .end = evt2irq(0x2580), | |
594 | .flags = IORESOURCE_IRQ, | |
595 | }, | |
596 | { | |
597 | /* IRQ for channel 23 */ | |
598 | .start = evt2irq(0x2600), | |
599 | .end = evt2irq(0x2600), | |
600 | .flags = IORESOURCE_IRQ, | |
601 | }, | |
602 | }; | |
603 | ||
604 | static struct platform_device dma0_device = { | |
605 | .name = "sh-dma-engine", | |
606 | .id = 0, | |
607 | .resource = sh7757_dmae0_resources, | |
608 | .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), | |
609 | .dev = { | |
610 | .platform_data = &dma0_platform_data, | |
611 | }, | |
612 | }; | |
613 | ||
614 | static struct platform_device dma1_device = { | |
615 | .name = "sh-dma-engine", | |
616 | .id = 1, | |
617 | .resource = sh7757_dmae1_resources, | |
618 | .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), | |
619 | .dev = { | |
620 | .platform_data = &dma1_platform_data, | |
621 | }, | |
622 | }; | |
623 | ||
624 | static struct platform_device dma2_device = { | |
625 | .name = "sh-dma-engine", | |
626 | .id = 2, | |
627 | .resource = sh7757_dmae2_resources, | |
628 | .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), | |
629 | .dev = { | |
630 | .platform_data = &dma2_platform_data, | |
631 | }, | |
632 | }; | |
633 | ||
634 | static struct platform_device dma3_device = { | |
635 | .name = "sh-dma-engine", | |
636 | .id = 3, | |
637 | .resource = sh7757_dmae3_resources, | |
638 | .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), | |
639 | .dev = { | |
640 | .platform_data = &dma3_platform_data, | |
641 | }, | |
642 | }; | |
643 | ||
644 | static struct platform_device spi0_device = { | |
645 | .name = "sh_spi", | |
646 | .id = 0, | |
647 | .dev = { | |
648 | .dma_mask = NULL, | |
649 | .coherent_dma_mask = 0xffffffff, | |
650 | }, | |
651 | .num_resources = ARRAY_SIZE(spi0_resources), | |
652 | .resource = spi0_resources, | |
653 | }; | |
654 | ||
655 | static struct resource spi1_resources[] = { | |
656 | { | |
657 | .start = 0xffd8ee70, | |
658 | .end = 0xffd8eeff, | |
659 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, | |
660 | }, | |
661 | { | |
662 | .start = evt2irq(0x8c0), | |
663 | .flags = IORESOURCE_IRQ, | |
664 | }, | |
665 | }; | |
666 | ||
667 | static struct platform_device spi1_device = { | |
668 | .name = "sh_spi", | |
669 | .id = 1, | |
670 | .num_resources = ARRAY_SIZE(spi1_resources), | |
671 | .resource = spi1_resources, | |
672 | }; | |
673 | ||
674 | static struct resource rspi_resources[] = { | |
675 | { | |
676 | .start = 0xfe480000, | |
677 | .end = 0xfe4800ff, | |
678 | .flags = IORESOURCE_MEM, | |
679 | }, | |
680 | { | |
681 | .start = evt2irq(0x1d80), | |
682 | .flags = IORESOURCE_IRQ, | |
683 | }, | |
684 | }; | |
685 | ||
686 | static struct platform_device rspi_device = { | |
687 | .name = "rspi", | |
688 | .id = 2, | |
689 | .num_resources = ARRAY_SIZE(rspi_resources), | |
690 | .resource = rspi_resources, | |
691 | }; | |
692 | ||
693 | static struct resource usb_ehci_resources[] = { | |
694 | [0] = { | |
695 | .start = 0xfe4f1000, | |
696 | .end = 0xfe4f10ff, | |
697 | .flags = IORESOURCE_MEM, | |
698 | }, | |
699 | [1] = { | |
700 | .start = evt2irq(0x920), | |
701 | .end = evt2irq(0x920), | |
702 | .flags = IORESOURCE_IRQ, | |
703 | }, | |
704 | }; | |
705 | ||
706 | static struct platform_device usb_ehci_device = { | |
707 | .name = "sh_ehci", | |
708 | .id = -1, | |
709 | .dev = { | |
710 | .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, | |
711 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
712 | }, | |
713 | .num_resources = ARRAY_SIZE(usb_ehci_resources), | |
714 | .resource = usb_ehci_resources, | |
715 | }; | |
716 | ||
717 | static struct resource usb_ohci_resources[] = { | |
718 | [0] = { | |
719 | .start = 0xfe4f1800, | |
720 | .end = 0xfe4f18ff, | |
721 | .flags = IORESOURCE_MEM, | |
722 | }, | |
723 | [1] = { | |
724 | .start = evt2irq(0x920), | |
725 | .end = evt2irq(0x920), | |
726 | .flags = IORESOURCE_IRQ, | |
727 | }, | |
728 | }; | |
729 | ||
730 | static struct usb_ohci_pdata usb_ohci_pdata; | |
731 | ||
732 | static struct platform_device usb_ohci_device = { | |
733 | .name = "ohci-platform", | |
734 | .id = -1, | |
735 | .dev = { | |
736 | .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, | |
737 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
738 | .platform_data = &usb_ohci_pdata, | |
739 | }, | |
740 | .num_resources = ARRAY_SIZE(usb_ohci_resources), | |
741 | .resource = usb_ohci_resources, | |
742 | }; | |
743 | ||
744 | static struct platform_device *sh7757_devices[] __initdata = { | |
745 | &scif2_device, | |
746 | &scif3_device, | |
747 | &scif4_device, | |
748 | &tmu0_device, | |
749 | &dma0_device, | |
750 | &dma1_device, | |
751 | &dma2_device, | |
752 | &dma3_device, | |
753 | &spi0_device, | |
754 | &spi1_device, | |
755 | &rspi_device, | |
756 | &usb_ehci_device, | |
757 | &usb_ohci_device, | |
758 | }; | |
759 | ||
760 | static int __init sh7757_devices_setup(void) | |
761 | { | |
762 | return platform_add_devices(sh7757_devices, | |
763 | ARRAY_SIZE(sh7757_devices)); | |
764 | } | |
765 | arch_initcall(sh7757_devices_setup); | |
766 | ||
767 | static struct platform_device *sh7757_early_devices[] __initdata = { | |
768 | &scif2_device, | |
769 | &scif3_device, | |
770 | &scif4_device, | |
771 | &tmu0_device, | |
772 | }; | |
773 | ||
774 | void __init plat_early_device_setup(void) | |
775 | { | |
776 | early_platform_add_devices(sh7757_early_devices, | |
777 | ARRAY_SIZE(sh7757_early_devices)); | |
778 | } | |
779 | ||
780 | enum { | |
781 | UNUSED = 0, | |
782 | ||
783 | /* interrupt sources */ | |
784 | ||
785 | IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, | |
786 | IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, | |
787 | IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, | |
788 | IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, | |
789 | ||
790 | IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, | |
791 | IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, | |
792 | IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, | |
793 | IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, | |
794 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
795 | ||
796 | SDHI, DVC, | |
797 | IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, | |
798 | TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, | |
799 | HUDI, | |
800 | ARC4, | |
801 | DMAC0_5, DMAC6_7, DMAC8_11, | |
802 | SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, | |
803 | USB0, USB1, | |
804 | JMC, | |
805 | SPI0, SPI1, | |
806 | TMR01, TMR23, TMR45, | |
807 | FRT, | |
808 | LPC, LPC5, LPC6, LPC7, LPC8, | |
809 | PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, | |
810 | ETHERC, | |
811 | ADC0, ADC1, | |
812 | SIM, | |
813 | IIC0_0, IIC0_1, IIC0_2, IIC0_3, | |
814 | IIC1_0, IIC1_1, IIC1_2, IIC1_3, | |
815 | IIC2_0, IIC2_1, IIC2_2, IIC2_3, | |
816 | IIC3_0, IIC3_1, IIC3_2, IIC3_3, | |
817 | IIC4_0, IIC4_1, IIC4_2, IIC4_3, | |
818 | IIC5_0, IIC5_1, IIC5_2, IIC5_3, | |
819 | IIC6_0, IIC6_1, IIC6_2, IIC6_3, | |
820 | IIC7_0, IIC7_1, IIC7_2, IIC7_3, | |
821 | IIC8_0, IIC8_1, IIC8_2, IIC8_3, | |
822 | IIC9_0, IIC9_1, IIC9_2, IIC9_3, | |
823 | ONFICTL, | |
824 | MMC1, MMC2, | |
825 | ECCU, | |
826 | PCIC, | |
827 | G200, | |
828 | RSPI, | |
829 | SGPIO, | |
830 | DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, | |
831 | DMINT20, DMINT21, DMINT22, DMINT23, | |
832 | DDRECC, | |
833 | TSIP, | |
834 | PCIE_BRIDGE, | |
835 | WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, | |
836 | GETHER0, GETHER1, GETHER2, | |
837 | PBIA, PBIB, PBIC, | |
838 | DMAE2, DMAE3, | |
839 | SERMUX2, SERMUX3, | |
840 | ||
841 | /* interrupt groups */ | |
842 | ||
843 | TMU012, TMU345, | |
844 | }; | |
845 | ||
846 | static struct intc_vect vectors[] __initdata = { | |
847 | INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), | |
848 | INTC_VECT(SDHI, 0x4c0), | |
849 | INTC_VECT(DVC, 0x4e0), | |
850 | INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), | |
851 | INTC_VECT(IRQ10, 0x540), | |
852 | INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), | |
853 | INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), | |
854 | INTC_VECT(HUDI, 0x600), | |
855 | INTC_VECT(ARC4, 0x620), | |
856 | INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), | |
857 | INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), | |
858 | INTC_VECT(DMAC0_5, 0x6c0), | |
859 | INTC_VECT(IRQ11, 0x6e0), | |
860 | INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), | |
861 | INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), | |
862 | INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), | |
863 | INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), | |
864 | INTC_VECT(USB0, 0x840), | |
865 | INTC_VECT(IRQ12, 0x880), | |
866 | INTC_VECT(JMC, 0x8a0), | |
867 | INTC_VECT(SPI1, 0x8c0), | |
868 | INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), | |
869 | INTC_VECT(USB1, 0x920), | |
870 | INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), | |
871 | INTC_VECT(TMR45, 0xa40), | |
872 | INTC_VECT(FRT, 0xa80), | |
873 | INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), | |
874 | INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), | |
875 | INTC_VECT(LPC, 0xb20), | |
876 | INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), | |
877 | INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), | |
878 | INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), | |
879 | INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), | |
880 | INTC_VECT(PECI2, 0xc40), | |
881 | INTC_VECT(IRQ15, 0xc60), | |
882 | INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), | |
883 | INTC_VECT(SPI0, 0xcc0), | |
884 | INTC_VECT(ADC1, 0xce0), | |
885 | INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), | |
886 | INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), | |
887 | INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), | |
888 | INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), | |
889 | INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), | |
890 | INTC_VECT(TMU5, 0xe40), | |
891 | INTC_VECT(ADC0, 0xe60), | |
892 | INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), | |
893 | INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), | |
894 | INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), | |
895 | INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), | |
896 | INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), | |
897 | INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), | |
898 | INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), | |
899 | INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), | |
900 | INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), | |
901 | INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), | |
902 | INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), | |
903 | INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), | |
904 | INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), | |
905 | INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), | |
906 | INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), | |
907 | INTC_VECT(IIC6_2, 0x1920), | |
908 | INTC_VECT(ONFICTL, 0x1960), | |
909 | INTC_VECT(IIC6_3, 0x1980), | |
910 | INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), | |
911 | INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), | |
912 | INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), | |
913 | INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), | |
914 | INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), | |
915 | INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), | |
916 | INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), | |
917 | INTC_VECT(ECCU, 0x1cc0), | |
918 | INTC_VECT(PCIC, 0x1ce0), | |
919 | INTC_VECT(G200, 0x1d00), | |
920 | INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), | |
921 | INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), | |
922 | INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), | |
923 | INTC_VECT(PECI5, 0x1f00), | |
924 | INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), | |
925 | INTC_VECT(SGPIO, 0x1fc0), | |
926 | INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), | |
927 | INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), | |
928 | INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), | |
929 | INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), | |
930 | INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), | |
931 | INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), | |
932 | INTC_VECT(DDRECC, 0x2620), | |
933 | INTC_VECT(TSIP, 0x2640), | |
934 | INTC_VECT(PCIE_BRIDGE, 0x27c0), | |
935 | INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), | |
936 | INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), | |
937 | INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), | |
938 | INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), | |
939 | INTC_VECT(WDT8B, 0x2900), | |
940 | INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), | |
941 | INTC_VECT(GETHER2, 0x29a0), | |
942 | INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), | |
943 | INTC_VECT(PBIC, 0x2a40), | |
944 | INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), | |
945 | INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), | |
946 | INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), | |
947 | INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), | |
948 | }; | |
949 | ||
950 | static struct intc_group groups[] __initdata = { | |
951 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), | |
952 | INTC_GROUP(TMU345, TMU3, TMU4, TMU5), | |
953 | }; | |
954 | ||
955 | static struct intc_mask_reg mask_registers[] __initdata = { | |
956 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ | |
957 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
958 | ||
959 | { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ | |
960 | { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, | |
961 | IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, | |
962 | IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, | |
963 | IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, | |
964 | IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, | |
965 | IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, | |
966 | IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, | |
967 | IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, | |
968 | ||
969 | { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ | |
970 | { 0, 0, 0, 0, 0, 0, 0, 0, | |
971 | 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, | |
972 | TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, | |
973 | HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 | |
974 | } }, | |
975 | ||
976 | { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ | |
977 | { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, | |
978 | IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, | |
979 | ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, | |
980 | ARC4, 0, SPI1, JMC, 0, 0, 0, DVC | |
981 | } }, | |
982 | ||
983 | { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ | |
984 | { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, | |
985 | 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, | |
986 | IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, | |
987 | IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 | |
988 | } }, | |
989 | ||
990 | { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ | |
991 | { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, | |
992 | IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, | |
993 | PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, | |
994 | IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 | |
995 | } }, | |
996 | ||
997 | { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ | |
998 | { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, | |
999 | 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, | |
1000 | PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, | |
1001 | DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 | |
1002 | } }, | |
1003 | ||
1004 | { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ | |
1005 | { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, | |
1006 | DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, | |
1007 | 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, | |
1008 | DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 | |
1009 | } }, | |
1010 | }; | |
1011 | ||
1012 | #define INTPRI 0xffd00010 | |
1013 | #define INT2PRI0 0xffd40000 | |
1014 | #define INT2PRI1 0xffd40004 | |
1015 | #define INT2PRI2 0xffd40008 | |
1016 | #define INT2PRI3 0xffd4000c | |
1017 | #define INT2PRI4 0xffd40010 | |
1018 | #define INT2PRI5 0xffd40014 | |
1019 | #define INT2PRI6 0xffd40018 | |
1020 | #define INT2PRI7 0xffd4001c | |
1021 | #define INT2PRI8 0xffd400a0 | |
1022 | #define INT2PRI9 0xffd400a4 | |
1023 | #define INT2PRI10 0xffd400a8 | |
1024 | #define INT2PRI11 0xffd400ac | |
1025 | #define INT2PRI12 0xffd400b0 | |
1026 | #define INT2PRI13 0xffd400b4 | |
1027 | #define INT2PRI14 0xffd400b8 | |
1028 | #define INT2PRI15 0xffd400bc | |
1029 | #define INT2PRI16 0xffd10000 | |
1030 | #define INT2PRI17 0xffd10004 | |
1031 | #define INT2PRI18 0xffd10008 | |
1032 | #define INT2PRI19 0xffd1000c | |
1033 | #define INT2PRI20 0xffd10010 | |
1034 | #define INT2PRI21 0xffd10014 | |
1035 | #define INT2PRI22 0xffd10018 | |
1036 | #define INT2PRI23 0xffd1001c | |
1037 | #define INT2PRI24 0xffd100a0 | |
1038 | #define INT2PRI25 0xffd100a4 | |
1039 | #define INT2PRI26 0xffd100a8 | |
1040 | #define INT2PRI27 0xffd100ac | |
1041 | #define INT2PRI28 0xffd100b0 | |
1042 | #define INT2PRI29 0xffd100b4 | |
1043 | #define INT2PRI30 0xffd100b8 | |
1044 | #define INT2PRI31 0xffd100bc | |
1045 | #define INT2PRI32 0xffd20000 | |
1046 | #define INT2PRI33 0xffd20004 | |
1047 | #define INT2PRI34 0xffd20008 | |
1048 | #define INT2PRI35 0xffd2000c | |
1049 | #define INT2PRI36 0xffd20010 | |
1050 | #define INT2PRI37 0xffd20014 | |
1051 | #define INT2PRI38 0xffd20018 | |
1052 | #define INT2PRI39 0xffd2001c | |
1053 | #define INT2PRI40 0xffd200a0 | |
1054 | #define INT2PRI41 0xffd200a4 | |
1055 | #define INT2PRI42 0xffd200a8 | |
1056 | #define INT2PRI43 0xffd200ac | |
1057 | #define INT2PRI44 0xffd200b0 | |
1058 | #define INT2PRI45 0xffd200b4 | |
1059 | #define INT2PRI46 0xffd200b8 | |
1060 | #define INT2PRI47 0xffd200bc | |
1061 | ||
1062 | static struct intc_prio_reg prio_registers[] __initdata = { | |
1063 | { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, | |
1064 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
1065 | ||
1066 | { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, | |
1067 | { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, | |
1068 | { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, | |
1069 | { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, | |
1070 | { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, | |
1071 | { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, | |
1072 | { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, | |
1073 | { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, | |
1074 | { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, | |
1075 | { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, | |
1076 | { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, | |
1077 | { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, | |
1078 | { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, | |
1079 | { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, | |
1080 | ||
1081 | { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, | |
1082 | { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, | |
1083 | { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, | |
1084 | { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, | |
1085 | { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, | |
1086 | { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, | |
1087 | { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, | |
1088 | { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, | |
1089 | { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, | |
1090 | { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, | |
1091 | { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, | |
1092 | { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, | |
1093 | { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, | |
1094 | { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, | |
1095 | { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, | |
1096 | { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, | |
1097 | { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, | |
1098 | { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, | |
1099 | { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, | |
1100 | { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, | |
1101 | { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, | |
1102 | { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, | |
1103 | { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, | |
1104 | { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, | |
1105 | { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, | |
1106 | { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, | |
1107 | { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, | |
1108 | { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, | |
1109 | { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, | |
1110 | { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, | |
1111 | { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, | |
1112 | { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, | |
1113 | }; | |
1114 | ||
1115 | static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { | |
1116 | { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, | |
1117 | IRQ11, IRQ10, IRQ9, IRQ8 } }, | |
1118 | }; | |
1119 | ||
1120 | static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, | |
1121 | mask_registers, prio_registers, | |
1122 | sense_registers_irq8to15); | |
1123 | ||
1124 | /* Support for external interrupt pins in IRQ mode */ | |
1125 | static struct intc_vect vectors_irq0123[] __initdata = { | |
1126 | INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), | |
1127 | INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), | |
1128 | }; | |
1129 | ||
1130 | static struct intc_vect vectors_irq4567[] __initdata = { | |
1131 | INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), | |
1132 | INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), | |
1133 | }; | |
1134 | ||
1135 | static struct intc_sense_reg sense_registers[] __initdata = { | |
1136 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, | |
1137 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
1138 | }; | |
1139 | ||
1140 | static struct intc_mask_reg ack_registers[] __initdata = { | |
1141 | { 0xffd00024, 0, 32, /* INTREQ */ | |
1142 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
1143 | }; | |
1144 | ||
1145 | static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", | |
1146 | vectors_irq0123, NULL, mask_registers, | |
1147 | prio_registers, sense_registers, ack_registers); | |
1148 | ||
1149 | static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", | |
1150 | vectors_irq4567, NULL, mask_registers, | |
1151 | prio_registers, sense_registers, ack_registers); | |
1152 | ||
1153 | /* External interrupt pins in IRL mode */ | |
1154 | static struct intc_vect vectors_irl0123[] __initdata = { | |
1155 | INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), | |
1156 | INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), | |
1157 | INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), | |
1158 | INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), | |
1159 | INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), | |
1160 | INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), | |
1161 | INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), | |
1162 | INTC_VECT(IRL0_HHHL, 0x3c0), | |
1163 | }; | |
1164 | ||
1165 | static struct intc_vect vectors_irl4567[] __initdata = { | |
1166 | INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220), | |
1167 | INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260), | |
1168 | INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0), | |
1169 | INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0), | |
1170 | INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320), | |
1171 | INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360), | |
1172 | INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0), | |
1173 | INTC_VECT(IRL4_HHHL, 0x3c0), | |
1174 | }; | |
1175 | ||
1176 | static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, | |
1177 | NULL, mask_registers, NULL, NULL); | |
1178 | ||
1179 | static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, | |
1180 | NULL, mask_registers, NULL, NULL); | |
1181 | ||
1182 | #define INTC_ICR0 0xffd00000 | |
1183 | #define INTC_INTMSK0 0xffd00044 | |
1184 | #define INTC_INTMSK1 0xffd00048 | |
1185 | #define INTC_INTMSK2 0xffd40080 | |
1186 | #define INTC_INTMSKCLR1 0xffd00068 | |
1187 | #define INTC_INTMSKCLR2 0xffd40084 | |
1188 | ||
1189 | void __init plat_irq_setup(void) | |
1190 | { | |
1191 | /* disable IRQ3-0 + IRQ7-4 */ | |
1192 | __raw_writel(0xff000000, INTC_INTMSK0); | |
1193 | ||
1194 | /* disable IRL3-0 + IRL7-4 */ | |
1195 | __raw_writel(0xc0000000, INTC_INTMSK1); | |
1196 | __raw_writel(0xfffefffe, INTC_INTMSK2); | |
1197 | ||
1198 | /* select IRL mode for IRL3-0 + IRL7-4 */ | |
1199 | __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); | |
1200 | ||
1201 | /* disable holding function, ie enable "SH-4 Mode" */ | |
1202 | __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); | |
1203 | ||
1204 | register_intc_controller(&intc_desc); | |
1205 | } | |
1206 | ||
1207 | void __init plat_irq_setup_pins(int mode) | |
1208 | { | |
1209 | switch (mode) { | |
1210 | case IRQ_MODE_IRQ7654: | |
1211 | /* select IRQ mode for IRL7-4 */ | |
1212 | __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); | |
1213 | register_intc_controller(&intc_desc_irq4567); | |
1214 | break; | |
1215 | case IRQ_MODE_IRQ3210: | |
1216 | /* select IRQ mode for IRL3-0 */ | |
1217 | __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); | |
1218 | register_intc_controller(&intc_desc_irq0123); | |
1219 | break; | |
1220 | case IRQ_MODE_IRL7654: | |
1221 | /* enable IRL7-4 but don't provide any masking */ | |
1222 | __raw_writel(0x40000000, INTC_INTMSKCLR1); | |
1223 | __raw_writel(0x0000fffe, INTC_INTMSKCLR2); | |
1224 | break; | |
1225 | case IRQ_MODE_IRL3210: | |
1226 | /* enable IRL0-3 but don't provide any masking */ | |
1227 | __raw_writel(0x80000000, INTC_INTMSKCLR1); | |
1228 | __raw_writel(0xfffe0000, INTC_INTMSKCLR2); | |
1229 | break; | |
1230 | case IRQ_MODE_IRL7654_MASK: | |
1231 | /* enable IRL7-4 and mask using cpu intc controller */ | |
1232 | __raw_writel(0x40000000, INTC_INTMSKCLR1); | |
1233 | register_intc_controller(&intc_desc_irl4567); | |
1234 | break; | |
1235 | case IRQ_MODE_IRL3210_MASK: | |
1236 | /* enable IRL0-3 and mask using cpu intc controller */ | |
1237 | __raw_writel(0x80000000, INTC_INTMSKCLR1); | |
1238 | register_intc_controller(&intc_desc_irl0123); | |
1239 | break; | |
1240 | default: | |
1241 | BUG(); | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | void __init plat_mem_setup(void) | |
1246 | { | |
1247 | } |