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1 | #ifndef _ASM_X86_APIC_H | |
2 | #define _ASM_X86_APIC_H | |
3 | ||
4 | #include <linux/cpumask.h> | |
5 | #include <linux/pm.h> | |
6 | ||
7 | #include <asm/alternative.h> | |
8 | #include <asm/cpufeature.h> | |
9 | #include <asm/apicdef.h> | |
10 | #include <linux/atomic.h> | |
11 | #include <asm/fixmap.h> | |
12 | #include <asm/mpspec.h> | |
13 | #include <asm/msr.h> | |
14 | #include <asm/idle.h> | |
15 | ||
16 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
17 | ||
18 | /* | |
19 | * Debugging macros | |
20 | */ | |
21 | #define APIC_QUIET 0 | |
22 | #define APIC_VERBOSE 1 | |
23 | #define APIC_DEBUG 2 | |
24 | ||
25 | /* Macros for apic_extnmi which controls external NMI masking */ | |
26 | #define APIC_EXTNMI_BSP 0 /* Default */ | |
27 | #define APIC_EXTNMI_ALL 1 | |
28 | #define APIC_EXTNMI_NONE 2 | |
29 | ||
30 | /* | |
31 | * Define the default level of output to be very little | |
32 | * This can be turned up by using apic=verbose for more | |
33 | * information and apic=debug for _lots_ of information. | |
34 | * apic_verbosity is defined in apic.c | |
35 | */ | |
36 | #define apic_printk(v, s, a...) do { \ | |
37 | if ((v) <= apic_verbosity) \ | |
38 | printk(s, ##a); \ | |
39 | } while (0) | |
40 | ||
41 | ||
42 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) | |
43 | extern void generic_apic_probe(void); | |
44 | #else | |
45 | static inline void generic_apic_probe(void) | |
46 | { | |
47 | } | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_X86_LOCAL_APIC | |
51 | ||
52 | extern unsigned int apic_verbosity; | |
53 | extern int local_apic_timer_c2_ok; | |
54 | ||
55 | extern int disable_apic; | |
56 | extern unsigned int lapic_timer_frequency; | |
57 | ||
58 | #ifdef CONFIG_SMP | |
59 | extern void __inquire_remote_apic(int apicid); | |
60 | #else /* CONFIG_SMP */ | |
61 | static inline void __inquire_remote_apic(int apicid) | |
62 | { | |
63 | } | |
64 | #endif /* CONFIG_SMP */ | |
65 | ||
66 | static inline void default_inquire_remote_apic(int apicid) | |
67 | { | |
68 | if (apic_verbosity >= APIC_DEBUG) | |
69 | __inquire_remote_apic(apicid); | |
70 | } | |
71 | ||
72 | /* | |
73 | * With 82489DX we can't rely on apic feature bit | |
74 | * retrieved via cpuid but still have to deal with | |
75 | * such an apic chip so we assume that SMP configuration | |
76 | * is found from MP table (64bit case uses ACPI mostly | |
77 | * which set smp presence flag as well so we are safe | |
78 | * to use this helper too). | |
79 | */ | |
80 | static inline bool apic_from_smp_config(void) | |
81 | { | |
82 | return smp_found_config && !disable_apic; | |
83 | } | |
84 | ||
85 | /* | |
86 | * Basic functions accessing APICs. | |
87 | */ | |
88 | #ifdef CONFIG_PARAVIRT | |
89 | #include <asm/paravirt.h> | |
90 | #endif | |
91 | ||
92 | extern int setup_profiling_timer(unsigned int); | |
93 | ||
94 | static inline void native_apic_mem_write(u32 reg, u32 v) | |
95 | { | |
96 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); | |
97 | ||
98 | alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, | |
99 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
100 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
101 | } | |
102 | ||
103 | static inline u32 native_apic_mem_read(u32 reg) | |
104 | { | |
105 | return *((volatile u32 *)(APIC_BASE + reg)); | |
106 | } | |
107 | ||
108 | extern void native_apic_wait_icr_idle(void); | |
109 | extern u32 native_safe_apic_wait_icr_idle(void); | |
110 | extern void native_apic_icr_write(u32 low, u32 id); | |
111 | extern u64 native_apic_icr_read(void); | |
112 | ||
113 | static inline bool apic_is_x2apic_enabled(void) | |
114 | { | |
115 | u64 msr; | |
116 | ||
117 | if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) | |
118 | return false; | |
119 | return msr & X2APIC_ENABLE; | |
120 | } | |
121 | ||
122 | extern void enable_IR_x2apic(void); | |
123 | ||
124 | extern int get_physical_broadcast(void); | |
125 | ||
126 | extern int lapic_get_maxlvt(void); | |
127 | extern void clear_local_APIC(void); | |
128 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
129 | extern void disable_local_APIC(void); | |
130 | extern void lapic_shutdown(void); | |
131 | extern void sync_Arb_IDs(void); | |
132 | extern void init_bsp_APIC(void); | |
133 | extern void setup_local_APIC(void); | |
134 | extern void init_apic_mappings(void); | |
135 | void register_lapic_address(unsigned long address); | |
136 | extern void setup_boot_APIC_clock(void); | |
137 | extern void setup_secondary_APIC_clock(void); | |
138 | extern void lapic_update_tsc_freq(void); | |
139 | extern int APIC_init_uniprocessor(void); | |
140 | ||
141 | #ifdef CONFIG_X86_64 | |
142 | static inline int apic_force_enable(unsigned long addr) | |
143 | { | |
144 | return -1; | |
145 | } | |
146 | #else | |
147 | extern int apic_force_enable(unsigned long addr); | |
148 | #endif | |
149 | ||
150 | extern int apic_bsp_setup(bool upmode); | |
151 | extern void apic_ap_setup(void); | |
152 | ||
153 | /* | |
154 | * On 32bit this is mach-xxx local | |
155 | */ | |
156 | #ifdef CONFIG_X86_64 | |
157 | extern int apic_is_clustered_box(void); | |
158 | #else | |
159 | static inline int apic_is_clustered_box(void) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | #endif | |
164 | ||
165 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); | |
166 | ||
167 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
168 | static inline void lapic_shutdown(void) { } | |
169 | #define local_apic_timer_c2_ok 1 | |
170 | static inline void init_apic_mappings(void) { } | |
171 | static inline void disable_local_APIC(void) { } | |
172 | # define setup_boot_APIC_clock x86_init_noop | |
173 | # define setup_secondary_APIC_clock x86_init_noop | |
174 | static inline void lapic_update_tsc_freq(void) { } | |
175 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
176 | ||
177 | #ifdef CONFIG_X86_X2APIC | |
178 | /* | |
179 | * Make previous memory operations globally visible before | |
180 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
181 | * mfence for this. | |
182 | */ | |
183 | static inline void x2apic_wrmsr_fence(void) | |
184 | { | |
185 | asm volatile("mfence" : : : "memory"); | |
186 | } | |
187 | ||
188 | static inline void native_apic_msr_write(u32 reg, u32 v) | |
189 | { | |
190 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
191 | reg == APIC_LVR) | |
192 | return; | |
193 | ||
194 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
195 | } | |
196 | ||
197 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) | |
198 | { | |
199 | wrmsr_notrace(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); | |
200 | } | |
201 | ||
202 | static inline u32 native_apic_msr_read(u32 reg) | |
203 | { | |
204 | u64 msr; | |
205 | ||
206 | if (reg == APIC_DFR) | |
207 | return -1; | |
208 | ||
209 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); | |
210 | return (u32)msr; | |
211 | } | |
212 | ||
213 | static inline void native_x2apic_wait_icr_idle(void) | |
214 | { | |
215 | /* no need to wait for icr idle in x2apic */ | |
216 | return; | |
217 | } | |
218 | ||
219 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
220 | { | |
221 | /* no need to wait for icr idle in x2apic */ | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
226 | { | |
227 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
228 | } | |
229 | ||
230 | static inline u64 native_x2apic_icr_read(void) | |
231 | { | |
232 | unsigned long val; | |
233 | ||
234 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
235 | return val; | |
236 | } | |
237 | ||
238 | extern int x2apic_mode; | |
239 | extern int x2apic_phys; | |
240 | extern void __init check_x2apic(void); | |
241 | extern void x2apic_setup(void); | |
242 | static inline int x2apic_enabled(void) | |
243 | { | |
244 | return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); | |
245 | } | |
246 | ||
247 | #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) | |
248 | #else /* !CONFIG_X86_X2APIC */ | |
249 | static inline void check_x2apic(void) { } | |
250 | static inline void x2apic_setup(void) { } | |
251 | static inline int x2apic_enabled(void) { return 0; } | |
252 | ||
253 | #define x2apic_mode (0) | |
254 | #define x2apic_supported() (0) | |
255 | #endif /* !CONFIG_X86_X2APIC */ | |
256 | ||
257 | #ifdef CONFIG_X86_64 | |
258 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
259 | #else | |
260 | ||
261 | #endif | |
262 | ||
263 | /* | |
264 | * Copyright 2004 James Cleverdon, IBM. | |
265 | * Subject to the GNU Public License, v.2 | |
266 | * | |
267 | * Generic APIC sub-arch data struct. | |
268 | * | |
269 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
270 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
271 | * James Cleverdon. | |
272 | */ | |
273 | struct apic { | |
274 | char *name; | |
275 | ||
276 | int (*probe)(void); | |
277 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
278 | int (*apic_id_valid)(int apicid); | |
279 | int (*apic_id_registered)(void); | |
280 | ||
281 | u32 irq_delivery_mode; | |
282 | u32 irq_dest_mode; | |
283 | ||
284 | const struct cpumask *(*target_cpus)(void); | |
285 | ||
286 | int disable_esr; | |
287 | ||
288 | int dest_logical; | |
289 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); | |
290 | ||
291 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, | |
292 | const struct cpumask *mask); | |
293 | void (*init_apic_ldr)(void); | |
294 | ||
295 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); | |
296 | ||
297 | void (*setup_apic_routing)(void); | |
298 | int (*cpu_present_to_apicid)(int mps_cpu); | |
299 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); | |
300 | int (*check_phys_apicid_present)(int phys_apicid); | |
301 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); | |
302 | ||
303 | unsigned int (*get_apic_id)(unsigned long x); | |
304 | unsigned long (*set_apic_id)(unsigned int id); | |
305 | ||
306 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, | |
307 | const struct cpumask *andmask, | |
308 | unsigned int *apicid); | |
309 | ||
310 | /* ipi */ | |
311 | void (*send_IPI)(int cpu, int vector); | |
312 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
313 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
314 | int vector); | |
315 | void (*send_IPI_allbutself)(int vector); | |
316 | void (*send_IPI_all)(int vector); | |
317 | void (*send_IPI_self)(int vector); | |
318 | ||
319 | /* wakeup_secondary_cpu */ | |
320 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); | |
321 | ||
322 | void (*inquire_remote_apic)(int apicid); | |
323 | ||
324 | /* apic ops */ | |
325 | u32 (*read)(u32 reg); | |
326 | void (*write)(u32 reg, u32 v); | |
327 | /* | |
328 | * ->eoi_write() has the same signature as ->write(). | |
329 | * | |
330 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
331 | * callback value. Kernel can override ->eoi_write() and fall back | |
332 | * on write for EOI. | |
333 | */ | |
334 | void (*eoi_write)(u32 reg, u32 v); | |
335 | void (*native_eoi_write)(u32 reg, u32 v); | |
336 | u64 (*icr_read)(void); | |
337 | void (*icr_write)(u32 low, u32 high); | |
338 | void (*wait_icr_idle)(void); | |
339 | u32 (*safe_wait_icr_idle)(void); | |
340 | ||
341 | #ifdef CONFIG_X86_32 | |
342 | /* | |
343 | * Called very early during boot from get_smp_config(). It should | |
344 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
345 | * initialized before this function is called. | |
346 | * | |
347 | * If logical apicid can't be determined that early, the function | |
348 | * may return BAD_APICID. Logical apicid will be configured after | |
349 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
350 | * won't be applied properly during early boot in this case. | |
351 | */ | |
352 | int (*x86_32_early_logical_apicid)(int cpu); | |
353 | #endif | |
354 | }; | |
355 | ||
356 | /* | |
357 | * Pointer to the local APIC driver in use on this system (there's | |
358 | * always just one such driver in use - the kernel decides via an | |
359 | * early probing process which one it picks - and then sticks to it): | |
360 | */ | |
361 | extern struct apic *apic; | |
362 | ||
363 | /* | |
364 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
365 | * section. So the order is important and enforced by the ordering | |
366 | * of different apic driver files in the Makefile. | |
367 | * | |
368 | * For the files having two apic drivers, we use apic_drivers() | |
369 | * to enforce the order with in them. | |
370 | */ | |
371 | #define apic_driver(sym) \ | |
372 | static const struct apic *__apicdrivers_##sym __used \ | |
373 | __aligned(sizeof(struct apic *)) \ | |
374 | __section(.apicdrivers) = { &sym } | |
375 | ||
376 | #define apic_drivers(sym1, sym2) \ | |
377 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
378 | __aligned(sizeof(struct apic *)) \ | |
379 | __section(.apicdrivers) = { &sym1, &sym2 } | |
380 | ||
381 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
382 | ||
383 | /* | |
384 | * APIC functionality to boot other CPUs - only used on SMP: | |
385 | */ | |
386 | #ifdef CONFIG_SMP | |
387 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); | |
388 | #endif | |
389 | ||
390 | #ifdef CONFIG_X86_LOCAL_APIC | |
391 | ||
392 | static inline u32 apic_read(u32 reg) | |
393 | { | |
394 | return apic->read(reg); | |
395 | } | |
396 | ||
397 | static inline void apic_write(u32 reg, u32 val) | |
398 | { | |
399 | apic->write(reg, val); | |
400 | } | |
401 | ||
402 | static inline void apic_eoi(void) | |
403 | { | |
404 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
405 | } | |
406 | ||
407 | static inline u64 apic_icr_read(void) | |
408 | { | |
409 | return apic->icr_read(); | |
410 | } | |
411 | ||
412 | static inline void apic_icr_write(u32 low, u32 high) | |
413 | { | |
414 | apic->icr_write(low, high); | |
415 | } | |
416 | ||
417 | static inline void apic_wait_icr_idle(void) | |
418 | { | |
419 | apic->wait_icr_idle(); | |
420 | } | |
421 | ||
422 | static inline u32 safe_apic_wait_icr_idle(void) | |
423 | { | |
424 | return apic->safe_wait_icr_idle(); | |
425 | } | |
426 | ||
427 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); | |
428 | ||
429 | #else /* CONFIG_X86_LOCAL_APIC */ | |
430 | ||
431 | static inline u32 apic_read(u32 reg) { return 0; } | |
432 | static inline void apic_write(u32 reg, u32 val) { } | |
433 | static inline void apic_eoi(void) { } | |
434 | static inline u64 apic_icr_read(void) { return 0; } | |
435 | static inline void apic_icr_write(u32 low, u32 high) { } | |
436 | static inline void apic_wait_icr_idle(void) { } | |
437 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
438 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} | |
439 | ||
440 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
441 | ||
442 | static inline void ack_APIC_irq(void) | |
443 | { | |
444 | /* | |
445 | * ack_APIC_irq() actually gets compiled as a single instruction | |
446 | * ... yummie. | |
447 | */ | |
448 | apic_eoi(); | |
449 | } | |
450 | ||
451 | static inline unsigned default_get_apic_id(unsigned long x) | |
452 | { | |
453 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
454 | ||
455 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) | |
456 | return (x >> 24) & 0xFF; | |
457 | else | |
458 | return (x >> 24) & 0x0F; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Warm reset vector position: | |
463 | */ | |
464 | #define TRAMPOLINE_PHYS_LOW 0x467 | |
465 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
466 | ||
467 | #ifdef CONFIG_X86_64 | |
468 | extern void apic_send_IPI_self(int vector); | |
469 | ||
470 | DECLARE_PER_CPU(int, x2apic_extra_bits); | |
471 | ||
472 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
473 | extern int default_check_phys_apicid_present(int phys_apicid); | |
474 | #endif | |
475 | ||
476 | extern void generic_bigsmp_probe(void); | |
477 | ||
478 | ||
479 | #ifdef CONFIG_X86_LOCAL_APIC | |
480 | ||
481 | #include <asm/smp.h> | |
482 | ||
483 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
484 | ||
485 | static inline const struct cpumask *default_target_cpus(void) | |
486 | { | |
487 | #ifdef CONFIG_SMP | |
488 | return cpu_online_mask; | |
489 | #else | |
490 | return cpumask_of(0); | |
491 | #endif | |
492 | } | |
493 | ||
494 | static inline const struct cpumask *online_target_cpus(void) | |
495 | { | |
496 | return cpu_online_mask; | |
497 | } | |
498 | ||
499 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); | |
500 | ||
501 | ||
502 | static inline unsigned int read_apic_id(void) | |
503 | { | |
504 | unsigned int reg; | |
505 | ||
506 | reg = apic_read(APIC_ID); | |
507 | ||
508 | return apic->get_apic_id(reg); | |
509 | } | |
510 | ||
511 | static inline int default_apic_id_valid(int apicid) | |
512 | { | |
513 | return (apicid < 255); | |
514 | } | |
515 | ||
516 | extern int default_acpi_madt_oem_check(char *, char *); | |
517 | ||
518 | extern void default_setup_apic_routing(void); | |
519 | ||
520 | extern struct apic apic_noop; | |
521 | ||
522 | #ifdef CONFIG_X86_32 | |
523 | ||
524 | static inline int noop_x86_32_early_logical_apicid(int cpu) | |
525 | { | |
526 | return BAD_APICID; | |
527 | } | |
528 | ||
529 | /* | |
530 | * Set up the logical destination ID. | |
531 | * | |
532 | * Intel recommends to set DFR, LDR and TPR before enabling | |
533 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
534 | * document number 292116). So here it goes... | |
535 | */ | |
536 | extern void default_init_apic_ldr(void); | |
537 | ||
538 | static inline int default_apic_id_registered(void) | |
539 | { | |
540 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
541 | } | |
542 | ||
543 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) | |
544 | { | |
545 | return cpuid_apic >> index_msb; | |
546 | } | |
547 | ||
548 | #endif | |
549 | ||
550 | static inline int | |
551 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
552 | const struct cpumask *andmask, | |
553 | unsigned int *apicid) | |
554 | { | |
555 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & | |
556 | cpumask_bits(andmask)[0] & | |
557 | cpumask_bits(cpu_online_mask)[0] & | |
558 | APIC_ALL_CPUS; | |
559 | ||
560 | if (likely(cpu_mask)) { | |
561 | *apicid = (unsigned int)cpu_mask; | |
562 | return 0; | |
563 | } else { | |
564 | return -EINVAL; | |
565 | } | |
566 | } | |
567 | ||
568 | extern int | |
569 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
570 | const struct cpumask *andmask, | |
571 | unsigned int *apicid); | |
572 | ||
573 | static inline void | |
574 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, | |
575 | const struct cpumask *mask) | |
576 | { | |
577 | /* Careful. Some cpus do not strictly honor the set of cpus | |
578 | * specified in the interrupt destination when using lowest | |
579 | * priority interrupt delivery mode. | |
580 | * | |
581 | * In particular there was a hyperthreading cpu observed to | |
582 | * deliver interrupts to the wrong hyperthread when only one | |
583 | * hyperthread was specified in the interrupt desitination. | |
584 | */ | |
585 | cpumask_clear(retmask); | |
586 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
587 | } | |
588 | ||
589 | static inline void | |
590 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, | |
591 | const struct cpumask *mask) | |
592 | { | |
593 | cpumask_copy(retmask, cpumask_of(cpu)); | |
594 | } | |
595 | ||
596 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) | |
597 | { | |
598 | return physid_isset(apicid, *map); | |
599 | } | |
600 | ||
601 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) | |
602 | { | |
603 | *retmap = *phys_map; | |
604 | } | |
605 | ||
606 | static inline int __default_cpu_present_to_apicid(int mps_cpu) | |
607 | { | |
608 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
609 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
610 | else | |
611 | return BAD_APICID; | |
612 | } | |
613 | ||
614 | static inline int | |
615 | __default_check_phys_apicid_present(int phys_apicid) | |
616 | { | |
617 | return physid_isset(phys_apicid, phys_cpu_present_map); | |
618 | } | |
619 | ||
620 | #ifdef CONFIG_X86_32 | |
621 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
622 | { | |
623 | return __default_cpu_present_to_apicid(mps_cpu); | |
624 | } | |
625 | ||
626 | static inline int | |
627 | default_check_phys_apicid_present(int phys_apicid) | |
628 | { | |
629 | return __default_check_phys_apicid_present(phys_apicid); | |
630 | } | |
631 | #else | |
632 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
633 | extern int default_check_phys_apicid_present(int phys_apicid); | |
634 | #endif | |
635 | ||
636 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
637 | extern void irq_enter(void); | |
638 | extern void irq_exit(void); | |
639 | ||
640 | static inline void entering_irq(void) | |
641 | { | |
642 | irq_enter(); | |
643 | exit_idle(); | |
644 | } | |
645 | ||
646 | static inline void entering_ack_irq(void) | |
647 | { | |
648 | entering_irq(); | |
649 | ack_APIC_irq(); | |
650 | } | |
651 | ||
652 | static inline void ipi_entering_ack_irq(void) | |
653 | { | |
654 | irq_enter(); | |
655 | ack_APIC_irq(); | |
656 | } | |
657 | ||
658 | static inline void exiting_irq(void) | |
659 | { | |
660 | irq_exit(); | |
661 | } | |
662 | ||
663 | static inline void exiting_ack_irq(void) | |
664 | { | |
665 | ack_APIC_irq(); | |
666 | irq_exit(); | |
667 | } | |
668 | ||
669 | extern void ioapic_zap_locks(void); | |
670 | ||
671 | #endif /* _ASM_X86_APIC_H */ |