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1 | /* | |
2 | * Defines x86 CPU feature bits | |
3 | */ | |
4 | #ifndef _ASM_X86_CPUFEATURE_H | |
5 | #define _ASM_X86_CPUFEATURE_H | |
6 | ||
7 | #ifndef _ASM_X86_REQUIRED_FEATURES_H | |
8 | #include <asm/required-features.h> | |
9 | #endif | |
10 | ||
11 | #define NCAPINTS 10 /* N 32-bit words worth of info */ | |
12 | ||
13 | /* | |
14 | * Note: If the comment begins with a quoted string, that string is used | |
15 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
16 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
17 | */ | |
18 | ||
19 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
20 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ | |
21 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ | |
22 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ | |
23 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ | |
24 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ | |
25 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ | |
26 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ | |
27 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ | |
28 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ | |
29 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ | |
30 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ | |
31 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ | |
32 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ | |
33 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ | |
34 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ | |
35 | /* (plus FCMOVcc, FCOMI with FPU) */ | |
36 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ | |
37 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ | |
38 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ | |
39 | #define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ | |
40 | #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ | |
41 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ | |
42 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ | |
43 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
44 | #define X86_FEATURE_XMM (0*32+25) /* "sse" */ | |
45 | #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ | |
46 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ | |
47 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ | |
48 | #define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ | |
49 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ | |
50 | #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ | |
51 | ||
52 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
53 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
54 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ | |
55 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ | |
56 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ | |
57 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ | |
58 | #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
59 | #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ | |
60 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ | |
61 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ | |
62 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ | |
63 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ | |
64 | ||
65 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
66 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ | |
67 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ | |
68 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ | |
69 | ||
70 | /* Other features, Linux-defined mapping, word 3 */ | |
71 | /* This range is used for feature bits which conflict or are synthesized */ | |
72 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ | |
73 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
74 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
75 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
76 | /* cpu types for specific tunings: */ | |
77 | #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ | |
78 | #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ | |
79 | #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ | |
80 | #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ | |
81 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ | |
82 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ | |
83 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ | |
84 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | |
85 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | |
86 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | |
87 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ | |
88 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ | |
89 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ | |
90 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ | |
91 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ | |
92 | #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ | |
93 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ | |
94 | /* 21 available, was AMD_C1E */ | |
95 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ | |
96 | #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ | |
97 | #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ | |
98 | #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ | |
99 | #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ | |
100 | #define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ | |
101 | #define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ | |
102 | #define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ | |
103 | ||
104 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
105 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ | |
106 | #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ | |
107 | #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ | |
108 | #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
109 | #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
110 | #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ | |
111 | #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ | |
112 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ | |
113 | #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ | |
114 | #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ | |
115 | #define X86_FEATURE_CID (4*32+10) /* Context ID */ | |
116 | #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ | |
117 | #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ | |
118 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ | |
119 | #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ | |
120 | #define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ | |
121 | #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ | |
122 | #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ | |
123 | #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ | |
124 | #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ | |
125 | #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ | |
126 | #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ | |
127 | #define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ | |
128 | #define X86_FEATURE_AES (4*32+25) /* AES instructions */ | |
129 | #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
130 | #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ | |
131 | #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ | |
132 | #define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ | |
133 | #define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ | |
134 | #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ | |
135 | ||
136 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
137 | #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ | |
138 | #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ | |
139 | #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
140 | #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
141 | #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
142 | #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ | |
143 | #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ | |
144 | #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ | |
145 | #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ | |
146 | #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ | |
147 | ||
148 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
149 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | |
150 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | |
151 | #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ | |
152 | #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ | |
153 | #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ | |
154 | #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ | |
155 | #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ | |
156 | #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ | |
157 | #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ | |
158 | #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ | |
159 | #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ | |
160 | #define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ | |
161 | #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ | |
162 | #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ | |
163 | #define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ | |
164 | #define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ | |
165 | #define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ | |
166 | #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ | |
167 | #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ | |
168 | #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ | |
169 | #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ | |
170 | ||
171 | /* | |
172 | * Auxiliary flags: Linux defined - For features scattered in various | |
173 | * CPUID levels like 0x6, 0xA etc, word 7 | |
174 | */ | |
175 | #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ | |
176 | #define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ | |
177 | #define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ | |
178 | #define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
179 | #define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ | |
180 | #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ | |
181 | #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ | |
182 | #define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ | |
183 | #define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ | |
184 | ||
185 | /* Virtualization flags: Linux defined, word 8 */ | |
186 | #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ | |
187 | #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ | |
188 | #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ | |
189 | #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ | |
190 | #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ | |
191 | #define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ | |
192 | #define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ | |
193 | #define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ | |
194 | #define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ | |
195 | #define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ | |
196 | #define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ | |
197 | #define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ | |
198 | #define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ | |
199 | #define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ | |
200 | #define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ | |
201 | ||
202 | ||
203 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | |
204 | #define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | |
205 | #define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
206 | #define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ | |
207 | #define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ | |
208 | #define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ | |
209 | #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ | |
210 | #define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ | |
211 | #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
212 | #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ | |
213 | #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ | |
214 | #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ | |
215 | #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ | |
216 | #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ | |
217 | ||
218 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | |
219 | ||
220 | #include <asm/asm.h> | |
221 | #include <linux/bitops.h> | |
222 | ||
223 | extern const char * const x86_cap_flags[NCAPINTS*32]; | |
224 | extern const char * const x86_power_flags[32]; | |
225 | ||
226 | #define test_cpu_cap(c, bit) \ | |
227 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
228 | ||
229 | #define REQUIRED_MASK_BIT_SET(bit) \ | |
230 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ | |
231 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ | |
232 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ | |
233 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | |
234 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | |
235 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | |
236 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ | |
237 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ | |
238 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ | |
239 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) | |
240 | ||
241 | #define cpu_has(c, bit) \ | |
242 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
243 | test_cpu_cap(c, bit)) | |
244 | ||
245 | #define this_cpu_has(bit) \ | |
246 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
247 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) | |
248 | ||
249 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) | |
250 | ||
251 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) | |
252 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
253 | #define setup_clear_cpu_cap(bit) do { \ | |
254 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
255 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ | |
256 | } while (0) | |
257 | #define setup_force_cpu_cap(bit) do { \ | |
258 | set_cpu_cap(&boot_cpu_data, bit); \ | |
259 | set_bit(bit, (unsigned long *)cpu_caps_set); \ | |
260 | } while (0) | |
261 | ||
262 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | |
263 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) | |
264 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) | |
265 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) | |
266 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
267 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) | |
268 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) | |
269 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
270 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) | |
271 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) | |
272 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) | |
273 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) | |
274 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
275 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
276 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) | |
277 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) | |
278 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) | |
279 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) | |
280 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) | |
281 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) | |
282 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) | |
283 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) | |
284 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) | |
285 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) | |
286 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) | |
287 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) | |
288 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) | |
289 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) | |
290 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) | |
291 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) | |
292 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) | |
293 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) | |
294 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) | |
295 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) | |
296 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | |
297 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | |
298 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) | |
299 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) | |
300 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) | |
301 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) | |
302 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) | |
303 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) | |
304 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) | |
305 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) | |
306 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) | |
307 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) | |
308 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) | |
309 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) | |
310 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) | |
311 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) | |
312 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) | |
313 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) | |
314 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) | |
315 | ||
316 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) | |
317 | # define cpu_has_invlpg 1 | |
318 | #else | |
319 | # define cpu_has_invlpg (boot_cpu_data.x86 > 3) | |
320 | #endif | |
321 | ||
322 | #ifdef CONFIG_X86_64 | |
323 | ||
324 | #undef cpu_has_vme | |
325 | #define cpu_has_vme 0 | |
326 | ||
327 | #undef cpu_has_pae | |
328 | #define cpu_has_pae ___BUG___ | |
329 | ||
330 | #undef cpu_has_mp | |
331 | #define cpu_has_mp 1 | |
332 | ||
333 | #undef cpu_has_k6_mtrr | |
334 | #define cpu_has_k6_mtrr 0 | |
335 | ||
336 | #undef cpu_has_cyrix_arr | |
337 | #define cpu_has_cyrix_arr 0 | |
338 | ||
339 | #undef cpu_has_centaur_mcr | |
340 | #define cpu_has_centaur_mcr 0 | |
341 | ||
342 | #endif /* CONFIG_X86_64 */ | |
343 | ||
344 | #if __GNUC__ >= 4 | |
345 | /* | |
346 | * Static testing of CPU features. Used the same as boot_cpu_has(). | |
347 | * These are only valid after alternatives have run, but will statically | |
348 | * patch the target code for additional performance. | |
349 | * | |
350 | */ | |
351 | static __always_inline __pure bool __static_cpu_has(u16 bit) | |
352 | { | |
353 | #if __GNUC__ > 4 || __GNUC_MINOR__ >= 5 | |
354 | asm goto("1: jmp %l[t_no]\n" | |
355 | "2:\n" | |
356 | ".section .altinstructions,\"a\"\n" | |
357 | " .long 1b - .\n" | |
358 | " .long 0\n" /* no replacement */ | |
359 | " .word %P0\n" /* feature bit */ | |
360 | " .byte 2b - 1b\n" /* source len */ | |
361 | " .byte 0\n" /* replacement len */ | |
362 | ".previous\n" | |
363 | /* skipping size check since replacement size = 0 */ | |
364 | : : "i" (bit) : : t_no); | |
365 | return true; | |
366 | t_no: | |
367 | return false; | |
368 | #else | |
369 | u8 flag; | |
370 | /* Open-coded due to __stringify() in ALTERNATIVE() */ | |
371 | asm volatile("1: movb $0,%0\n" | |
372 | "2:\n" | |
373 | ".section .altinstructions,\"a\"\n" | |
374 | " .long 1b - .\n" | |
375 | " .long 3f - .\n" | |
376 | " .word %P1\n" /* feature bit */ | |
377 | " .byte 2b - 1b\n" /* source len */ | |
378 | " .byte 4f - 3f\n" /* replacement len */ | |
379 | ".previous\n" | |
380 | ".section .discard,\"aw\",@progbits\n" | |
381 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ | |
382 | ".previous\n" | |
383 | ".section .altinstr_replacement,\"ax\"\n" | |
384 | "3: movb $1,%0\n" | |
385 | "4:\n" | |
386 | ".previous\n" | |
387 | : "=qm" (flag) : "i" (bit)); | |
388 | return flag; | |
389 | #endif | |
390 | } | |
391 | ||
392 | #define static_cpu_has(bit) \ | |
393 | ( \ | |
394 | __builtin_constant_p(boot_cpu_has(bit)) ? \ | |
395 | boot_cpu_has(bit) : \ | |
396 | __builtin_constant_p(bit) ? \ | |
397 | __static_cpu_has(bit) : \ | |
398 | boot_cpu_has(bit) \ | |
399 | ) | |
400 | #else | |
401 | /* | |
402 | * gcc 3.x is too stupid to do the static test; fall back to dynamic. | |
403 | */ | |
404 | #define static_cpu_has(bit) boot_cpu_has(bit) | |
405 | #endif | |
406 | ||
407 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ | |
408 | ||
409 | #endif /* _ASM_X86_CPUFEATURE_H */ |