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1 | /* | |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/debugfs.h> | |
24 | #include <linux/scatterlist.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/iommu-helper.h> | |
27 | #include <linux/iommu.h> | |
28 | #include <asm/proto.h> | |
29 | #include <asm/iommu.h> | |
30 | #include <asm/gart.h> | |
31 | #include <asm/amd_iommu_types.h> | |
32 | #include <asm/amd_iommu.h> | |
33 | ||
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
36 | #define EXIT_LOOP_COUNT 10000000 | |
37 | ||
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); | |
39 | ||
40 | /* A list of preallocated protection domains */ | |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
44 | #ifdef CONFIG_IOMMU_API | |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
48 | /* | |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
51 | struct iommu_cmd { | |
52 | u32 data[4]; | |
53 | }; | |
54 | ||
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, | |
56 | struct unity_map_entry *e); | |
57 | static struct dma_ops_domain *find_protection_domain(u16 devid); | |
58 | static u64* alloc_pte(struct protection_domain *dom, | |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
64 | static u64 *fetch_pte(struct protection_domain *domain, | |
65 | unsigned long address); | |
66 | static void update_domain(struct protection_domain *domain); | |
67 | ||
68 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER | |
69 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
70 | #endif | |
71 | ||
72 | #ifdef CONFIG_AMD_IOMMU_STATS | |
73 | ||
74 | /* | |
75 | * Initialization code for statistics collection | |
76 | */ | |
77 | ||
78 | DECLARE_STATS_COUNTER(compl_wait); | |
79 | DECLARE_STATS_COUNTER(cnt_map_single); | |
80 | DECLARE_STATS_COUNTER(cnt_unmap_single); | |
81 | DECLARE_STATS_COUNTER(cnt_map_sg); | |
82 | DECLARE_STATS_COUNTER(cnt_unmap_sg); | |
83 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); | |
84 | DECLARE_STATS_COUNTER(cnt_free_coherent); | |
85 | DECLARE_STATS_COUNTER(cross_page); | |
86 | DECLARE_STATS_COUNTER(domain_flush_single); | |
87 | DECLARE_STATS_COUNTER(domain_flush_all); | |
88 | DECLARE_STATS_COUNTER(alloced_io_mem); | |
89 | DECLARE_STATS_COUNTER(total_map_requests); | |
90 | ||
91 | static struct dentry *stats_dir; | |
92 | static struct dentry *de_isolate; | |
93 | static struct dentry *de_fflush; | |
94 | ||
95 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
96 | { | |
97 | if (stats_dir == NULL) | |
98 | return; | |
99 | ||
100 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
101 | &cnt->value); | |
102 | } | |
103 | ||
104 | static void amd_iommu_stats_init(void) | |
105 | { | |
106 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
107 | if (stats_dir == NULL) | |
108 | return; | |
109 | ||
110 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
111 | (u32 *)&amd_iommu_isolate); | |
112 | ||
113 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
114 | (u32 *)&amd_iommu_unmap_flush); | |
115 | ||
116 | amd_iommu_stats_add(&compl_wait); | |
117 | amd_iommu_stats_add(&cnt_map_single); | |
118 | amd_iommu_stats_add(&cnt_unmap_single); | |
119 | amd_iommu_stats_add(&cnt_map_sg); | |
120 | amd_iommu_stats_add(&cnt_unmap_sg); | |
121 | amd_iommu_stats_add(&cnt_alloc_coherent); | |
122 | amd_iommu_stats_add(&cnt_free_coherent); | |
123 | amd_iommu_stats_add(&cross_page); | |
124 | amd_iommu_stats_add(&domain_flush_single); | |
125 | amd_iommu_stats_add(&domain_flush_all); | |
126 | amd_iommu_stats_add(&alloced_io_mem); | |
127 | amd_iommu_stats_add(&total_map_requests); | |
128 | } | |
129 | ||
130 | #endif | |
131 | ||
132 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ | |
133 | static int iommu_has_npcache(struct amd_iommu *iommu) | |
134 | { | |
135 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); | |
136 | } | |
137 | ||
138 | /**************************************************************************** | |
139 | * | |
140 | * Interrupt handling functions | |
141 | * | |
142 | ****************************************************************************/ | |
143 | ||
144 | static void iommu_print_event(void *__evt) | |
145 | { | |
146 | u32 *event = __evt; | |
147 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
148 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
149 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
150 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
151 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
152 | ||
153 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
154 | ||
155 | switch (type) { | |
156 | case EVENT_TYPE_ILL_DEV: | |
157 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
158 | "address=0x%016llx flags=0x%04x]\n", | |
159 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
160 | address, flags); | |
161 | break; | |
162 | case EVENT_TYPE_IO_FAULT: | |
163 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
164 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
165 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
166 | domid, address, flags); | |
167 | break; | |
168 | case EVENT_TYPE_DEV_TAB_ERR: | |
169 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
170 | "address=0x%016llx flags=0x%04x]\n", | |
171 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
172 | address, flags); | |
173 | break; | |
174 | case EVENT_TYPE_PAGE_TAB_ERR: | |
175 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
176 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
177 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
178 | domid, address, flags); | |
179 | break; | |
180 | case EVENT_TYPE_ILL_CMD: | |
181 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
182 | break; | |
183 | case EVENT_TYPE_CMD_HARD_ERR: | |
184 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
185 | "flags=0x%04x]\n", address, flags); | |
186 | break; | |
187 | case EVENT_TYPE_IOTLB_INV_TO: | |
188 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
189 | "address=0x%016llx]\n", | |
190 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
191 | address); | |
192 | break; | |
193 | case EVENT_TYPE_INV_DEV_REQ: | |
194 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
195 | "address=0x%016llx flags=0x%04x]\n", | |
196 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
197 | address, flags); | |
198 | break; | |
199 | default: | |
200 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
201 | } | |
202 | } | |
203 | ||
204 | static void iommu_poll_events(struct amd_iommu *iommu) | |
205 | { | |
206 | u32 head, tail; | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&iommu->lock, flags); | |
210 | ||
211 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
212 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
213 | ||
214 | while (head != tail) { | |
215 | iommu_print_event(iommu->evt_buf + head); | |
216 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
217 | } | |
218 | ||
219 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
220 | ||
221 | spin_unlock_irqrestore(&iommu->lock, flags); | |
222 | } | |
223 | ||
224 | irqreturn_t amd_iommu_int_handler(int irq, void *data) | |
225 | { | |
226 | struct amd_iommu *iommu; | |
227 | ||
228 | for_each_iommu(iommu) | |
229 | iommu_poll_events(iommu); | |
230 | ||
231 | return IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | /**************************************************************************** | |
235 | * | |
236 | * IOMMU command queuing functions | |
237 | * | |
238 | ****************************************************************************/ | |
239 | ||
240 | /* | |
241 | * Writes the command to the IOMMUs command buffer and informs the | |
242 | * hardware about the new command. Must be called with iommu->lock held. | |
243 | */ | |
244 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) | |
245 | { | |
246 | u32 tail, head; | |
247 | u8 *target; | |
248 | ||
249 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
250 | target = iommu->cmd_buf + tail; | |
251 | memcpy_toio(target, cmd, sizeof(*cmd)); | |
252 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
253 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
254 | if (tail == head) | |
255 | return -ENOMEM; | |
256 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | /* | |
262 | * General queuing function for commands. Takes iommu->lock and calls | |
263 | * __iommu_queue_command(). | |
264 | */ | |
265 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) | |
266 | { | |
267 | unsigned long flags; | |
268 | int ret; | |
269 | ||
270 | spin_lock_irqsave(&iommu->lock, flags); | |
271 | ret = __iommu_queue_command(iommu, cmd); | |
272 | if (!ret) | |
273 | iommu->need_sync = true; | |
274 | spin_unlock_irqrestore(&iommu->lock, flags); | |
275 | ||
276 | return ret; | |
277 | } | |
278 | ||
279 | /* | |
280 | * This function waits until an IOMMU has completed a completion | |
281 | * wait command | |
282 | */ | |
283 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
284 | { | |
285 | int ready = 0; | |
286 | unsigned status = 0; | |
287 | unsigned long i = 0; | |
288 | ||
289 | INC_STATS_COUNTER(compl_wait); | |
290 | ||
291 | while (!ready && (i < EXIT_LOOP_COUNT)) { | |
292 | ++i; | |
293 | /* wait for the bit to become one */ | |
294 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
295 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
296 | } | |
297 | ||
298 | /* set bit back to zero */ | |
299 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
300 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
301 | ||
302 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
303 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
304 | } | |
305 | ||
306 | /* | |
307 | * This function queues a completion wait command into the command | |
308 | * buffer of an IOMMU | |
309 | */ | |
310 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
311 | { | |
312 | struct iommu_cmd cmd; | |
313 | ||
314 | memset(&cmd, 0, sizeof(cmd)); | |
315 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
316 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
317 | ||
318 | return __iommu_queue_command(iommu, &cmd); | |
319 | } | |
320 | ||
321 | /* | |
322 | * This function is called whenever we need to ensure that the IOMMU has | |
323 | * completed execution of all commands we sent. It sends a | |
324 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
325 | * us about that by writing a value to a physical address we pass with | |
326 | * the command. | |
327 | */ | |
328 | static int iommu_completion_wait(struct amd_iommu *iommu) | |
329 | { | |
330 | int ret = 0; | |
331 | unsigned long flags; | |
332 | ||
333 | spin_lock_irqsave(&iommu->lock, flags); | |
334 | ||
335 | if (!iommu->need_sync) | |
336 | goto out; | |
337 | ||
338 | ret = __iommu_completion_wait(iommu); | |
339 | ||
340 | iommu->need_sync = false; | |
341 | ||
342 | if (ret) | |
343 | goto out; | |
344 | ||
345 | __iommu_wait_for_completion(iommu); | |
346 | ||
347 | out: | |
348 | spin_unlock_irqrestore(&iommu->lock, flags); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Command send function for invalidating a device table entry | |
355 | */ | |
356 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) | |
357 | { | |
358 | struct iommu_cmd cmd; | |
359 | int ret; | |
360 | ||
361 | BUG_ON(iommu == NULL); | |
362 | ||
363 | memset(&cmd, 0, sizeof(cmd)); | |
364 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
365 | cmd.data[0] = devid; | |
366 | ||
367 | ret = iommu_queue_command(iommu, &cmd); | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, | |
373 | u16 domid, int pde, int s) | |
374 | { | |
375 | memset(cmd, 0, sizeof(*cmd)); | |
376 | address &= PAGE_MASK; | |
377 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
378 | cmd->data[1] |= domid; | |
379 | cmd->data[2] = lower_32_bits(address); | |
380 | cmd->data[3] = upper_32_bits(address); | |
381 | if (s) /* size bit - we flush more than one 4kb page */ | |
382 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
383 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
384 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
385 | } | |
386 | ||
387 | /* | |
388 | * Generic command send function for invalidaing TLB entries | |
389 | */ | |
390 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, | |
391 | u64 address, u16 domid, int pde, int s) | |
392 | { | |
393 | struct iommu_cmd cmd; | |
394 | int ret; | |
395 | ||
396 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); | |
397 | ||
398 | ret = iommu_queue_command(iommu, &cmd); | |
399 | ||
400 | return ret; | |
401 | } | |
402 | ||
403 | /* | |
404 | * TLB invalidation function which is called from the mapping functions. | |
405 | * It invalidates a single PTE if the range to flush is within a single | |
406 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
407 | */ | |
408 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, | |
409 | u64 address, size_t size) | |
410 | { | |
411 | int s = 0; | |
412 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); | |
413 | ||
414 | address &= PAGE_MASK; | |
415 | ||
416 | if (pages > 1) { | |
417 | /* | |
418 | * If we have to flush more than one page, flush all | |
419 | * TLB entries for this domain | |
420 | */ | |
421 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
422 | s = 1; | |
423 | } | |
424 | ||
425 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | /* Flush the whole IO/TLB for a given protection domain */ | |
431 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
432 | { | |
433 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
434 | ||
435 | INC_STATS_COUNTER(domain_flush_single); | |
436 | ||
437 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
438 | } | |
439 | ||
440 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ | |
441 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
442 | { | |
443 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
444 | ||
445 | INC_STATS_COUNTER(domain_flush_single); | |
446 | ||
447 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
448 | } | |
449 | ||
450 | /* | |
451 | * This function is used to flush the IO/TLB for a given protection domain | |
452 | * on every IOMMU in the system | |
453 | */ | |
454 | static void iommu_flush_domain(u16 domid) | |
455 | { | |
456 | unsigned long flags; | |
457 | struct amd_iommu *iommu; | |
458 | struct iommu_cmd cmd; | |
459 | ||
460 | INC_STATS_COUNTER(domain_flush_all); | |
461 | ||
462 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
463 | domid, 1, 1); | |
464 | ||
465 | for_each_iommu(iommu) { | |
466 | spin_lock_irqsave(&iommu->lock, flags); | |
467 | __iommu_queue_command(iommu, &cmd); | |
468 | __iommu_completion_wait(iommu); | |
469 | __iommu_wait_for_completion(iommu); | |
470 | spin_unlock_irqrestore(&iommu->lock, flags); | |
471 | } | |
472 | } | |
473 | ||
474 | void amd_iommu_flush_all_domains(void) | |
475 | { | |
476 | int i; | |
477 | ||
478 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
479 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
480 | continue; | |
481 | iommu_flush_domain(i); | |
482 | } | |
483 | } | |
484 | ||
485 | static void flush_devices_by_domain(struct protection_domain *domain) | |
486 | { | |
487 | struct amd_iommu *iommu; | |
488 | int i; | |
489 | ||
490 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
491 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || | |
492 | (amd_iommu_pd_table[i] != domain)) | |
493 | continue; | |
494 | ||
495 | iommu = amd_iommu_rlookup_table[i]; | |
496 | if (!iommu) | |
497 | continue; | |
498 | ||
499 | iommu_queue_inv_dev_entry(iommu, i); | |
500 | iommu_completion_wait(iommu); | |
501 | } | |
502 | } | |
503 | ||
504 | void amd_iommu_flush_all_devices(void) | |
505 | { | |
506 | flush_devices_by_domain(NULL); | |
507 | } | |
508 | ||
509 | /**************************************************************************** | |
510 | * | |
511 | * The functions below are used the create the page table mappings for | |
512 | * unity mapped regions. | |
513 | * | |
514 | ****************************************************************************/ | |
515 | ||
516 | /* | |
517 | * Generic mapping functions. It maps a physical address into a DMA | |
518 | * address space. It allocates the page table pages if necessary. | |
519 | * In the future it can be extended to a generic mapping function | |
520 | * supporting all features of AMD IOMMU page tables like level skipping | |
521 | * and full 64 bit address spaces. | |
522 | */ | |
523 | static int iommu_map_page(struct protection_domain *dom, | |
524 | unsigned long bus_addr, | |
525 | unsigned long phys_addr, | |
526 | int prot) | |
527 | { | |
528 | u64 __pte, *pte; | |
529 | ||
530 | bus_addr = PAGE_ALIGN(bus_addr); | |
531 | phys_addr = PAGE_ALIGN(phys_addr); | |
532 | ||
533 | /* only support 512GB address spaces for now */ | |
534 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
535 | return -EINVAL; | |
536 | ||
537 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); | |
538 | ||
539 | if (IOMMU_PTE_PRESENT(*pte)) | |
540 | return -EBUSY; | |
541 | ||
542 | __pte = phys_addr | IOMMU_PTE_P; | |
543 | if (prot & IOMMU_PROT_IR) | |
544 | __pte |= IOMMU_PTE_IR; | |
545 | if (prot & IOMMU_PROT_IW) | |
546 | __pte |= IOMMU_PTE_IW; | |
547 | ||
548 | *pte = __pte; | |
549 | ||
550 | update_domain(dom); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | static void iommu_unmap_page(struct protection_domain *dom, | |
556 | unsigned long bus_addr) | |
557 | { | |
558 | u64 *pte = fetch_pte(dom, bus_addr); | |
559 | ||
560 | if (pte) | |
561 | *pte = 0; | |
562 | } | |
563 | ||
564 | /* | |
565 | * This function checks if a specific unity mapping entry is needed for | |
566 | * this specific IOMMU. | |
567 | */ | |
568 | static int iommu_for_unity_map(struct amd_iommu *iommu, | |
569 | struct unity_map_entry *entry) | |
570 | { | |
571 | u16 bdf, i; | |
572 | ||
573 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
574 | bdf = amd_iommu_alias_table[i]; | |
575 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
576 | return 1; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Init the unity mappings for a specific IOMMU in the system | |
584 | * | |
585 | * Basically iterates over all unity mapping entries and applies them to | |
586 | * the default domain DMA of that IOMMU if necessary. | |
587 | */ | |
588 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
589 | { | |
590 | struct unity_map_entry *entry; | |
591 | int ret; | |
592 | ||
593 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
594 | if (!iommu_for_unity_map(iommu, entry)) | |
595 | continue; | |
596 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
597 | if (ret) | |
598 | return ret; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | /* | |
605 | * This function actually applies the mapping to the page table of the | |
606 | * dma_ops domain. | |
607 | */ | |
608 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, | |
609 | struct unity_map_entry *e) | |
610 | { | |
611 | u64 addr; | |
612 | int ret; | |
613 | ||
614 | for (addr = e->address_start; addr < e->address_end; | |
615 | addr += PAGE_SIZE) { | |
616 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); | |
617 | if (ret) | |
618 | return ret; | |
619 | /* | |
620 | * if unity mapping is in aperture range mark the page | |
621 | * as allocated in the aperture | |
622 | */ | |
623 | if (addr < dma_dom->aperture_size) | |
624 | __set_bit(addr >> PAGE_SHIFT, | |
625 | dma_dom->aperture[0]->bitmap); | |
626 | } | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | /* | |
632 | * Inits the unity mappings required for a specific device | |
633 | */ | |
634 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, | |
635 | u16 devid) | |
636 | { | |
637 | struct unity_map_entry *e; | |
638 | int ret; | |
639 | ||
640 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
641 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
642 | continue; | |
643 | ret = dma_ops_unity_map(dma_dom, e); | |
644 | if (ret) | |
645 | return ret; | |
646 | } | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /**************************************************************************** | |
652 | * | |
653 | * The next functions belong to the address allocator for the dma_ops | |
654 | * interface functions. They work like the allocators in the other IOMMU | |
655 | * drivers. Its basically a bitmap which marks the allocated pages in | |
656 | * the aperture. Maybe it could be enhanced in the future to a more | |
657 | * efficient allocator. | |
658 | * | |
659 | ****************************************************************************/ | |
660 | ||
661 | /* | |
662 | * The address allocator core functions. | |
663 | * | |
664 | * called with domain->lock held | |
665 | */ | |
666 | ||
667 | /* | |
668 | * This function checks if there is a PTE for a given dma address. If | |
669 | * there is one, it returns the pointer to it. | |
670 | */ | |
671 | static u64 *fetch_pte(struct protection_domain *domain, | |
672 | unsigned long address) | |
673 | { | |
674 | int level; | |
675 | u64 *pte; | |
676 | ||
677 | level = domain->mode - 1; | |
678 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
679 | ||
680 | while (level > 0) { | |
681 | if (!IOMMU_PTE_PRESENT(*pte)) | |
682 | return NULL; | |
683 | ||
684 | level -= 1; | |
685 | ||
686 | pte = IOMMU_PTE_PAGE(*pte); | |
687 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
688 | } | |
689 | ||
690 | return pte; | |
691 | } | |
692 | ||
693 | /* | |
694 | * This function is used to add a new aperture range to an existing | |
695 | * aperture in case of dma_ops domain allocation or address allocation | |
696 | * failure. | |
697 | */ | |
698 | static int alloc_new_range(struct amd_iommu *iommu, | |
699 | struct dma_ops_domain *dma_dom, | |
700 | bool populate, gfp_t gfp) | |
701 | { | |
702 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
703 | int i; | |
704 | ||
705 | #ifdef CONFIG_IOMMU_STRESS | |
706 | populate = false; | |
707 | #endif | |
708 | ||
709 | if (index >= APERTURE_MAX_RANGES) | |
710 | return -ENOMEM; | |
711 | ||
712 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
713 | if (!dma_dom->aperture[index]) | |
714 | return -ENOMEM; | |
715 | ||
716 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
717 | if (!dma_dom->aperture[index]->bitmap) | |
718 | goto out_free; | |
719 | ||
720 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
721 | ||
722 | if (populate) { | |
723 | unsigned long address = dma_dom->aperture_size; | |
724 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
725 | u64 *pte, *pte_page; | |
726 | ||
727 | for (i = 0; i < num_ptes; ++i) { | |
728 | pte = alloc_pte(&dma_dom->domain, address, | |
729 | &pte_page, gfp); | |
730 | if (!pte) | |
731 | goto out_free; | |
732 | ||
733 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
734 | ||
735 | address += APERTURE_RANGE_SIZE / 64; | |
736 | } | |
737 | } | |
738 | ||
739 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
740 | ||
741 | /* Intialize the exclusion range if necessary */ | |
742 | if (iommu->exclusion_start && | |
743 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
744 | iommu->exclusion_start < dma_dom->aperture_size) { | |
745 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
746 | int pages = iommu_num_pages(iommu->exclusion_start, | |
747 | iommu->exclusion_length, | |
748 | PAGE_SIZE); | |
749 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
750 | } | |
751 | ||
752 | /* | |
753 | * Check for areas already mapped as present in the new aperture | |
754 | * range and mark those pages as reserved in the allocator. Such | |
755 | * mappings may already exist as a result of requested unity | |
756 | * mappings for devices. | |
757 | */ | |
758 | for (i = dma_dom->aperture[index]->offset; | |
759 | i < dma_dom->aperture_size; | |
760 | i += PAGE_SIZE) { | |
761 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
762 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
763 | continue; | |
764 | ||
765 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
766 | } | |
767 | ||
768 | update_domain(&dma_dom->domain); | |
769 | ||
770 | return 0; | |
771 | ||
772 | out_free: | |
773 | update_domain(&dma_dom->domain); | |
774 | ||
775 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
776 | ||
777 | kfree(dma_dom->aperture[index]); | |
778 | dma_dom->aperture[index] = NULL; | |
779 | ||
780 | return -ENOMEM; | |
781 | } | |
782 | ||
783 | static unsigned long dma_ops_area_alloc(struct device *dev, | |
784 | struct dma_ops_domain *dom, | |
785 | unsigned int pages, | |
786 | unsigned long align_mask, | |
787 | u64 dma_mask, | |
788 | unsigned long start) | |
789 | { | |
790 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; | |
791 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
792 | int i = start >> APERTURE_RANGE_SHIFT; | |
793 | unsigned long boundary_size; | |
794 | unsigned long address = -1; | |
795 | unsigned long limit; | |
796 | ||
797 | next_bit >>= PAGE_SHIFT; | |
798 | ||
799 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
800 | PAGE_SIZE) >> PAGE_SHIFT; | |
801 | ||
802 | for (;i < max_index; ++i) { | |
803 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
804 | ||
805 | if (dom->aperture[i]->offset >= dma_mask) | |
806 | break; | |
807 | ||
808 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
809 | dma_mask >> PAGE_SHIFT); | |
810 | ||
811 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
812 | limit, next_bit, pages, 0, | |
813 | boundary_size, align_mask); | |
814 | if (address != -1) { | |
815 | address = dom->aperture[i]->offset + | |
816 | (address << PAGE_SHIFT); | |
817 | dom->next_address = address + (pages << PAGE_SHIFT); | |
818 | break; | |
819 | } | |
820 | ||
821 | next_bit = 0; | |
822 | } | |
823 | ||
824 | return address; | |
825 | } | |
826 | ||
827 | static unsigned long dma_ops_alloc_addresses(struct device *dev, | |
828 | struct dma_ops_domain *dom, | |
829 | unsigned int pages, | |
830 | unsigned long align_mask, | |
831 | u64 dma_mask) | |
832 | { | |
833 | unsigned long address; | |
834 | ||
835 | #ifdef CONFIG_IOMMU_STRESS | |
836 | dom->next_address = 0; | |
837 | dom->need_flush = true; | |
838 | #endif | |
839 | ||
840 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, | |
841 | dma_mask, dom->next_address); | |
842 | ||
843 | if (address == -1) { | |
844 | dom->next_address = 0; | |
845 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, | |
846 | dma_mask, 0); | |
847 | dom->need_flush = true; | |
848 | } | |
849 | ||
850 | if (unlikely(address == -1)) | |
851 | address = bad_dma_address; | |
852 | ||
853 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
854 | ||
855 | return address; | |
856 | } | |
857 | ||
858 | /* | |
859 | * The address free function. | |
860 | * | |
861 | * called with domain->lock held | |
862 | */ | |
863 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, | |
864 | unsigned long address, | |
865 | unsigned int pages) | |
866 | { | |
867 | unsigned i = address >> APERTURE_RANGE_SHIFT; | |
868 | struct aperture_range *range = dom->aperture[i]; | |
869 | ||
870 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); | |
871 | ||
872 | #ifdef CONFIG_IOMMU_STRESS | |
873 | if (i < 4) | |
874 | return; | |
875 | #endif | |
876 | ||
877 | if (address >= dom->next_address) | |
878 | dom->need_flush = true; | |
879 | ||
880 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
881 | ||
882 | iommu_area_free(range->bitmap, address, pages); | |
883 | ||
884 | } | |
885 | ||
886 | /**************************************************************************** | |
887 | * | |
888 | * The next functions belong to the domain allocation. A domain is | |
889 | * allocated for every IOMMU as the default domain. If device isolation | |
890 | * is enabled, every device get its own domain. The most important thing | |
891 | * about domains is the page table mapping the DMA address space they | |
892 | * contain. | |
893 | * | |
894 | ****************************************************************************/ | |
895 | ||
896 | static u16 domain_id_alloc(void) | |
897 | { | |
898 | unsigned long flags; | |
899 | int id; | |
900 | ||
901 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
902 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
903 | BUG_ON(id == 0); | |
904 | if (id > 0 && id < MAX_DOMAIN_ID) | |
905 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
906 | else | |
907 | id = 0; | |
908 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
909 | ||
910 | return id; | |
911 | } | |
912 | ||
913 | static void domain_id_free(int id) | |
914 | { | |
915 | unsigned long flags; | |
916 | ||
917 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
918 | if (id > 0 && id < MAX_DOMAIN_ID) | |
919 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
920 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
921 | } | |
922 | ||
923 | /* | |
924 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
925 | * ranges. | |
926 | */ | |
927 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
928 | unsigned long start_page, | |
929 | unsigned int pages) | |
930 | { | |
931 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
932 | ||
933 | if (start_page + pages > last_page) | |
934 | pages = last_page - start_page; | |
935 | ||
936 | for (i = start_page; i < start_page + pages; ++i) { | |
937 | int index = i / APERTURE_RANGE_PAGES; | |
938 | int page = i % APERTURE_RANGE_PAGES; | |
939 | __set_bit(page, dom->aperture[index]->bitmap); | |
940 | } | |
941 | } | |
942 | ||
943 | static void free_pagetable(struct protection_domain *domain) | |
944 | { | |
945 | int i, j; | |
946 | u64 *p1, *p2, *p3; | |
947 | ||
948 | p1 = domain->pt_root; | |
949 | ||
950 | if (!p1) | |
951 | return; | |
952 | ||
953 | for (i = 0; i < 512; ++i) { | |
954 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
955 | continue; | |
956 | ||
957 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
958 | for (j = 0; j < 512; ++j) { | |
959 | if (!IOMMU_PTE_PRESENT(p2[j])) | |
960 | continue; | |
961 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
962 | free_page((unsigned long)p3); | |
963 | } | |
964 | ||
965 | free_page((unsigned long)p2); | |
966 | } | |
967 | ||
968 | free_page((unsigned long)p1); | |
969 | ||
970 | domain->pt_root = NULL; | |
971 | } | |
972 | ||
973 | /* | |
974 | * Free a domain, only used if something went wrong in the | |
975 | * allocation path and we need to free an already allocated page table | |
976 | */ | |
977 | static void dma_ops_domain_free(struct dma_ops_domain *dom) | |
978 | { | |
979 | int i; | |
980 | ||
981 | if (!dom) | |
982 | return; | |
983 | ||
984 | free_pagetable(&dom->domain); | |
985 | ||
986 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { | |
987 | if (!dom->aperture[i]) | |
988 | continue; | |
989 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
990 | kfree(dom->aperture[i]); | |
991 | } | |
992 | ||
993 | kfree(dom); | |
994 | } | |
995 | ||
996 | /* | |
997 | * Allocates a new protection domain usable for the dma_ops functions. | |
998 | * It also intializes the page table and the address allocator data | |
999 | * structures required for the dma_ops interface | |
1000 | */ | |
1001 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) | |
1002 | { | |
1003 | struct dma_ops_domain *dma_dom; | |
1004 | ||
1005 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1006 | if (!dma_dom) | |
1007 | return NULL; | |
1008 | ||
1009 | spin_lock_init(&dma_dom->domain.lock); | |
1010 | ||
1011 | dma_dom->domain.id = domain_id_alloc(); | |
1012 | if (dma_dom->domain.id == 0) | |
1013 | goto free_dma_dom; | |
1014 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1015 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1016 | dma_dom->domain.flags = PD_DMA_OPS_MASK; | |
1017 | dma_dom->domain.priv = dma_dom; | |
1018 | if (!dma_dom->domain.pt_root) | |
1019 | goto free_dma_dom; | |
1020 | ||
1021 | dma_dom->need_flush = false; | |
1022 | dma_dom->target_dev = 0xffff; | |
1023 | ||
1024 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) | |
1025 | goto free_dma_dom; | |
1026 | ||
1027 | /* | |
1028 | * mark the first page as allocated so we never return 0 as | |
1029 | * a valid dma-address. So we can use 0 as error value | |
1030 | */ | |
1031 | dma_dom->aperture[0]->bitmap[0] = 1; | |
1032 | dma_dom->next_address = 0; | |
1033 | ||
1034 | ||
1035 | return dma_dom; | |
1036 | ||
1037 | free_dma_dom: | |
1038 | dma_ops_domain_free(dma_dom); | |
1039 | ||
1040 | return NULL; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * little helper function to check whether a given protection domain is a | |
1045 | * dma_ops domain | |
1046 | */ | |
1047 | static bool dma_ops_domain(struct protection_domain *domain) | |
1048 | { | |
1049 | return domain->flags & PD_DMA_OPS_MASK; | |
1050 | } | |
1051 | ||
1052 | /* | |
1053 | * Find out the protection domain structure for a given PCI device. This | |
1054 | * will give us the pointer to the page table root for example. | |
1055 | */ | |
1056 | static struct protection_domain *domain_for_device(u16 devid) | |
1057 | { | |
1058 | struct protection_domain *dom; | |
1059 | unsigned long flags; | |
1060 | ||
1061 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1062 | dom = amd_iommu_pd_table[devid]; | |
1063 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1064 | ||
1065 | return dom; | |
1066 | } | |
1067 | ||
1068 | static void set_dte_entry(u16 devid, struct protection_domain *domain) | |
1069 | { | |
1070 | u64 pte_root = virt_to_phys(domain->pt_root); | |
1071 | unsigned long flags; | |
1072 | ||
1073 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) | |
1074 | << DEV_ENTRY_MODE_SHIFT; | |
1075 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
1076 | ||
1077 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1078 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
1079 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1080 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1081 | ||
1082 | amd_iommu_pd_table[devid] = domain; | |
1083 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * If a device is not yet associated with a domain, this function does | |
1088 | * assigns it visible for the hardware | |
1089 | */ | |
1090 | static void attach_device(struct amd_iommu *iommu, | |
1091 | struct protection_domain *domain, | |
1092 | u16 devid) | |
1093 | { | |
1094 | /* set the DTE entry */ | |
1095 | set_dte_entry(devid, domain); | |
1096 | ||
1097 | /* increase reference counter */ | |
1098 | domain->dev_cnt += 1; | |
1099 | ||
1100 | /* | |
1101 | * We might boot into a crash-kernel here. The crashed kernel | |
1102 | * left the caches in the IOMMU dirty. So we have to flush | |
1103 | * here to evict all dirty stuff. | |
1104 | */ | |
1105 | iommu_queue_inv_dev_entry(iommu, devid); | |
1106 | iommu_flush_tlb_pde(iommu, domain->id); | |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * Removes a device from a protection domain (unlocked) | |
1111 | */ | |
1112 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1113 | { | |
1114 | ||
1115 | /* lock domain */ | |
1116 | spin_lock(&domain->lock); | |
1117 | ||
1118 | /* remove domain from the lookup table */ | |
1119 | amd_iommu_pd_table[devid] = NULL; | |
1120 | ||
1121 | /* remove entry from the device table seen by the hardware */ | |
1122 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1123 | amd_iommu_dev_table[devid].data[1] = 0; | |
1124 | amd_iommu_dev_table[devid].data[2] = 0; | |
1125 | ||
1126 | /* decrease reference counter */ | |
1127 | domain->dev_cnt -= 1; | |
1128 | ||
1129 | /* ready */ | |
1130 | spin_unlock(&domain->lock); | |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * Removes a device from a protection domain (with devtable_lock held) | |
1135 | */ | |
1136 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1137 | { | |
1138 | unsigned long flags; | |
1139 | ||
1140 | /* lock device table */ | |
1141 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1142 | __detach_device(domain, devid); | |
1143 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1144 | } | |
1145 | ||
1146 | static int device_change_notifier(struct notifier_block *nb, | |
1147 | unsigned long action, void *data) | |
1148 | { | |
1149 | struct device *dev = data; | |
1150 | struct pci_dev *pdev = to_pci_dev(dev); | |
1151 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1152 | struct protection_domain *domain; | |
1153 | struct dma_ops_domain *dma_domain; | |
1154 | struct amd_iommu *iommu; | |
1155 | unsigned long flags; | |
1156 | ||
1157 | if (devid > amd_iommu_last_bdf) | |
1158 | goto out; | |
1159 | ||
1160 | devid = amd_iommu_alias_table[devid]; | |
1161 | ||
1162 | iommu = amd_iommu_rlookup_table[devid]; | |
1163 | if (iommu == NULL) | |
1164 | goto out; | |
1165 | ||
1166 | domain = domain_for_device(devid); | |
1167 | ||
1168 | if (domain && !dma_ops_domain(domain)) | |
1169 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1170 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1171 | ||
1172 | switch (action) { | |
1173 | case BUS_NOTIFY_UNBOUND_DRIVER: | |
1174 | if (!domain) | |
1175 | goto out; | |
1176 | detach_device(domain, devid); | |
1177 | break; | |
1178 | case BUS_NOTIFY_ADD_DEVICE: | |
1179 | /* allocate a protection domain if a device is added */ | |
1180 | dma_domain = find_protection_domain(devid); | |
1181 | if (dma_domain) | |
1182 | goto out; | |
1183 | dma_domain = dma_ops_domain_alloc(iommu); | |
1184 | if (!dma_domain) | |
1185 | goto out; | |
1186 | dma_domain->target_dev = devid; | |
1187 | ||
1188 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1189 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1190 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1191 | ||
1192 | break; | |
1193 | default: | |
1194 | goto out; | |
1195 | } | |
1196 | ||
1197 | iommu_queue_inv_dev_entry(iommu, devid); | |
1198 | iommu_completion_wait(iommu); | |
1199 | ||
1200 | out: | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static struct notifier_block device_nb = { | |
1205 | .notifier_call = device_change_notifier, | |
1206 | }; | |
1207 | ||
1208 | /***************************************************************************** | |
1209 | * | |
1210 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1211 | * | |
1212 | *****************************************************************************/ | |
1213 | ||
1214 | /* | |
1215 | * This function checks if the driver got a valid device from the caller to | |
1216 | * avoid dereferencing invalid pointers. | |
1217 | */ | |
1218 | static bool check_device(struct device *dev) | |
1219 | { | |
1220 | if (!dev || !dev->dma_mask) | |
1221 | return false; | |
1222 | ||
1223 | return true; | |
1224 | } | |
1225 | ||
1226 | /* | |
1227 | * In this function the list of preallocated protection domains is traversed to | |
1228 | * find the domain for a specific device | |
1229 | */ | |
1230 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1231 | { | |
1232 | struct dma_ops_domain *entry, *ret = NULL; | |
1233 | unsigned long flags; | |
1234 | ||
1235 | if (list_empty(&iommu_pd_list)) | |
1236 | return NULL; | |
1237 | ||
1238 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1239 | ||
1240 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1241 | if (entry->target_dev == devid) { | |
1242 | ret = entry; | |
1243 | break; | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1248 | ||
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | /* | |
1253 | * In the dma_ops path we only have the struct device. This function | |
1254 | * finds the corresponding IOMMU, the protection domain and the | |
1255 | * requestor id for a given device. | |
1256 | * If the device is not yet associated with a domain this is also done | |
1257 | * in this function. | |
1258 | */ | |
1259 | static int get_device_resources(struct device *dev, | |
1260 | struct amd_iommu **iommu, | |
1261 | struct protection_domain **domain, | |
1262 | u16 *bdf) | |
1263 | { | |
1264 | struct dma_ops_domain *dma_dom; | |
1265 | struct pci_dev *pcidev; | |
1266 | u16 _bdf; | |
1267 | ||
1268 | *iommu = NULL; | |
1269 | *domain = NULL; | |
1270 | *bdf = 0xffff; | |
1271 | ||
1272 | if (dev->bus != &pci_bus_type) | |
1273 | return 0; | |
1274 | ||
1275 | pcidev = to_pci_dev(dev); | |
1276 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1277 | ||
1278 | /* device not translated by any IOMMU in the system? */ | |
1279 | if (_bdf > amd_iommu_last_bdf) | |
1280 | return 0; | |
1281 | ||
1282 | *bdf = amd_iommu_alias_table[_bdf]; | |
1283 | ||
1284 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1285 | if (*iommu == NULL) | |
1286 | return 0; | |
1287 | *domain = domain_for_device(*bdf); | |
1288 | if (*domain == NULL) { | |
1289 | dma_dom = find_protection_domain(*bdf); | |
1290 | if (!dma_dom) | |
1291 | dma_dom = (*iommu)->default_dom; | |
1292 | *domain = &dma_dom->domain; | |
1293 | attach_device(*iommu, *domain, *bdf); | |
1294 | DUMP_printk("Using protection domain %d for device %s\n", | |
1295 | (*domain)->id, dev_name(dev)); | |
1296 | } | |
1297 | ||
1298 | if (domain_for_device(_bdf) == NULL) | |
1299 | attach_device(*iommu, *domain, _bdf); | |
1300 | ||
1301 | return 1; | |
1302 | } | |
1303 | ||
1304 | static void update_device_table(struct protection_domain *domain) | |
1305 | { | |
1306 | int i; | |
1307 | ||
1308 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1309 | if (amd_iommu_pd_table[i] != domain) | |
1310 | continue; | |
1311 | set_dte_entry(i, domain); | |
1312 | } | |
1313 | } | |
1314 | ||
1315 | static void update_domain(struct protection_domain *domain) | |
1316 | { | |
1317 | if (!domain->updated) | |
1318 | return; | |
1319 | ||
1320 | update_device_table(domain); | |
1321 | flush_devices_by_domain(domain); | |
1322 | iommu_flush_domain(domain->id); | |
1323 | ||
1324 | domain->updated = false; | |
1325 | } | |
1326 | ||
1327 | /* | |
1328 | * This function is used to add another level to an IO page table. Adding | |
1329 | * another level increases the size of the address space by 9 bits to a size up | |
1330 | * to 64 bits. | |
1331 | */ | |
1332 | static bool increase_address_space(struct protection_domain *domain, | |
1333 | gfp_t gfp) | |
1334 | { | |
1335 | u64 *pte; | |
1336 | ||
1337 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1338 | /* address space already 64 bit large */ | |
1339 | return false; | |
1340 | ||
1341 | pte = (void *)get_zeroed_page(gfp); | |
1342 | if (!pte) | |
1343 | return false; | |
1344 | ||
1345 | *pte = PM_LEVEL_PDE(domain->mode, | |
1346 | virt_to_phys(domain->pt_root)); | |
1347 | domain->pt_root = pte; | |
1348 | domain->mode += 1; | |
1349 | domain->updated = true; | |
1350 | ||
1351 | return true; | |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * If the pte_page is not yet allocated this function is called | |
1356 | */ | |
1357 | static u64* alloc_pte(struct protection_domain *dom, | |
1358 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1359 | { | |
1360 | u64 *pte, *page; | |
1361 | ||
1362 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1363 | ||
1364 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1365 | page = (u64 *)get_zeroed_page(gfp); | |
1366 | if (!page) | |
1367 | return NULL; | |
1368 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1369 | } | |
1370 | ||
1371 | pte = IOMMU_PTE_PAGE(*pte); | |
1372 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1373 | ||
1374 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1375 | page = (u64 *)get_zeroed_page(gfp); | |
1376 | if (!page) | |
1377 | return NULL; | |
1378 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1379 | } | |
1380 | ||
1381 | pte = IOMMU_PTE_PAGE(*pte); | |
1382 | ||
1383 | if (pte_page) | |
1384 | *pte_page = pte; | |
1385 | ||
1386 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1387 | ||
1388 | return pte; | |
1389 | } | |
1390 | ||
1391 | /* | |
1392 | * This function fetches the PTE for a given address in the aperture | |
1393 | */ | |
1394 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1395 | unsigned long address) | |
1396 | { | |
1397 | struct aperture_range *aperture; | |
1398 | u64 *pte, *pte_page; | |
1399 | ||
1400 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; | |
1401 | if (!aperture) | |
1402 | return NULL; | |
1403 | ||
1404 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1405 | if (!pte) { | |
1406 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
1407 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; | |
1408 | } else | |
1409 | pte += IOMMU_PTE_L0_INDEX(address); | |
1410 | ||
1411 | update_domain(&dom->domain); | |
1412 | ||
1413 | return pte; | |
1414 | } | |
1415 | ||
1416 | /* | |
1417 | * This is the generic map function. It maps one 4kb page at paddr to | |
1418 | * the given address in the DMA address space for the domain. | |
1419 | */ | |
1420 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, | |
1421 | struct dma_ops_domain *dom, | |
1422 | unsigned long address, | |
1423 | phys_addr_t paddr, | |
1424 | int direction) | |
1425 | { | |
1426 | u64 *pte, __pte; | |
1427 | ||
1428 | WARN_ON(address > dom->aperture_size); | |
1429 | ||
1430 | paddr &= PAGE_MASK; | |
1431 | ||
1432 | pte = dma_ops_get_pte(dom, address); | |
1433 | if (!pte) | |
1434 | return bad_dma_address; | |
1435 | ||
1436 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1437 | ||
1438 | if (direction == DMA_TO_DEVICE) | |
1439 | __pte |= IOMMU_PTE_IR; | |
1440 | else if (direction == DMA_FROM_DEVICE) | |
1441 | __pte |= IOMMU_PTE_IW; | |
1442 | else if (direction == DMA_BIDIRECTIONAL) | |
1443 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1444 | ||
1445 | WARN_ON(*pte); | |
1446 | ||
1447 | *pte = __pte; | |
1448 | ||
1449 | return (dma_addr_t)address; | |
1450 | } | |
1451 | ||
1452 | /* | |
1453 | * The generic unmapping function for on page in the DMA address space. | |
1454 | */ | |
1455 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, | |
1456 | struct dma_ops_domain *dom, | |
1457 | unsigned long address) | |
1458 | { | |
1459 | struct aperture_range *aperture; | |
1460 | u64 *pte; | |
1461 | ||
1462 | if (address >= dom->aperture_size) | |
1463 | return; | |
1464 | ||
1465 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; | |
1466 | if (!aperture) | |
1467 | return; | |
1468 | ||
1469 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1470 | if (!pte) | |
1471 | return; | |
1472 | ||
1473 | pte += IOMMU_PTE_L0_INDEX(address); | |
1474 | ||
1475 | WARN_ON(!*pte); | |
1476 | ||
1477 | *pte = 0ULL; | |
1478 | } | |
1479 | ||
1480 | /* | |
1481 | * This function contains common code for mapping of a physically | |
1482 | * contiguous memory region into DMA address space. It is used by all | |
1483 | * mapping functions provided with this IOMMU driver. | |
1484 | * Must be called with the domain lock held. | |
1485 | */ | |
1486 | static dma_addr_t __map_single(struct device *dev, | |
1487 | struct amd_iommu *iommu, | |
1488 | struct dma_ops_domain *dma_dom, | |
1489 | phys_addr_t paddr, | |
1490 | size_t size, | |
1491 | int dir, | |
1492 | bool align, | |
1493 | u64 dma_mask) | |
1494 | { | |
1495 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1496 | dma_addr_t address, start, ret; | |
1497 | unsigned int pages; | |
1498 | unsigned long align_mask = 0; | |
1499 | int i; | |
1500 | ||
1501 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1502 | paddr &= PAGE_MASK; | |
1503 | ||
1504 | INC_STATS_COUNTER(total_map_requests); | |
1505 | ||
1506 | if (pages > 1) | |
1507 | INC_STATS_COUNTER(cross_page); | |
1508 | ||
1509 | if (align) | |
1510 | align_mask = (1UL << get_order(size)) - 1; | |
1511 | ||
1512 | retry: | |
1513 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, | |
1514 | dma_mask); | |
1515 | if (unlikely(address == bad_dma_address)) { | |
1516 | /* | |
1517 | * setting next_address here will let the address | |
1518 | * allocator only scan the new allocated range in the | |
1519 | * first run. This is a small optimization. | |
1520 | */ | |
1521 | dma_dom->next_address = dma_dom->aperture_size; | |
1522 | ||
1523 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1524 | goto out; | |
1525 | ||
1526 | /* | |
1527 | * aperture was sucessfully enlarged by 128 MB, try | |
1528 | * allocation again | |
1529 | */ | |
1530 | goto retry; | |
1531 | } | |
1532 | ||
1533 | start = address; | |
1534 | for (i = 0; i < pages; ++i) { | |
1535 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1536 | if (ret == bad_dma_address) | |
1537 | goto out_unmap; | |
1538 | ||
1539 | paddr += PAGE_SIZE; | |
1540 | start += PAGE_SIZE; | |
1541 | } | |
1542 | address += offset; | |
1543 | ||
1544 | ADD_STATS_COUNTER(alloced_io_mem, size); | |
1545 | ||
1546 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { | |
1547 | iommu_flush_tlb(iommu, dma_dom->domain.id); | |
1548 | dma_dom->need_flush = false; | |
1549 | } else if (unlikely(iommu_has_npcache(iommu))) | |
1550 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); | |
1551 | ||
1552 | out: | |
1553 | return address; | |
1554 | ||
1555 | out_unmap: | |
1556 | ||
1557 | for (--i; i >= 0; --i) { | |
1558 | start -= PAGE_SIZE; | |
1559 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1560 | } | |
1561 | ||
1562 | dma_ops_free_addresses(dma_dom, address, pages); | |
1563 | ||
1564 | return bad_dma_address; | |
1565 | } | |
1566 | ||
1567 | /* | |
1568 | * Does the reverse of the __map_single function. Must be called with | |
1569 | * the domain lock held too | |
1570 | */ | |
1571 | static void __unmap_single(struct amd_iommu *iommu, | |
1572 | struct dma_ops_domain *dma_dom, | |
1573 | dma_addr_t dma_addr, | |
1574 | size_t size, | |
1575 | int dir) | |
1576 | { | |
1577 | dma_addr_t i, start; | |
1578 | unsigned int pages; | |
1579 | ||
1580 | if ((dma_addr == bad_dma_address) || | |
1581 | (dma_addr + size > dma_dom->aperture_size)) | |
1582 | return; | |
1583 | ||
1584 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); | |
1585 | dma_addr &= PAGE_MASK; | |
1586 | start = dma_addr; | |
1587 | ||
1588 | for (i = 0; i < pages; ++i) { | |
1589 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1590 | start += PAGE_SIZE; | |
1591 | } | |
1592 | ||
1593 | SUB_STATS_COUNTER(alloced_io_mem, size); | |
1594 | ||
1595 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
1596 | ||
1597 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { | |
1598 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); | |
1599 | dma_dom->need_flush = false; | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | /* | |
1604 | * The exported map_single function for dma_ops. | |
1605 | */ | |
1606 | static dma_addr_t map_page(struct device *dev, struct page *page, | |
1607 | unsigned long offset, size_t size, | |
1608 | enum dma_data_direction dir, | |
1609 | struct dma_attrs *attrs) | |
1610 | { | |
1611 | unsigned long flags; | |
1612 | struct amd_iommu *iommu; | |
1613 | struct protection_domain *domain; | |
1614 | u16 devid; | |
1615 | dma_addr_t addr; | |
1616 | u64 dma_mask; | |
1617 | phys_addr_t paddr = page_to_phys(page) + offset; | |
1618 | ||
1619 | INC_STATS_COUNTER(cnt_map_single); | |
1620 | ||
1621 | if (!check_device(dev)) | |
1622 | return bad_dma_address; | |
1623 | ||
1624 | dma_mask = *dev->dma_mask; | |
1625 | ||
1626 | get_device_resources(dev, &iommu, &domain, &devid); | |
1627 | ||
1628 | if (iommu == NULL || domain == NULL) | |
1629 | /* device not handled by any AMD IOMMU */ | |
1630 | return (dma_addr_t)paddr; | |
1631 | ||
1632 | if (!dma_ops_domain(domain)) | |
1633 | return bad_dma_address; | |
1634 | ||
1635 | spin_lock_irqsave(&domain->lock, flags); | |
1636 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, | |
1637 | dma_mask); | |
1638 | if (addr == bad_dma_address) | |
1639 | goto out; | |
1640 | ||
1641 | iommu_completion_wait(iommu); | |
1642 | ||
1643 | out: | |
1644 | spin_unlock_irqrestore(&domain->lock, flags); | |
1645 | ||
1646 | return addr; | |
1647 | } | |
1648 | ||
1649 | /* | |
1650 | * The exported unmap_single function for dma_ops. | |
1651 | */ | |
1652 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, | |
1653 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1654 | { | |
1655 | unsigned long flags; | |
1656 | struct amd_iommu *iommu; | |
1657 | struct protection_domain *domain; | |
1658 | u16 devid; | |
1659 | ||
1660 | INC_STATS_COUNTER(cnt_unmap_single); | |
1661 | ||
1662 | if (!check_device(dev) || | |
1663 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
1664 | /* device not handled by any AMD IOMMU */ | |
1665 | return; | |
1666 | ||
1667 | if (!dma_ops_domain(domain)) | |
1668 | return; | |
1669 | ||
1670 | spin_lock_irqsave(&domain->lock, flags); | |
1671 | ||
1672 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1673 | ||
1674 | iommu_completion_wait(iommu); | |
1675 | ||
1676 | spin_unlock_irqrestore(&domain->lock, flags); | |
1677 | } | |
1678 | ||
1679 | /* | |
1680 | * This is a special map_sg function which is used if we should map a | |
1681 | * device which is not handled by an AMD IOMMU in the system. | |
1682 | */ | |
1683 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, | |
1684 | int nelems, int dir) | |
1685 | { | |
1686 | struct scatterlist *s; | |
1687 | int i; | |
1688 | ||
1689 | for_each_sg(sglist, s, nelems, i) { | |
1690 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1691 | s->dma_length = s->length; | |
1692 | } | |
1693 | ||
1694 | return nelems; | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1699 | * lists). | |
1700 | */ | |
1701 | static int map_sg(struct device *dev, struct scatterlist *sglist, | |
1702 | int nelems, enum dma_data_direction dir, | |
1703 | struct dma_attrs *attrs) | |
1704 | { | |
1705 | unsigned long flags; | |
1706 | struct amd_iommu *iommu; | |
1707 | struct protection_domain *domain; | |
1708 | u16 devid; | |
1709 | int i; | |
1710 | struct scatterlist *s; | |
1711 | phys_addr_t paddr; | |
1712 | int mapped_elems = 0; | |
1713 | u64 dma_mask; | |
1714 | ||
1715 | INC_STATS_COUNTER(cnt_map_sg); | |
1716 | ||
1717 | if (!check_device(dev)) | |
1718 | return 0; | |
1719 | ||
1720 | dma_mask = *dev->dma_mask; | |
1721 | ||
1722 | get_device_resources(dev, &iommu, &domain, &devid); | |
1723 | ||
1724 | if (!iommu || !domain) | |
1725 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1726 | ||
1727 | if (!dma_ops_domain(domain)) | |
1728 | return 0; | |
1729 | ||
1730 | spin_lock_irqsave(&domain->lock, flags); | |
1731 | ||
1732 | for_each_sg(sglist, s, nelems, i) { | |
1733 | paddr = sg_phys(s); | |
1734 | ||
1735 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
1736 | paddr, s->length, dir, false, | |
1737 | dma_mask); | |
1738 | ||
1739 | if (s->dma_address) { | |
1740 | s->dma_length = s->length; | |
1741 | mapped_elems++; | |
1742 | } else | |
1743 | goto unmap; | |
1744 | } | |
1745 | ||
1746 | iommu_completion_wait(iommu); | |
1747 | ||
1748 | out: | |
1749 | spin_unlock_irqrestore(&domain->lock, flags); | |
1750 | ||
1751 | return mapped_elems; | |
1752 | unmap: | |
1753 | for_each_sg(sglist, s, mapped_elems, i) { | |
1754 | if (s->dma_address) | |
1755 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1756 | s->dma_length, dir); | |
1757 | s->dma_address = s->dma_length = 0; | |
1758 | } | |
1759 | ||
1760 | mapped_elems = 0; | |
1761 | ||
1762 | goto out; | |
1763 | } | |
1764 | ||
1765 | /* | |
1766 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1767 | * lists). | |
1768 | */ | |
1769 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, | |
1770 | int nelems, enum dma_data_direction dir, | |
1771 | struct dma_attrs *attrs) | |
1772 | { | |
1773 | unsigned long flags; | |
1774 | struct amd_iommu *iommu; | |
1775 | struct protection_domain *domain; | |
1776 | struct scatterlist *s; | |
1777 | u16 devid; | |
1778 | int i; | |
1779 | ||
1780 | INC_STATS_COUNTER(cnt_unmap_sg); | |
1781 | ||
1782 | if (!check_device(dev) || | |
1783 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
1784 | return; | |
1785 | ||
1786 | if (!dma_ops_domain(domain)) | |
1787 | return; | |
1788 | ||
1789 | spin_lock_irqsave(&domain->lock, flags); | |
1790 | ||
1791 | for_each_sg(sglist, s, nelems, i) { | |
1792 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1793 | s->dma_length, dir); | |
1794 | s->dma_address = s->dma_length = 0; | |
1795 | } | |
1796 | ||
1797 | iommu_completion_wait(iommu); | |
1798 | ||
1799 | spin_unlock_irqrestore(&domain->lock, flags); | |
1800 | } | |
1801 | ||
1802 | /* | |
1803 | * The exported alloc_coherent function for dma_ops. | |
1804 | */ | |
1805 | static void *alloc_coherent(struct device *dev, size_t size, | |
1806 | dma_addr_t *dma_addr, gfp_t flag) | |
1807 | { | |
1808 | unsigned long flags; | |
1809 | void *virt_addr; | |
1810 | struct amd_iommu *iommu; | |
1811 | struct protection_domain *domain; | |
1812 | u16 devid; | |
1813 | phys_addr_t paddr; | |
1814 | u64 dma_mask = dev->coherent_dma_mask; | |
1815 | ||
1816 | INC_STATS_COUNTER(cnt_alloc_coherent); | |
1817 | ||
1818 | if (!check_device(dev)) | |
1819 | return NULL; | |
1820 | ||
1821 | if (!get_device_resources(dev, &iommu, &domain, &devid)) | |
1822 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
1823 | ||
1824 | flag |= __GFP_ZERO; | |
1825 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
1826 | if (!virt_addr) | |
1827 | return NULL; | |
1828 | ||
1829 | paddr = virt_to_phys(virt_addr); | |
1830 | ||
1831 | if (!iommu || !domain) { | |
1832 | *dma_addr = (dma_addr_t)paddr; | |
1833 | return virt_addr; | |
1834 | } | |
1835 | ||
1836 | if (!dma_ops_domain(domain)) | |
1837 | goto out_free; | |
1838 | ||
1839 | if (!dma_mask) | |
1840 | dma_mask = *dev->dma_mask; | |
1841 | ||
1842 | spin_lock_irqsave(&domain->lock, flags); | |
1843 | ||
1844 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
1845 | size, DMA_BIDIRECTIONAL, true, dma_mask); | |
1846 | ||
1847 | if (*dma_addr == bad_dma_address) { | |
1848 | spin_unlock_irqrestore(&domain->lock, flags); | |
1849 | goto out_free; | |
1850 | } | |
1851 | ||
1852 | iommu_completion_wait(iommu); | |
1853 | ||
1854 | spin_unlock_irqrestore(&domain->lock, flags); | |
1855 | ||
1856 | return virt_addr; | |
1857 | ||
1858 | out_free: | |
1859 | ||
1860 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1861 | ||
1862 | return NULL; | |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * The exported free_coherent function for dma_ops. | |
1867 | */ | |
1868 | static void free_coherent(struct device *dev, size_t size, | |
1869 | void *virt_addr, dma_addr_t dma_addr) | |
1870 | { | |
1871 | unsigned long flags; | |
1872 | struct amd_iommu *iommu; | |
1873 | struct protection_domain *domain; | |
1874 | u16 devid; | |
1875 | ||
1876 | INC_STATS_COUNTER(cnt_free_coherent); | |
1877 | ||
1878 | if (!check_device(dev)) | |
1879 | return; | |
1880 | ||
1881 | get_device_resources(dev, &iommu, &domain, &devid); | |
1882 | ||
1883 | if (!iommu || !domain) | |
1884 | goto free_mem; | |
1885 | ||
1886 | if (!dma_ops_domain(domain)) | |
1887 | goto free_mem; | |
1888 | ||
1889 | spin_lock_irqsave(&domain->lock, flags); | |
1890 | ||
1891 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
1892 | ||
1893 | iommu_completion_wait(iommu); | |
1894 | ||
1895 | spin_unlock_irqrestore(&domain->lock, flags); | |
1896 | ||
1897 | free_mem: | |
1898 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1899 | } | |
1900 | ||
1901 | /* | |
1902 | * This function is called by the DMA layer to find out if we can handle a | |
1903 | * particular device. It is part of the dma_ops. | |
1904 | */ | |
1905 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1906 | { | |
1907 | u16 bdf; | |
1908 | struct pci_dev *pcidev; | |
1909 | ||
1910 | /* No device or no PCI device */ | |
1911 | if (!dev || dev->bus != &pci_bus_type) | |
1912 | return 0; | |
1913 | ||
1914 | pcidev = to_pci_dev(dev); | |
1915 | ||
1916 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1917 | ||
1918 | /* Out of our scope? */ | |
1919 | if (bdf > amd_iommu_last_bdf) | |
1920 | return 0; | |
1921 | ||
1922 | return 1; | |
1923 | } | |
1924 | ||
1925 | /* | |
1926 | * The function for pre-allocating protection domains. | |
1927 | * | |
1928 | * If the driver core informs the DMA layer if a driver grabs a device | |
1929 | * we don't need to preallocate the protection domains anymore. | |
1930 | * For now we have to. | |
1931 | */ | |
1932 | static void prealloc_protection_domains(void) | |
1933 | { | |
1934 | struct pci_dev *dev = NULL; | |
1935 | struct dma_ops_domain *dma_dom; | |
1936 | struct amd_iommu *iommu; | |
1937 | u16 devid; | |
1938 | ||
1939 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1940 | devid = calc_devid(dev->bus->number, dev->devfn); | |
1941 | if (devid > amd_iommu_last_bdf) | |
1942 | continue; | |
1943 | devid = amd_iommu_alias_table[devid]; | |
1944 | if (domain_for_device(devid)) | |
1945 | continue; | |
1946 | iommu = amd_iommu_rlookup_table[devid]; | |
1947 | if (!iommu) | |
1948 | continue; | |
1949 | dma_dom = dma_ops_domain_alloc(iommu); | |
1950 | if (!dma_dom) | |
1951 | continue; | |
1952 | init_unity_mappings_for_device(dma_dom, devid); | |
1953 | dma_dom->target_dev = devid; | |
1954 | ||
1955 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
1956 | } | |
1957 | } | |
1958 | ||
1959 | static struct dma_map_ops amd_iommu_dma_ops = { | |
1960 | .alloc_coherent = alloc_coherent, | |
1961 | .free_coherent = free_coherent, | |
1962 | .map_page = map_page, | |
1963 | .unmap_page = unmap_page, | |
1964 | .map_sg = map_sg, | |
1965 | .unmap_sg = unmap_sg, | |
1966 | .dma_supported = amd_iommu_dma_supported, | |
1967 | }; | |
1968 | ||
1969 | /* | |
1970 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1971 | */ | |
1972 | int __init amd_iommu_init_dma_ops(void) | |
1973 | { | |
1974 | struct amd_iommu *iommu; | |
1975 | int ret; | |
1976 | ||
1977 | /* | |
1978 | * first allocate a default protection domain for every IOMMU we | |
1979 | * found in the system. Devices not assigned to any other | |
1980 | * protection domain will be assigned to the default one. | |
1981 | */ | |
1982 | for_each_iommu(iommu) { | |
1983 | iommu->default_dom = dma_ops_domain_alloc(iommu); | |
1984 | if (iommu->default_dom == NULL) | |
1985 | return -ENOMEM; | |
1986 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; | |
1987 | ret = iommu_init_unity_mappings(iommu); | |
1988 | if (ret) | |
1989 | goto free_domains; | |
1990 | } | |
1991 | ||
1992 | /* | |
1993 | * If device isolation is enabled, pre-allocate the protection | |
1994 | * domains for each device. | |
1995 | */ | |
1996 | if (amd_iommu_isolate) | |
1997 | prealloc_protection_domains(); | |
1998 | ||
1999 | iommu_detected = 1; | |
2000 | force_iommu = 1; | |
2001 | bad_dma_address = 0; | |
2002 | #ifdef CONFIG_GART_IOMMU | |
2003 | gart_iommu_aperture_disabled = 1; | |
2004 | gart_iommu_aperture = 0; | |
2005 | #endif | |
2006 | ||
2007 | /* Make the driver finally visible to the drivers */ | |
2008 | dma_ops = &amd_iommu_dma_ops; | |
2009 | ||
2010 | register_iommu(&amd_iommu_ops); | |
2011 | ||
2012 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2013 | ||
2014 | amd_iommu_stats_init(); | |
2015 | ||
2016 | return 0; | |
2017 | ||
2018 | free_domains: | |
2019 | ||
2020 | for_each_iommu(iommu) { | |
2021 | if (iommu->default_dom) | |
2022 | dma_ops_domain_free(iommu->default_dom); | |
2023 | } | |
2024 | ||
2025 | return ret; | |
2026 | } | |
2027 | ||
2028 | /***************************************************************************** | |
2029 | * | |
2030 | * The following functions belong to the exported interface of AMD IOMMU | |
2031 | * | |
2032 | * This interface allows access to lower level functions of the IOMMU | |
2033 | * like protection domain handling and assignement of devices to domains | |
2034 | * which is not possible with the dma_ops interface. | |
2035 | * | |
2036 | *****************************************************************************/ | |
2037 | ||
2038 | static void cleanup_domain(struct protection_domain *domain) | |
2039 | { | |
2040 | unsigned long flags; | |
2041 | u16 devid; | |
2042 | ||
2043 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2044 | ||
2045 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2046 | if (amd_iommu_pd_table[devid] == domain) | |
2047 | __detach_device(domain, devid); | |
2048 | ||
2049 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2050 | } | |
2051 | ||
2052 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2053 | { | |
2054 | struct protection_domain *domain; | |
2055 | ||
2056 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2057 | if (!domain) | |
2058 | return -ENOMEM; | |
2059 | ||
2060 | spin_lock_init(&domain->lock); | |
2061 | domain->mode = PAGE_MODE_3_LEVEL; | |
2062 | domain->id = domain_id_alloc(); | |
2063 | if (!domain->id) | |
2064 | goto out_free; | |
2065 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2066 | if (!domain->pt_root) | |
2067 | goto out_free; | |
2068 | ||
2069 | dom->priv = domain; | |
2070 | ||
2071 | return 0; | |
2072 | ||
2073 | out_free: | |
2074 | kfree(domain); | |
2075 | ||
2076 | return -ENOMEM; | |
2077 | } | |
2078 | ||
2079 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) | |
2080 | { | |
2081 | struct protection_domain *domain = dom->priv; | |
2082 | ||
2083 | if (!domain) | |
2084 | return; | |
2085 | ||
2086 | if (domain->dev_cnt > 0) | |
2087 | cleanup_domain(domain); | |
2088 | ||
2089 | BUG_ON(domain->dev_cnt != 0); | |
2090 | ||
2091 | free_pagetable(domain); | |
2092 | ||
2093 | domain_id_free(domain->id); | |
2094 | ||
2095 | kfree(domain); | |
2096 | ||
2097 | dom->priv = NULL; | |
2098 | } | |
2099 | ||
2100 | static void amd_iommu_detach_device(struct iommu_domain *dom, | |
2101 | struct device *dev) | |
2102 | { | |
2103 | struct protection_domain *domain = dom->priv; | |
2104 | struct amd_iommu *iommu; | |
2105 | struct pci_dev *pdev; | |
2106 | u16 devid; | |
2107 | ||
2108 | if (dev->bus != &pci_bus_type) | |
2109 | return; | |
2110 | ||
2111 | pdev = to_pci_dev(dev); | |
2112 | ||
2113 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2114 | ||
2115 | if (devid > 0) | |
2116 | detach_device(domain, devid); | |
2117 | ||
2118 | iommu = amd_iommu_rlookup_table[devid]; | |
2119 | if (!iommu) | |
2120 | return; | |
2121 | ||
2122 | iommu_queue_inv_dev_entry(iommu, devid); | |
2123 | iommu_completion_wait(iommu); | |
2124 | } | |
2125 | ||
2126 | static int amd_iommu_attach_device(struct iommu_domain *dom, | |
2127 | struct device *dev) | |
2128 | { | |
2129 | struct protection_domain *domain = dom->priv; | |
2130 | struct protection_domain *old_domain; | |
2131 | struct amd_iommu *iommu; | |
2132 | struct pci_dev *pdev; | |
2133 | u16 devid; | |
2134 | ||
2135 | if (dev->bus != &pci_bus_type) | |
2136 | return -EINVAL; | |
2137 | ||
2138 | pdev = to_pci_dev(dev); | |
2139 | ||
2140 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2141 | ||
2142 | if (devid >= amd_iommu_last_bdf || | |
2143 | devid != amd_iommu_alias_table[devid]) | |
2144 | return -EINVAL; | |
2145 | ||
2146 | iommu = amd_iommu_rlookup_table[devid]; | |
2147 | if (!iommu) | |
2148 | return -EINVAL; | |
2149 | ||
2150 | old_domain = domain_for_device(devid); | |
2151 | if (old_domain) | |
2152 | detach_device(old_domain, devid); | |
2153 | ||
2154 | attach_device(iommu, domain, devid); | |
2155 | ||
2156 | iommu_completion_wait(iommu); | |
2157 | ||
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | static int amd_iommu_map_range(struct iommu_domain *dom, | |
2162 | unsigned long iova, phys_addr_t paddr, | |
2163 | size_t size, int iommu_prot) | |
2164 | { | |
2165 | struct protection_domain *domain = dom->priv; | |
2166 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2167 | int prot = 0; | |
2168 | int ret; | |
2169 | ||
2170 | if (iommu_prot & IOMMU_READ) | |
2171 | prot |= IOMMU_PROT_IR; | |
2172 | if (iommu_prot & IOMMU_WRITE) | |
2173 | prot |= IOMMU_PROT_IW; | |
2174 | ||
2175 | iova &= PAGE_MASK; | |
2176 | paddr &= PAGE_MASK; | |
2177 | ||
2178 | for (i = 0; i < npages; ++i) { | |
2179 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2180 | if (ret) | |
2181 | return ret; | |
2182 | ||
2183 | iova += PAGE_SIZE; | |
2184 | paddr += PAGE_SIZE; | |
2185 | } | |
2186 | ||
2187 | return 0; | |
2188 | } | |
2189 | ||
2190 | static void amd_iommu_unmap_range(struct iommu_domain *dom, | |
2191 | unsigned long iova, size_t size) | |
2192 | { | |
2193 | ||
2194 | struct protection_domain *domain = dom->priv; | |
2195 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2196 | ||
2197 | iova &= PAGE_MASK; | |
2198 | ||
2199 | for (i = 0; i < npages; ++i) { | |
2200 | iommu_unmap_page(domain, iova); | |
2201 | iova += PAGE_SIZE; | |
2202 | } | |
2203 | ||
2204 | iommu_flush_domain(domain->id); | |
2205 | } | |
2206 | ||
2207 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, | |
2208 | unsigned long iova) | |
2209 | { | |
2210 | struct protection_domain *domain = dom->priv; | |
2211 | unsigned long offset = iova & ~PAGE_MASK; | |
2212 | phys_addr_t paddr; | |
2213 | u64 *pte; | |
2214 | ||
2215 | pte = fetch_pte(domain, iova); | |
2216 | ||
2217 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
2218 | return 0; | |
2219 | ||
2220 | paddr = *pte & IOMMU_PAGE_MASK; | |
2221 | paddr |= offset; | |
2222 | ||
2223 | return paddr; | |
2224 | } | |
2225 | ||
2226 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, | |
2227 | unsigned long cap) | |
2228 | { | |
2229 | return 0; | |
2230 | } | |
2231 | ||
2232 | static struct iommu_ops amd_iommu_ops = { | |
2233 | .domain_init = amd_iommu_domain_init, | |
2234 | .domain_destroy = amd_iommu_domain_destroy, | |
2235 | .attach_dev = amd_iommu_attach_device, | |
2236 | .detach_dev = amd_iommu_detach_device, | |
2237 | .map = amd_iommu_map_range, | |
2238 | .unmap = amd_iommu_unmap_range, | |
2239 | .iova_to_phys = amd_iommu_iova_to_phys, | |
2240 | .domain_has_cap = amd_iommu_domain_has_cap, | |
2241 | }; | |
2242 |