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1 | /* | |
2 | * Support of MSI, HPET and DMAR interrupts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/mm.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/dmar.h> | |
15 | #include <linux/hpet.h> | |
16 | #include <linux/msi.h> | |
17 | #include <linux/irqdomain.h> | |
18 | #include <asm/msidef.h> | |
19 | #include <asm/hpet.h> | |
20 | #include <asm/hw_irq.h> | |
21 | #include <asm/apic.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
24 | void native_compose_msi_msg(struct pci_dev *pdev, | |
25 | unsigned int irq, unsigned int dest, | |
26 | struct msi_msg *msg, u8 hpet_id) | |
27 | { | |
28 | struct irq_cfg *cfg = irq_cfg(irq); | |
29 | ||
30 | msg->address_hi = MSI_ADDR_BASE_HI; | |
31 | ||
32 | if (x2apic_enabled()) | |
33 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); | |
34 | ||
35 | msg->address_lo = | |
36 | MSI_ADDR_BASE_LO | | |
37 | ((apic->irq_dest_mode == 0) ? | |
38 | MSI_ADDR_DEST_MODE_PHYSICAL : | |
39 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
40 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
41 | MSI_ADDR_REDIRECTION_CPU : | |
42 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
43 | MSI_ADDR_DEST_ID(dest); | |
44 | ||
45 | msg->data = | |
46 | MSI_DATA_TRIGGER_EDGE | | |
47 | MSI_DATA_LEVEL_ASSERT | | |
48 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
49 | MSI_DATA_DELIVERY_FIXED : | |
50 | MSI_DATA_DELIVERY_LOWPRI) | | |
51 | MSI_DATA_VECTOR(cfg->vector); | |
52 | } | |
53 | ||
54 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |
55 | struct msi_msg *msg, u8 hpet_id) | |
56 | { | |
57 | struct irq_cfg *cfg; | |
58 | int err; | |
59 | unsigned dest; | |
60 | ||
61 | if (disable_apic) | |
62 | return -ENXIO; | |
63 | ||
64 | cfg = irq_cfg(irq); | |
65 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | |
66 | if (err) | |
67 | return err; | |
68 | ||
69 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | |
70 | apic->target_cpus(), &dest); | |
71 | if (err) | |
72 | return err; | |
73 | ||
74 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static int | |
80 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
81 | { | |
82 | struct irq_cfg *cfg = irqd_cfg(data); | |
83 | struct msi_msg msg; | |
84 | unsigned int dest; | |
85 | int ret; | |
86 | ||
87 | ret = apic_set_affinity(data, mask, &dest); | |
88 | if (ret) | |
89 | return ret; | |
90 | ||
91 | __get_cached_msi_msg(data->msi_desc, &msg); | |
92 | ||
93 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
94 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
95 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
96 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
97 | ||
98 | __pci_write_msi_msg(data->msi_desc, &msg); | |
99 | ||
100 | return IRQ_SET_MASK_OK_NOCOPY; | |
101 | } | |
102 | ||
103 | /* | |
104 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
105 | * which implement the MSI or MSI-X Capability Structure. | |
106 | */ | |
107 | static struct irq_chip msi_chip = { | |
108 | .name = "PCI-MSI", | |
109 | .irq_unmask = pci_msi_unmask_irq, | |
110 | .irq_mask = pci_msi_mask_irq, | |
111 | .irq_ack = apic_ack_edge, | |
112 | .irq_set_affinity = msi_set_affinity, | |
113 | .irq_retrigger = apic_retrigger_irq, | |
114 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
115 | }; | |
116 | ||
117 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, | |
118 | unsigned int irq_base, unsigned int irq_offset) | |
119 | { | |
120 | struct irq_chip *chip = &msi_chip; | |
121 | struct msi_msg msg; | |
122 | unsigned int irq = irq_base + irq_offset; | |
123 | int ret; | |
124 | ||
125 | ret = msi_compose_msg(dev, irq, &msg, -1); | |
126 | if (ret < 0) | |
127 | return ret; | |
128 | ||
129 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); | |
130 | ||
131 | /* | |
132 | * MSI-X message is written per-IRQ, the offset is always 0. | |
133 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. | |
134 | */ | |
135 | if (!irq_offset) | |
136 | pci_write_msi_msg(irq, &msg); | |
137 | ||
138 | setup_remapped_irq(irq, irq_cfg(irq), chip); | |
139 | ||
140 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
141 | ||
142 | dev_dbg(&dev->dev, "irq %d for MSI/MSI-X\n", irq); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
148 | { | |
149 | struct msi_desc *msidesc; | |
150 | int irq, ret; | |
151 | ||
152 | /* Multiple MSI vectors only supported with interrupt remapping */ | |
153 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
154 | return 1; | |
155 | ||
156 | list_for_each_entry(msidesc, &dev->msi_list, list) { | |
157 | irq = irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL); | |
158 | if (irq <= 0) | |
159 | return -ENOSPC; | |
160 | ||
161 | ret = setup_msi_irq(dev, msidesc, irq, 0); | |
162 | if (ret < 0) { | |
163 | irq_domain_free_irqs(irq, 1); | |
164 | return ret; | |
165 | } | |
166 | ||
167 | } | |
168 | return 0; | |
169 | } | |
170 | ||
171 | void native_teardown_msi_irq(unsigned int irq) | |
172 | { | |
173 | irq_domain_free_irqs(irq, 1); | |
174 | } | |
175 | ||
176 | #ifdef CONFIG_DMAR_TABLE | |
177 | static int | |
178 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
179 | bool force) | |
180 | { | |
181 | struct irq_cfg *cfg = irqd_cfg(data); | |
182 | unsigned int dest, irq = data->irq; | |
183 | struct msi_msg msg; | |
184 | int ret; | |
185 | ||
186 | ret = apic_set_affinity(data, mask, &dest); | |
187 | if (ret) | |
188 | return ret; | |
189 | ||
190 | dmar_msi_read(irq, &msg); | |
191 | ||
192 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
193 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
194 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
195 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
196 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); | |
197 | ||
198 | dmar_msi_write(irq, &msg); | |
199 | ||
200 | return IRQ_SET_MASK_OK_NOCOPY; | |
201 | } | |
202 | ||
203 | static struct irq_chip dmar_msi_type = { | |
204 | .name = "DMAR_MSI", | |
205 | .irq_unmask = dmar_msi_unmask, | |
206 | .irq_mask = dmar_msi_mask, | |
207 | .irq_ack = apic_ack_edge, | |
208 | .irq_set_affinity = dmar_msi_set_affinity, | |
209 | .irq_retrigger = apic_retrigger_irq, | |
210 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
211 | }; | |
212 | ||
213 | int arch_setup_dmar_msi(unsigned int irq) | |
214 | { | |
215 | int ret; | |
216 | struct msi_msg msg; | |
217 | ||
218 | ret = msi_compose_msg(NULL, irq, &msg, -1); | |
219 | if (ret < 0) | |
220 | return ret; | |
221 | dmar_msi_write(irq, &msg); | |
222 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
223 | "edge"); | |
224 | return 0; | |
225 | } | |
226 | #endif | |
227 | ||
228 | /* | |
229 | * MSI message composition | |
230 | */ | |
231 | #ifdef CONFIG_HPET_TIMER | |
232 | ||
233 | static int hpet_msi_set_affinity(struct irq_data *data, | |
234 | const struct cpumask *mask, bool force) | |
235 | { | |
236 | struct irq_cfg *cfg = irqd_cfg(data); | |
237 | struct msi_msg msg; | |
238 | unsigned int dest; | |
239 | int ret; | |
240 | ||
241 | ret = apic_set_affinity(data, mask, &dest); | |
242 | if (ret) | |
243 | return ret; | |
244 | ||
245 | hpet_msi_read(data->handler_data, &msg); | |
246 | ||
247 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
248 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
249 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
250 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
251 | ||
252 | hpet_msi_write(data->handler_data, &msg); | |
253 | ||
254 | return IRQ_SET_MASK_OK_NOCOPY; | |
255 | } | |
256 | ||
257 | static struct irq_chip hpet_msi_type = { | |
258 | .name = "HPET_MSI", | |
259 | .irq_unmask = hpet_msi_unmask, | |
260 | .irq_mask = hpet_msi_mask, | |
261 | .irq_ack = apic_ack_edge, | |
262 | .irq_set_affinity = hpet_msi_set_affinity, | |
263 | .irq_retrigger = apic_retrigger_irq, | |
264 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
265 | }; | |
266 | ||
267 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) | |
268 | { | |
269 | struct irq_chip *chip = &hpet_msi_type; | |
270 | struct msi_msg msg; | |
271 | int ret; | |
272 | ||
273 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
274 | if (ret < 0) | |
275 | return ret; | |
276 | ||
277 | hpet_msi_write(irq_get_handler_data(irq), &msg); | |
278 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); | |
279 | setup_remapped_irq(irq, irq_cfg(irq), chip); | |
280 | ||
281 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
282 | return 0; | |
283 | } | |
284 | #endif |